On 2/3/23 07:25, Philippe Mathieu-Daudé wrote:
On 3/2/23 18:18, Richard Henderson wrote:
'offset' should be bits [23:5] of LDR instruction, rather than [4:0].
Fixes: d59d83a1c388 ("tcg/aarch64: Reorg goto_tb implementation")
Reported-by: Zenghui Yu
Signed-off-by: Richard Henderson
---
tcg/a
On Wed, 2023-02-01 at 14:20 +0100, Pierre Morel wrote:
> > On interception of STSI(15.1.x) the System Information Block
> > (SYSIB) is built from the list of pre-ordered topology entries.
> >
> > Signed-off-by: Pierre Morel
> > ---
> > include/hw/s390x/cpu-topology.h | 22 +++
> > include/hw/s3
On 2/3/23 01:23, Alex Bennée wrote:
Anton Johansson writes:
Hi,
I was running check-tcg with ASan enabled on master, and ran into
the following use-after-free. There appears to be a race between
jump cache invalidation and thread destruction (?)
I thought I'd post here since I noticed some
On 3/2/23 18:18, Richard Henderson wrote:
'offset' should be bits [23:5] of LDR instruction, rather than [4:0].
Fixes: d59d83a1c388 ("tcg/aarch64: Reorg goto_tb implementation")
Reported-by: Zenghui Yu
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c.inc | 2 +-
1 file changed,
Hi Philippe,
On 2/3/23 18:21, Philippe Mathieu-Daudé wrote:
> On 3/2/23 18:15, Eric Auger wrote:
>> After commit 4e4fa6c12d ("accel/tcg: Complete cpu initialization
>> before registration"), it looks the CPUJumpCache handle can be NULL.
>> This causes a SIGSEV when running debug-wp-migration kvm un
On 3/2/23 18:15, Eric Auger wrote:
After commit 4e4fa6c12d ("accel/tcg: Complete cpu initialization
before registration"), it looks the CPUJumpCache handle can be NULL.
This causes a SIGSEV when running debug-wp-migration kvm unit test.
Do you mean commit a976a99a29 ("include/hw/core: Create st
'offset' should be bits [23:5] of LDR instruction, rather than [4:0].
Fixes: d59d83a1c388 ("tcg/aarch64: Reorg goto_tb implementation")
Reported-by: Zenghui Yu
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/t
Many registers whose 'cooked' writefns induce TLB maintenance do
not have raw_writefn ops defined. If only the writefn ops is set
(ie. no raw_writefn is provided), it is assumed the cooked also
work as the raw one. For those registers it is not obvious the
tlb_flush works on KVM mode so better/safe
After commit 4e4fa6c12d ("accel/tcg: Complete cpu initialization
before registration"), it looks the CPUJumpCache handle can be NULL.
This causes a SIGSEV when running debug-wp-migration kvm unit test.
At the first place it should be clarified why this TCG code is called
with KVM acceleration. Thi
On Thu, Jan 26, 2023 at 06:24:31PM +0100, Kevin Wolf wrote:
> bdrv_co_create_opts_simpl() runs in a coroutine. Therefore it is not
simple
> allowed to open images directly. Fix the call to use the corresponding
> no_co_wrapper instead.
>
> Signed-off-by: Kevin Wolf
> ---
> block.c | 4 ++--
>
On 2/3/23 04:00, Vladimir Isaev wrote:
According to spec, ctzw should work with 32-bit register, not 64.
For example, previous implementation returns 33 for (1<<33) input
when the new one returns 32.
Signed-off-by: Vladimir Isaev
---
target/riscv/insn_trans/trans_rvb.c.inc | 9 -
1
Rename 'g' and 'gpe_cpu' variables as 'gpe' to simplify.
No logical change.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/acpi/acpi-cpu-hotplug-stub.c | 6 ++---
hw/acpi/cpu_hotplug.c | 40 -
hw/acpi/ich9.c | 8 +++
hw/acpi/piix4.c
> -Original Message-
> From: Christian Schoenebeck
> Sent: Friday, February 3, 2023 22:41
> To: Greg Kurz ; qemu-devel@nongnu.org
> Cc: Meng, Bin ; Marc-André Lureau
> ; Daniel P. Berrangé ; Shi,
> Guohuai
> Subject: Re: [PATCH v4 04/16] hw/9pfs: Implement Windows specific xxxdir()
> A
ACPI CPU hotplug parent can't be any QOM object, it must be a QDev.
Convert AcpiCpuHotplug::device field as QDev to enforce this.
Rename 'owner' and 'device' variables as 'parent'.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/acpi/acpi-cpu-hotplug-stub.c | 2 +-
hw/acpi/cpu_hotplug.c
To ease code review, rename ACPI CPU hotplug variables
to more meaningful names.
Since hotplug parent can't be any QOM object, and must be
a QDev, convert AcpiCpuHotplug::device from Object* to
DeviceState*.
Philippe Mathieu-Daudé (3):
hw/acpi/cpu_hotplug: Rename gpe_cpu -> gpe
hw/acpi/cpu_ho
No logical change, rename for clarity.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/acpi/acpi-cpu-hotplug-stub.c | 2 +-
hw/acpi/cpu_hotplug.c | 10 +-
hw/acpi/piix4.c | 10 +-
include/hw/acpi/cpu_hotplug.h | 2 +-
4 files changed, 12 insertions(+),
Thomas Huth writes:
> On 02/02/2023 19.59, Alex Bennée wrote:
>> Alex Bennée writes:
>>
>>> A significant portion of our CI logs are just enumerating each
>>> successfully built object file. The current widespread versions of
>>> ninja don't have a quiet option so we use NINJA_STATUS to add a
Richard Henderson writes:
> On 2/2/23 08:59, Alex Bennée wrote:
>>> +- env NINJA_STATUS="[ninja][%f/%t] " ninja | fgrep -v "[ninja]"
>>> - if test -n "$MAKE_CHECK_ARGS";
>>> then
>>> make -j"$JOBS" $MAKE_CHECK_ARGS ;
>> This is too much for gitlab as it trips up on n
On Fri, 3 Feb 2023, Philippe Mathieu-Daudé wrote:
Since now PCI and SysBus properties are identical, unify them.
Suggested-by: BALATON Zoltan
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: BALATON Zoltan
---
hw/display/sm501.c | 11 +++
1 file changed, 3 insertions(+), 8 deleti
On Fri, 3 Feb 2023, Philippe Mathieu-Daudé wrote:
No need to use an intermediate 'dma-offset' property in the
chipset object. Alias the property, so when the machine (here
r2d-plus) sets the value on the chipset, it is propagated to
the OHCI object.
Note we can rename the chipset 'base' property
On Fri, 3 Feb 2023, Philippe Mathieu-Daudé wrote:
Note this device doesn't implement unrealize().
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: BALATON Zoltan
---
hw/display/sm501.c | 17 ++---
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/hw/display/sm501.
Commit 3efa6fa1e62 "hw/loongarch: Add smbios support" enabled
CONFIG_SMBIOS for target loongarch64, by adding
select SMBIOS
to hw/loongarch/Kconfig.
It didn't enable CLI option -smbios in
qemu-options.hx. It's enabled for the other targets that have
CONFIG_SMBIOS.
Was this an oversight? I
Philippe Mathieu-Daudé writes:
> Hi Bastian,
>
> On 3/2/23 15:54, Bastian Koppelmann wrote:
>> since binutils is pretty old, it fails our CI repeatedly during the
>> compilation of tricore-binutils. We created a precompiled version using
>> the debian docker image and download it instead of bui
On Fri, 3 Feb 2023 at 15:44, Thomas Huth wrote:
>
> On 03/02/2023 13.08, Kevin Wolf wrote:
> > Am 03.02.2023 um 12:23 hat Thomas Huth geschrieben:
> >> On 30/01/2023 11.58, Daniel P. Berrangé wrote:
> >>> On Mon, Jan 30, 2023 at 11:44:46AM +0100, Thomas Huth wrote:
> We can get rid of the bui
On 03/02/2023 13.08, Kevin Wolf wrote:
Am 03.02.2023 um 12:23 hat Thomas Huth geschrieben:
On 30/01/2023 11.58, Daniel P. Berrangé wrote:
On Mon, Jan 30, 2023 at 11:44:46AM +0100, Thomas Huth wrote:
We can get rid of the build-coroutine-sigaltstack job by moving
the configure flags that should
On Fri, 2023-02-03 at 15:40 +0100, Pierre Morel wrote:
>
> On 2/3/23 14:22, Nina Schoetterl-Glausch wrote:
> > On Fri, 2023-02-03 at 10:21 +0100, Pierre Morel wrote:
> > >
> > > On 2/2/23 17:42, Nina Schoetterl-Glausch wrote:
> > > > On Wed, 2023-02-01 at 14:20 +0100, Pierre Morel wrote:
> > > >
Hi Phil,
On Fri, Feb 03, 2023 at 04:02:16PM +0100, Philippe Mathieu-Daudé wrote:
> Hi Bastian,
>
> On 3/2/23 15:54, Bastian Koppelmann wrote:
> > since binutils is pretty old, it fails our CI repeatedly during the
> > compilation of tricore-binutils. We created a precompiled version using
> > the
On Fri, 3 Feb 2023 at 08:45, Markus Armbruster wrote:
>
>
> The following changes since commit deabea6e88f7c4c3c12a36ee30051c6209561165:
>
> Merge tag 'for_upstream' of
> https://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging (2023-02-02
> 10:10:07 +)
>
> are available in the Git re
This adds GRAPH_RDLOCK annotations to declare that callers of
bdrv_co_pread*/pwrite*() need to hold a reader lock for the graph.
For some places, we know that they will hold the lock, but we don't have
the GRAPH_RDLOCK annotations yet. In this case, add assume_graph_lock()
with a FIXME comment. Th
From: Emanuele Giuseppe Esposito
This adds GRAPH_RDLOCK annotations to declare that callers of
bdrv_co_is_inserted() need to hold a reader lock for the graph.
blk_is_inserted() is done as a co_wrapper_mixed_bdrv_rdlock (unlike most
other blk_* functions) because it is called a lot from other blk
This adds GRAPH_RDLOCK annotations to declare that callers of
bdrv_driver_*() need to hold a reader lock for the graph. It doesn't add
the annotation to public functions yet.
For some places, we know that they will hold the lock, but we don't have
the GRAPH_RDLOCK annotations yet. In this case, ad
This adds GRAPH_RDLOCK annotations to declare that callers of
bdrv_co_pwrite_zeroes() need to hold a reader lock for the graph.
For some places, we know that they will hold the lock, but we don't have
the GRAPH_RDLOCK annotations yet. In this case, add assume_graph_lock()
with a FIXME comment. The
From: Emanuele Giuseppe Esposito
This adds GRAPH_RDLOCK annotations to declare that callers of
bdrv_co_flush() need to hold a reader lock for the graph.
For some places, we know that they will hold the lock, but we don't have
the GRAPH_RDLOCK annotations yet. In this case, add assume_graph_lock(
This adds GRAPH_RDLOCK annotations to declare that callers of
bdrv_register_buf() and bdrv_unregister_buf() need to hold a reader lock
for the graph.
Signed-off-by: Kevin Wolf
---
include/block/block_int-common.h | 7 ---
block/io.c | 14 ++
2 files changed
This adds GRAPH_RDLOCK annotations to declare that callers of
bdrv_co_create() need to hold a reader lock for the graph.
Signed-off-by: Emanuele Giuseppe Esposito
Signed-off-by: Kevin Wolf
---
include/block/block-global-state.h | 14 ---
include/block/block_int-common.h | 11 +++---
block
This adds GRAPH_RDLOCK annotations to declare that callers of
bdrv_*_dirty_bitmap() need to hold a reader lock for the graph.
Signed-off-by: Kevin Wolf
---
include/block/block-io.h | 14 ++
include/block/block_int-common.h | 6 --
include/block/dirty-bitmap.h | 12 ++
From: Emanuele Giuseppe Esposito
This adds GRAPH_RDLOCK annotations to declare that callers of
bdrv_co_copy_range() need to hold a reader lock for the graph.
Signed-off-by: Emanuele Giuseppe Esposito
Signed-off-by: Kevin Wolf
---
include/block/block-io.h | 9 +
include/block/
This adds GRAPH_RDLOCK annotations to declare that callers of
bdrv_co_block_status() need to hold a reader lock for the graph.
For some places, we know that they will hold the lock, but we don't have
the GRAPH_RDLOCK annotations yet. In this case, add assume_graph_lock()
with a FIXME comment. Thes
This adds GRAPH_RDLOCK annotations to declare that callers of
bdrv_co_ioctl() need to hold a reader lock for the graph.
Signed-off-by: Kevin Wolf
---
include/block/block-io.h | 3 ++-
include/block/block_int-common.h | 9 +
block/block-backend.c| 1 +
block/io.c
From: Emanuele Giuseppe Esposito
This adds GRAPH_RDLOCK annotations to declare that callers of
bdrv_co_pdiscard() need to hold a reader lock for the graph.
For some places, we know that they will hold the lock, but we don't have
the GRAPH_RDLOCK annotations yet. In this case, add assume_graph_lo
From: Emanuele Giuseppe Esposito
This function is called in two different places:
- timer callback, which does not take the graph rdlock.
- bdrv_qed_drain_begin(), which is .bdrv_drain_begin()
callback documented as function that does not take the lock.
Since it calls recursive functions that
bdrv_mirror_top_pwritev() accesses the job object when active mirroring
is enabled. It disables this code during early initialisation while
s->job isn't set yet.
However, s->job is still set way too early when the job object isn't
fully initialised. For example, &s->ops_in_flight isn't initialised
It is never called outside of block.c.
Signed-off-by: Kevin Wolf
---
include/block/block-io.h | 2 --
block.c | 4 ++--
2 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/include/block/block-io.h b/include/block/block-io.h
index 614cbd7eda..f9fa88204d 100644
--- a/in
This adds GRAPH_RDLOCK annotations to declare that callers of
bdrv_co_io_plug() and bdrv_co_io_unplug() need to hold a reader lock for
the graph.
Signed-off-by: Kevin Wolf
---
include/block/block-io.h | 4 ++--
include/block/block_int-common.h | 5 +++--
block/block-backend.c
This adds GRAPH_RDLOCK annotations to declare that callers of
bdrv_co_delete_file() need to hold a reader lock for the graph.
Signed-off-by: Kevin Wolf
---
include/block/block-io.h | 8 ++--
include/block/block_int-common.h | 4 ++--
block.c | 1 +
3 files ch
After introducing the graph lock in a previous series, this series
actually starts making widespread use of it.
Most of the BlockDriver callbacks access the children list in some way,
so you need to hold the graph lock to call them. The patches in this
series add the corresponding GRAPH_RDLOCK ann
This adds GRAPH_RDLOCK annotations to declare that callers of
bdrv_co_truncate() need to hold a reader lock for the graph.
For some places, we know that they will hold the lock, but we don't have
the GRAPH_RDLOCK annotations yet. In this case, add assume_graph_lock()
with a FIXME comment. These pl
This adds GRAPH_RDLOCK annotations to declare that callers of
bdrv_co_refresh_total_sectors() need to hold a reader lock for the
graph.
Signed-off-by: Kevin Wolf
---
include/block/block-io.h | 8
include/block/block_int-common.h | 4 +++-
include/block/block_int-io.h | 7 +++
This adds GRAPH_RDLOCK annotations to declare that callers of
bdrv_co_pwrite_sync() need to hold a reader lock for the graph.
For some places, we know that they will hold the lock, but we don't have
the GRAPH_RDLOCK annotations yet. In this case, add assume_graph_lock()
with a FIXME comment. These
Signed-off-by: Kevin Wolf
---
include/block/block_int-common.h | 12 +++-
include/block/block_int-io.h | 8
block/copy-before-write.c| 6 ++
block/io.c | 2 ++
block/snapshot-access.c | 4 ++--
5 files changed, 17 insertions(+),
This adds GRAPH_RDLOCK annotations to declare that callers of
bdrv_co_eject() and bdrv_co_lock_medium() need to hold a reader lock for
the graph.
Signed-off-by: Emanuele Giuseppe Esposito
Signed-off-by: Kevin Wolf
---
include/block/block-io.h | 7 +--
include/block/block_int-common.
All callers are already GRAPH_RDLOCK, so just add the annotation and
remove assume_graph_lock().
Signed-off-by: Kevin Wolf
---
block/io.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/block/io.c b/block/io.c
index 4ea19a37e6..a56e565b12 100644
--- a/block/io.c
+++ b/
Hi Bastian,
On 3/2/23 15:54, Bastian Koppelmann wrote:
since binutils is pretty old, it fails our CI repeatedly during the
compilation of tricore-binutils. We created a precompiled version using
the debian docker image and download it instead of building it ourself.
Signed-off-by: Bastian Koppe
Some length properties are signed, other unsigned:
hw/mips/cps.c:183:DEFINE_PROP_UINT32("num-vp", MIPSCPSState, num_vp, 1),
hw/mips/cps.c:184:DEFINE_PROP_UINT32("num-irq", MIPSCPSState, num_irq,
256),
hw/misc/mips_cmgcr.c:215:DEFINE_PROP_INT32("num-vp", MIPSGCRState,
num_vps, 1
On Wed, 1 Feb 2023 at 16:04, Kevin Wolf wrote:
>
> The following changes since commit 13356edb87506c148b163b8c7eb0695647d00c2a:
>
> Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into
> staging (2023-01-24 09:45:33 +)
>
> are available in the Git repository at:
>
> htt
Since now PCI and SysBus properties are identical, unify them.
Suggested-by: BALATON Zoltan
Signed-off-by: Philippe Mathieu-Daudé
---
hw/display/sm501.c | 11 +++
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/hw/display/sm501.c b/hw/display/sm501.c
index efebd93f1e..9837
MAL properties are declared as uint8_t:
static Property ppc4xx_mal_properties[] = {
DEFINE_PROP_UINT8("txc-num", Ppc4xxMalState, txcnum, 0),
DEFINE_PROP_UINT8("rxc-num", Ppc4xxMalState, rxcnum, 0),
DEFINE_PROP_END_OF_LIST(),
};
Correct the API use by setting the property usi
Note this device doesn't implement unrealize().
Signed-off-by: Philippe Mathieu-Daudé
---
hw/display/sm501.c | 17 ++---
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/hw/display/sm501.c b/hw/display/sm501.c
index 52e42585af..0f7e09d7e2 100644
--- a/hw/display/sm501.c
No need to use an intermediate 'dma-offset' property in the
chipset object. Alias the property, so when the machine (here
r2d-plus) sets the value on the chipset, it is propagated to
the OHCI object.
Note we can rename the chipset 'base' property as 'dma-offset'
since the object is a non-user-crea
No need to use intermediate 'fec-phy-num' properties in the
SoC object. Alias the properties, so when the machines set
the value on the SoC, it is propagated to the network device
object.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/fsl-imx25.c | 3 +--
hw/arm/fsl-imx6.c
No need to use an intermediate 'flash-size' property in the
SoC object. Alias the property, so when the machine (here
microbit) sets the value on the SoC, it is propagated to
the flash object.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/microbit.c | 5 -
hw/arm/nrf51_soc.c
DEFINE_PROP_DMAADDR() is only used once. Since it doesn't
add much value, simply remove it, along with the header
defining it.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/usb/hcd-ohci-pci.c | 1 -
hw/usb/hcd-ohci.c | 3 +--
include/hw/qdev-dma.h | 16
3 files changed, 1 i
(See commits dc3edf8d8a "Convert to qdev_unrealize() manually"
and 981c3dcd94 "Convert to qdev_unrealize() with Coccinelle").
Reported-by: Markus Armbruster
Signed-off-by: Philippe Mathieu-Daudé
---
linux-user/syscall.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/linu
Avoid when including "hw/usb/hcd-ohci.h":
hw/usb/hcd-ohci.h:100:5: error: unknown type name 'SysBusDevice'
SysBusDevice parent_obj;
^
Reviewed-by: Markus Armbruster
Signed-off-by: Philippe Mathieu-Daudé
---
hw/usb/hcd-ohci.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/
(See commits dc3edf8d8a "Convert to qdev_unrealize() manually"
and 981c3dcd94 "Convert to qdev_unrealize() with Coccinelle").
Reported-by: Markus Armbruster
Signed-off-by: Philippe Mathieu-Daudé
---
hw/pci/pcie_sriov.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/hw
Reviewed-by: Markus Armbruster
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/sgx.c | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/hw/i386/sgx.c b/hw/i386/sgx.c
index db004d17a6..6a729bff94 100644
--- a/hw/i386/sgx.c
+++ b/hw/i386/sgx.c
@@ -285,7 +285,6 @@
Signed-off-by: Philippe Mathieu-Daudé
---
hw/pci/pcie_sriov.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/hw/pci/pcie_sriov.c b/hw/pci/pcie_sriov.c
index f0bd72e069..93b0624599 100644
--- a/hw/pci/pcie_sriov.c
+++ b/hw/pci/pcie_sriov.c
@@ -196,19 +196,17 @@ stat
QOM objects shouldn't access each other internals fields
except using the QOM API.
mips_cps_realize() instantiates a TYPE_MIPS_ITU object, and
directly sets the 'saar' pointer:
if (saar_present) {
s->itu.saar = &env->CP0_SAAR;
}
In order to avoid that, pass the MIPS_CPU object via a
Since v1:
- Addressed Markus & Zoltan review comments
- Introduce/use qdev_unrealize_and_unref()
These patches are extracted from a QOM/QDev refactor series,
so they are preliminary cleanups noticed while working on it:
- Use correct type when calling qdev_prop_set_xxx()
- Unify some qdev propert
Inspired-by: Markus Armbruster
Signed-off-by: Philippe Mathieu-Daudé
---
hw/core/qdev.c | 9 +
include/hw/qdev-core.h | 20
2 files changed, 29 insertions(+)
diff --git a/hw/core/qdev.c b/hw/core/qdev.c
index d759c4602c..b9ef793d51 100644
--- a/hw/core/qdev
since binutils is pretty old, it fails our CI repeatedly during the
compilation of tricore-binutils. We created a precompiled version using
the debian docker image and download it instead of building it ourself.
Signed-off-by: Bastian Koppelmann
---
Peter, I was having trouble with the new versio
On 2/3/23 14:22, Nina Schoetterl-Glausch wrote:
On Fri, 2023-02-03 at 10:21 +0100, Pierre Morel wrote:
On 2/2/23 17:42, Nina Schoetterl-Glausch wrote:
On Wed, 2023-02-01 at 14:20 +0100, Pierre Morel wrote:
The topology information are attributes of the CPU and are
specified during the CPU
On Friday, February 3, 2023 2:34:13 PM CET Shi, Guohuai wrote:
>
> > -Original Message-
> > From: Christian Schoenebeck
> > Sent: Friday, February 3, 2023 20:25
> > To: Greg Kurz ; qemu-devel@nongnu.org
> > Cc: Shi, Guohuai ; Meng, Bin
> > ; Marc-André Lureau ;
> > Daniel P. Berrangé
> >
The AArch32 ATS12NSO* address translation operations are supposed to
trap to either EL2 or EL3 if they're executed at Secure EL1 (which
can only happen if EL3 is AArch64). We implement this, but we got
the syndrome value wrong: like other traps to EL2 or EL3 on an
AArch32 cpreg access, they should
Mark up the sysreg definitons for the registers trapped
by HDFGRTR/HDFGWTR bits 0..11. These cover various debug
related registers.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Tested-by: Fuad Tabba
Message-id: 20230130182459.3309057-15-peter.mayd...@linaro.org
Message-id: 202301
From: Alexander Graf
We currently only support GICv2 emulation. To also support GICv3, we will
need to pass a few system registers into their respective handler functions.
This patch adds support for HVF to call into the TCG callbacks for GICv3
system register handlers. This is safe because the
From: Alexander Graf
Let's explicitly list out all accelerators that we support when trying to
determine the supported set of GIC versions. KVM was already separate, so
the only missing one is HVF which simply reuses all of TCG's emulation
code and thus has the same compatibility matrix.
Signed-
We added the CPAccessResult values CP_ACCESS_TRAP_UNCATEGORIZED_EL2
and CP_ACCESS_TRAP_UNCATEGORIZED_EL3 purely in order to use them in
the ats_access() function, but doing so was incorrect (a bug fixed in
a previous commit). There aren't any cases where we want an access
function to be able to re
From: Richard Henderson
Use the macro instead of two explicit string literals.
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Eric Auger
Message-id: 20230124232059.4017615-1-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
hw/arm/sbsa-ref.c |
The semantics of HSTR_EL2 require that it traps cpreg accesses
to EL2 for:
* EL1 accesses
* EL0 accesses, if the access is not UNDEFINED when the
trap bit is 0
(You can see this in the I_ZFGJP priority ordering, where HSTR_EL2
traps from EL1 to EL2 are priority 12, UNDEFs are priority 13, and
The encodings 0,0,C7,C9,0 and 0,0,C7,C9,1 are AT SP1E1RP and AT
S1E1WP, but our ARMCPRegInfo definitions for them incorrectly name
them AT S1E1R and AT S1E1W (which are entirely different
instructions). Fix the names.
(This has no guest-visible effect as the names are for debug purposes
only.)
S
Define the system registers which are provided by the
FEAT_FGT fine-grained trap architectural feature:
HFGRTR_EL2, HFGWTR_EL2, HDFGRTR_EL2, HDFGWTR_EL2, HFGITR_EL2
All these registers are a set of bit fields, where each bit is set
for a trap and clear to not trap on a particular system register
From: Evgeny Iakovlev
PL011 currently lacks a reset method. Implement it.
Signed-off-by: Evgeny Iakovlev
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20230123162304.26254-4-eiakov...@linux.microsoft.com
Signed-off-by: Peter Maydell
---
hw/char/pl011.c | 26
Mark up the sysreg definitions for the registers trapped
by HFGRTR/HFGWTR bits 36..63.
Of these, some correspond to RAS registers which we implement as
always-UNDEF: these don't need any extra handling for FGT because the
UNDEF-to-EL1 always takes priority over any theoretical
FGT-trap-to-EL2.
Bi
Mark up the sysreg definitions for the system instructions
trapped by HFGITR bits 12..17. These bits cover AT address
translation instructions.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Tested-by: Fuad Tabba
Message-id: 20230130182459.3309057-18-peter.mayd...@linaro.org
Messag
Implement the machinery for fine-grained traps on normal sysregs.
Any sysreg with a fine-grained trap will set the new field to
indicate which FGT register bit it should trap on.
FGT traps only happen when an AArch64 EL2 enables them for
an AArch64 EL1. They therefore are only relevant for AArch32
The HSTR_EL2 register is not supposed to have an effect unless EL2 is
enabled in the current security state. We weren't checking for this,
which meant that if the guest set up the HSTR_EL2 register we would
incorrectly trap even for accesses from Secure EL0 and EL1.
Add the missing checks. (Other
Implement the HFGITR_EL2.ERET fine-grained trap. This traps
execution from AArch64 EL1 of ERET, ERETAA and ERETAB. The trap is
reported with a syndrome value of 0x1a.
The trap must take precedence over a possible pointer-authentication
trap for ERETAA and ERETAB.
Signed-off-by: Peter Maydell
R
Mark up the sysreg definitions for the registers trapped
by HDFGRTR/HDFGWTR bits 12..x.
Bits 12..22 and bit 58 are for PMU registers.
The remaining bits in HDFGRTR/HDFGWTR are for traps on
registers that are part of features we don't implement:
Bits 23..32 and 63 : FEAT_SPE
Bits 33..48 : FEAT_ET
Mark up the sysreg definitions for the system instructions
trapped by HFGITR bits 0..11. These bits cover various
cache maintenance operations.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Tested-by: Fuad Tabba
Message-id: 20230130182459.3309057-17-peter.mayd...@linaro.org
Messag
Update the ID registers for TCG's '-cpu max' to report the
presence of FEAT_FGT Fine-Grained Traps support.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Tested-by: Fuad Tabba
Message-id: 20230130182459.3309057-24-peter.mayd...@linaro.org
Message-id: 20230127175507.2895013-24-pete
From: Marcin Juszkiewicz
Cortex-A76 supports 40bits of address space. sbsa-ref's memory
starts above this limit.
Signed-off-by: Marcin Juszkiewicz
Reviewed-by: Alex Bennée
Reviewed-by: Richard Henderson
Message-id: 20230126114416.2447685-1-marcin.juszkiew...@linaro.org
Signed-off-by: Peter Ma
Mark up the sysreg definitions for the registers trapped
by HFGRTR/HFGWTR bits 0..11.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Tested-by: Fuad Tabba
Message-id: 20230130182459.3309057-11-peter.mayd...@linaro.org
Message-id: 20230127175507.2895013-11-peter.mayd...@linaro.org
-
From: Evgeny Iakovlev
PL011 can be in either of 2 modes depending guest config: FIFO and
single register. The last mode could be viewed as a 1-element-deep FIFO.
Current code open-codes a bunch of depth-dependent logic. Refactor FIFO
depth handling code to isolate calculating current FIFO depth.
Mark up the sysreg definitions for the system instructions
trapped by HFGITR bits 48..63.
Some of these bits are for trapping instructions which are
not in the system instruction encoding (i.e. which are
not handled by the ARMCPRegInfo mechanism):
* ERET, ERETAA, ERETAB
* SVC
We will have to ha
Rearrange the code in do_coproc_insn() so that we calculate the
syndrome value for a potential trap early; we're about to add a
second check that wants this value earlier than where it is currently
determined.
(Specifically, a trap to EL2 because of HSTR_EL2 should take
priority over an UNDEF to E
Mark up the sysreg definitions for the system instructions
trapped by HFGITR bits 18..47. These bits cover TLBI
TLB maintenance instructions.
(If we implemented FEAT_XS we would need to trap some of the
instructions added by that feature using these bits; but we don't
yet, so will need to add the
Implement the HFGITR_EL2.SVC_EL0 and SVC_EL1 fine-grained traps.
These trap execution of the SVC instruction from AArch32 and AArch64.
(As usual, AArch32 can only trap from EL0, as fine grained traps are
disabled with an AArch32 EL1.)
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
T
From: Evgeny Iakovlev
Current FIFO handling code does not reset RXFE/RXFF flags when guest
resets FIFO by writing to UARTLCR register, although internal FIFO state
is reset to 0 read count. Actual guest-visible flag update will happen
only on next data read or write attempt. As a result of that a
FEAT_FGT also implements an extra trap bit in the MDCR_EL2 and
MDCR_EL3 registers: bit TDCC enables trapping of use of the Debug
Comms Channel registers OSDTRRX_EL1, OSDTRTX_EL1, MDCCSR_EL0,
MDCCINT_EL0, DBGDTR_EL0, DBGDTRRX_EL0 and DBGDTRTX_EL0 (and their
AArch32 equivalents). This trapping is in
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