[PATCH v2] target/riscv: fix ctzw behavior

According to spec, ctzw should work with 32-bit register, not 64. For example, previous implementation returns 33 for (1<<33) input when the new one returns 32. Signed-off-by: Vladimir Isaev Suggested-by: Richard Henderson --- v2: - Use simpler solution suggested by Richard Henderson --- ta

Re: [PULL 00/26] Next patches

On Thu, 2 Feb 2023 at 16:07, Juan Quintela wrote: > > The following changes since commit deabea6e88f7c4c3c12a36ee30051c6209561165: > > Merge tag 'for_upstream' of > https://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging (2023-02-02 > 10:10:07 +) > > are available in the Git reposito

Re: [PATCH 6/6] gitlab-ci.d/buildtest: Disintegrate the build-coroutine-sigaltstack job

On Fri, 3 Feb 2023 at 21:14, Juan Quintela wrote: > > Peter Maydell wrote: > > The migration tests have been flaky for a while now, > > including setups where host and guest page sizes are the same. > > (For instance, my x86 macos box pretty reliably sees failures > > when the machine is under lo

Re: [RFC v2 12/13] vdpa: preemptive kick at enable

On 2/2/2023 8:53 AM, Eugenio Perez Martin wrote: On Thu, Feb 2, 2023 at 1:57 AM Si-Wei Liu wrote: On 1/13/2023 1:06 AM, Eugenio Perez Martin wrote: On Fri, Jan 13, 2023 at 4:39 AM Jason Wang wrote: On Fri, Jan 13, 2023 at 11:25 AM Zhu, Lingshan wrote: On 1/13/2023 10:31 AM, Jason Wan

Re: [PATCH v4 3/4] qapi: Update flake8 config

John Snow writes: > New versions of flake8 don't like same-line comments. (It's a version > newer than what fc37 ships, but it still makes my life easier to fix it > now.) > > Signed-off-by: John Snow > --- > scripts/qapi/.flake8 | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > dif

[PATCH] configure: normalize riscv* cpu types too

For most CPU types out there, ./configure normalizes all variations into base form plus, optionally, variations, to find the proper arch-specific code. In particular, it's possible to use ./configure --cpu=$(uname -m) and it will figure out the right base cpu family out of that. But this does n

Re: [PATCH v4 4/4] qapi: update pylint configuration

John Snow writes: > Newer versions of pylint disable the "no-self-use" message by > default. Older versions don't, though. If we leave the suppressions in, > pylint yelps about useless options. Just tell pylint to shush. > > Signed-off-by: John Snow > --- > scripts/qapi/pylintrc | 1 + > 1 file

Re: [PATCH] tcg/aarch64: Fix patching of LDR in tb_target_set_jmp_target

On 2023/2/4 1:18, Richard Henderson wrote: 'offset' should be bits [23:5] of LDR instruction, rather than [4:0]. Fixes: d59d83a1c388 ("tcg/aarch64: Reorg goto_tb implementation") Reported-by: Zenghui Yu Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 2 +- 1 file changed,

Re: [PATCH v10 1/3] hw/riscv: handle 32 bit CPUs kernel_addr in riscv_load_kernel()

On Sat, Feb 4, 2023 at 7:01 AM Daniel Henrique Barboza wrote: > > Hey, > > On 2/3/23 07:45, Bin Meng wrote: > > Hi Daniel, > > > > On Fri, Feb 3, 2023 at 6:31 PM Daniel Henrique Barboza > > wrote: > >> > >> > >> > >> On 2/3/23 02:39, Bin Meng wrote: > >>> On Thu, Feb 2, 2023 at 9:58 PM Daniel Hen

Re: ASan reports use-after-free when running munmap-pthread

On 2/3/23 22:18, Richard Henderson wrote: The fix for this was merged today: 4731f89b3b cpu: free cpu->tb_jmp_cache with RCU I'd forgotten about this, since the pull request was pending for some time, while we waited for CI minutes to refresh. r~ Ah that's great, thanks for taking a lo

Re: [RFC PATCH 12/19] hw/i386: Set QDev properties using QDev API

Am 3. Februar 2023 18:09:07 UTC schrieb "Philippe Mathieu-Daudé" : >No need to use the low-level QOM API when an object >inherits from QDev. Directly use the QDev API to set >its properties. > >Signed-off-by: Philippe Mathieu-Daudé >--- > hw/i386/pc.c | 8 +++- > hw/i386/pc_q35.c

Re: [PULL v2 00/35] Monitor patches for 2023-02-03

On Sat, 4 Feb 2023 at 07:21, Markus Armbruster wrote: > > The following changes since commit deabea6e88f7c4c3c12a36ee30051c6209561165: > > Merge tag 'for_upstream' of > https://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging (2023-02-02 > 10:10:07 +) > > are available in the Git repo

Re: [PULL 00/11] Net patches

On Thu, 2 Feb 2023 at 06:21, Jason Wang wrote: > > The following changes since commit 13356edb87506c148b163b8c7eb0695647d00c2a: > > Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into > staging (2023-01-24 09:45:33 +) > > are available in the git repository at: > > htt

Re: [PATCH] configure: normalize riscv* cpu types too

On Sat, 4 Feb 2023 at 11:26, Michael Tokarev wrote: > > For most CPU types out there, ./configure normalizes all > variations into base form plus, optionally, variations, > to find the proper arch-specific code. In particular, > it's possible to use >./configure --cpu=$(uname -m) > and it wil

[PATCH v3 1/9] hw/pci-host/i440fx: Inline sysbus_add_io()

sysbus_add_io() just wraps memory_region_add_subregion() while also obscuring where the memory is attached. So use memory_region_add_subregion() directly and attach it to the existing memory region s->bus->address_space_io which is set as an alias to get_system_io() by the pc machine. Signed-off-b

[PATCH v3 5/9] hw/i386/pc_{q35, piix}: Minimize usage of get_system_memory()

Signed-off-by: Bernhard Beschow Reviewed-by: Thomas Huth --- hw/i386/pc_piix.c | 2 +- hw/i386/pc_q35.c | 7 --- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index ee9d9a4175..5bde4533cc 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_

[PATCH v3 2/9] hw/pci-host/q35: Inline sysbus_add_io()

sysbus_add_io() just wraps memory_region_add_subregion() while also obscuring where the memory is attached. So use memory_region_add_subregion() directly and attach it to the existing memory region s->mch.address_space_io which is set as an alias to get_system_io() by the q35 machine. Signed-off-b

[PATCH v3 8/9] hw/i386/x86: Make TYPE_X86_MACHINE the owner of smram

Treat the smram MemoryRegion analoguous to other memory regions such as ram, pci, io, ... , making the used memory regions more explicit when instantiating q35 or i440fx. Note that the q35 device uses these memory regions only during the realize phase which suggests that it shouldn't be the owner

[PATCH v3 3/9] hw/i386/pc_q35: Reuse machine parameter

Signed-off-by: Bernhard Beschow Reviewed-by: Thomas Huth --- hw/i386/pc_q35.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 66cd718b70..dee2b38474 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -218,7 +218,7 @@ static void

[PATCH v3 7/9] hw/pci-host/pam: Make init_pam() usage more readable

Unlike pam_update() which takes the subject -- PAMMemoryRegion -- as first argument, init_pam() takes it as fifth (!) argument. This makes it quite hard to figure out what an init_pam() invocation actually initializes. By moving the subject to the front this should become clearer. While at it, low

[PATCH v3 9/9] target/i386/tcg/sysemu/tcg-cpu: Avoid own opinion about smram size

When setting up the CPU's smram memory region alias, the code currently assumes that the smram size is 4 GiB. While this is true, it repeats a decision made elsewhere which seems redundant and prone to inconsistencies. Avoid this by reusing whatever size the smram region was set to. Signed-off-by:

[PATCH v3 4/9] hw/i386/pc_{q35, piix}: Reuse MachineClass::desc as SMB product name

No need to repeat the descriptions. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth --- hw/i386/pc_piix.c | 2 +- hw/i386/pc_q35.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index df

[PATCH v3 0/9] PC cleanups

This series contains some cleanups I came across when working on the PC machines. It consists of reducing the usage of global variables and eliminating some redundancies. One notable change is that the SMRAM memory region gets moved from the i440fx and q35 host bridges into the x86 machine. This w

[PATCH v3 6/9] hw/i386/pc: Initialize ram_memory variable directly

Going through pc_memory_init() seems quite complicated for a simple assignment. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé --- include/hw/i386/pc.h | 1 - hw/i386/pc.c | 2 -- hw/i386/pc_piix.c| 4 ++-- hw/i386/pc_q35.c | 5 ++--- 4 files changed, 4 inse

Re: [PATCH] configure: normalize riscv* cpu types too

04.02.2023 18:05, Peter Maydell пишет: On Sat, 4 Feb 2023 at 11:26, Michael Tokarev wrote: For most CPU types out there, ./configure normalizes all variations into base form plus, optionally, variations, to find the proper arch-specific code. In particular, it's possible to use ./configur

Re: [PATCH v3 6/9] hw/i386/pc: Initialize ram_memory variable directly

On Sat, 4 Feb 2023, Bernhard Beschow wrote: Going through pc_memory_init() seems quite complicated for a simple assignment. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé --- include/hw/i386/pc.h | 1 - hw/i386/pc.c | 2 -- hw/i386/pc_piix.c| 4 ++-- hw/i386/pc_q3

pixman_blt on aarch64

Hello, I'm trying to involve the pixman list in this thread on qemu-devel list started with subject "Display update issue on M1 Macs". See here: https://lists.nongnu.org/archive/html/qemu-devel/2023-02/msg01033.html We have found that on aarch64 Macs running macOS the pixman_blt and pixman_f

[PULL 13/22] linux-user: Improve strace output of getgroups() and setgroups()

From: Helge Deller Make the strace look nicer for those syscalls. Signed-off-by: Helge Deller Reviewed-by: Laurent Vivier Message-Id: <20230115210057.445132-1-del...@gmx.de> Signed-off-by: Laurent Vivier --- linux-user/strace.list | 8 1 file changed, 4 insertions(+), 4 deletions(-)

[PULL 14/22] linux-user: move target_flat.h to target subdirs

From: Mike Frysinger This makes target_flat.h behave like every other target_xxx.h header. It also makes it actually work -- while the current header says adding a header to the target subdir overrides the common one, it doesn't. This is for two reasons: * meson.build adds -Ilinux-user before -Il

[PULL 00/22] Linux user for 8.0 patches

x-user-for-8.0-pull-request for you to fetch changes up to 3f0744f98b07c6fd2ce9d5840726d0915b2ae7c1: linux-user: Allow sendmsg() without IOV (2023-02-03 22:55:12 +0100) linux-user branch pull request 20230204 Implement execveat()

[PULL 21/22] linux-user: Implement SOL_ALG encryption support

From: Helge Deller Add suport to handle SOL_ALG packets via sendmsg() and recvmsg(). This allows emulated userspace to use encryption functionality. Tested with the debian ell package with hppa guest on x86_64 host. Signed-off-by: Helge Deller Reviewed-by: Laurent Vivier Message-Id: <20221212

[PULL 01/22] linux-user/strace: Constify struct flags

From: Philippe Mathieu-Daudé print_flags() takes a const pointer. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Laurent Vivier Message-Id: <20221104173632.1052-2-phi...@linaro.org> Signed-off-by: Laurent Vivier --- linux-user/strace.c | 40 1 fil

[PULL 10/22] Revert "linux-user: add more compat ioctl definitions"

From: Daniel P. Berrangé This reverts commit c5495f4ecb0cdaaf2e9dddeb48f1689cdb520ca0. glibc has fixed (in 2.36.9000-40-g774058d729) the problem that caused a clash when both sys/mount.h annd linux/mount.h are included, and backported this to the 2.36 stable release too: https://sourceware.o

[PULL 11/22] Revert "linux-user: fix compat with glibc >= 2.36 sys/mount.h"

From: Daniel P. Berrangé This reverts commit 3cd3df2a9584e6f753bb62a0028bd67124ab5532. glibc has fixed (in 2.36.9000-40-g774058d729) the problem that caused a clash when both sys/mount.h annd linux/mount.h are included, and backported this to the 2.36 stable release too: https://sourceware.o

[PULL 20/22] linux-user: Enhance strace output for various syscalls

From: Helge Deller Add appropriate strace printf formats for various Linux syscalls. Signed-off-by: Helge Deller Reviewed-by: Philippe Mathieu-Daudé Message-Id: Signed-off-by: Laurent Vivier --- linux-user/strace.list | 43 ++ 1 file changed, 23 inser

[PULL 05/22] linux-user/syscall: Implement execveat()

From: Drew DeVault References: https://gitlab.com/qemu-project/qemu/-/issues/1007 Signed-off-by: Drew DeVault Reviewed-by: Laurent Vivier Message-Id: <20221104081015.706009-1-...@cmpwn.com> Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20221104173632.1052-6-phi...@linaro.org> Signed-off-b

[PULL 22/22] linux-user: Allow sendmsg() without IOV

From: Helge Deller Applications do call sendmsg() without any IOV, e.g.: sendmsg(4, {msg_name=NULL, msg_namelen=0, msg_iov=NULL, msg_iovlen=0, msg_control=[{cmsg_len=36, cmsg_level=SOL_ALG, cmsg_type=0x2}], msg_controllen=40, msg_flags=0}, MSG_MORE) = 0 sendmsg(4, {msg_n

[PULL 04/22] linux-user/syscall: Extract do_execve() from do_syscall1()

From: Drew DeVault execve() is a particular case of execveat(). In order to add do_execveat(), first factor do_execve() out. Signed-off-by: Drew DeVault Message-Id: <20221104081015.706009-1-...@cmpwn.com> [PMD: Split of bigger patch, filled description, fixed style] Signed-off-by: Philippe Math

[PULL 08/22] linux-user: fix strace build w/out munlockall

From: Mike Frysinger Signed-off-by: Mike Frysinger Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20230118090144.31155-1-vap...@gentoo.org> Signed-off-by: Laurent Vivier --- linux-user/strace.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/linux-user/strace.c b/linu

[PULL 07/22] linux-user: un-parent OBJECT(cpu) when closing thread

From: Richard Henderson This reinstates commit 52f0c1607671293afcdb2acc2f83e9bccbfa74bb: While forcing the CPU to unrealize by hand does trigger the clean-up code we never fully free resources because refcount never reaches zero. This is because QOM automatically added objects without an explici

[PULL 18/22] linux-user: Add emulation for MADV_WIPEONFORK and MADV_KEEPONFORK in madvise()

From: Helge Deller Both parameters have a different value on the parisc platform, so first translate the target value into a host value for usage in the native madvise() syscall. Those parameters are often used by security sensitive applications (e.g. tor browser, boringssl, ...) which expect th

[PULL 09/22] linux-user: add more netlink protocol constants

From: Letu Ren Currently, qemu strace only prints four protocol contants. This patch adds others listed in "linux/netlink.h". Signed-off-by: Letu Ren Message-Id: <20230101141105.12024-1-fantasq...@gmail.com> Signed-off-by: Laurent Vivier --- linux-user/strace.c | 48 ++

[PULL 15/22] linux-user: Fix SO_ERROR return code of getsockopt()

From: Helge Deller Add translation for the host error return code of: getsockopt(19, SOL_SOCKET, SO_ERROR, [ECONNREFUSED], [4]) = 0 This fixes the testsuite of the cockpit debian package with a hppa-linux guest on a x86-64 host. Signed-off-by: Helge Deller Reviewed-by: Richard Henderson R

[PULL 06/22] linux-user: Add missing MAP_HUGETLB and MAP_STACK flags in strace

From: Helge Deller Add two missing mmap flags. Signed-off-by: Helge Deller Reviewed-by: Laurent Vivier Message-Id: Signed-off-by: Laurent Vivier --- linux-user/strace.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/linux-user/strace.c b/linux-user/strace.c index 7bccb4f0c067..50272

[PULL 19/22] linux-user: Show 4th argument of rt_sigprocmask() in strace

From: Helge Deller Add output for the missing 4th parameter (size_t sigsetsize). Signed-off-by: Helge Deller Reviewed-by: Richard Henderson Reviewed-by: Laurent Vivier Message-Id: Signed-off-by: Laurent Vivier --- linux-user/strace.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)

[PULL 12/22] linux-user: Add strace output for clock_getres_time64() and futex_time64()

From: Helge Deller Add the two syscalls to strace output to avoid "Unknown syscall" message. Signed-off-by: Helge Deller Reviewed-by: Laurent Vivier Message-Id: <20230115113517.25143-1-del...@gmx.de> Signed-off-by: Laurent Vivier --- linux-user/strace.list | 6 ++ 1 file changed, 6 inser

[PULL 17/22] linux-user: Improve strace output of personality() and sysinfo()

From: Helge Deller Make the strace look nicer for those two syscalls. Signed-off-by: Helge Deller Reviewed-by: Richard Henderson Reviewed-by: Laurent Vivier Message-Id: Signed-off-by: Laurent Vivier --- linux-user/strace.list | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff

[PULL 02/22] linux-user/strace: Extract print_execve_argv() from print_execve()

From: Drew DeVault In order to add print_execveat() which re-use common code from print_execve(), extract print_execve_argv() from it. Signed-off-by: Drew DeVault Message-Id: <20221104081015.706009-1-...@cmpwn.com> [PMD: Split of bigger patch, filled description, fixed style] Signed-off-by: Phi

[PULL 03/22] linux-user/strace: Add output for execveat() syscall

From: Drew DeVault Signed-off-by: Drew DeVault Message-Id: <20221104081015.706009-1-...@cmpwn.com> Suggested-by: Helge Deller [PMD: Split of bigger patch] Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Laurent Vivier Message-Id: <20221104173632.1052-4-phi...@linaro.org> Signed-off-by: Lau

[PULL 16/22] linux-user: Fix /proc/cpuinfo output for hppa

From: Helge Deller The hppa architectures provides an own output for the emulated /proc/cpuinfo file. Some userspace applications count (even if that's not the recommended way) the number of lines which start with "processor:" and assume that this number then reflects the number of online CPUs.

[PATCH] KVM: dirty ring: check if vcpu is created before dirty_ring_reap_one

From: Weinan Liu Failed to assert '(dirty_gfns && ring_size)' in kvm_dirty_ring_reap_one if the vcpu has not been finished to create yet. This bug occasionally occurs when I open 200+ qemu instances on my 16G 6-cores x86 machine. And it must be triggered if inserting a 'sleep(10)' into kvm_vcpu_t

[PULL 32/40] target/s390x: Copy wout_x1 to wout_x1_P

Make a copy of wout_x1 before modifying it, as wout_x1_P emphasizing that it operates on the out/out2 pair. The insns that use x1_P are data movement that will not change to Int128. Acked-by: Ilya Leoshkevich Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/s390

[PULL 24/40] tests/tcg/s390x: Add clst.c

From: Ilya Leoshkevich Add a basic test to prevent regressions. Signed-off-by: Ilya Leoshkevich Message-Id: <20221025213008.2209006-2-...@linux.ibm.com> Signed-off-by: Richard Henderson --- tests/tcg/s390x/clst.c | 82 + tests/tcg/s390x/Makefile.target

[PULL 06/40] tcg: Introduce tcg_out_addi_ptr

Implement the function for arm, i386, and s390x, which will use it. Add stubs for all other backends. Reviewed-by: Alex Bennée Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- tcg/tcg.c| 2 ++ tcg/aarch64/tcg-target.c.inc | 7 +++ tcg/

[PULL 27/40] target/s390x: Use a single return for helper_divs32/u32

Pack the quotient and remainder into a single uint64_t. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- v2: Fix operand ordering; use tcg_extr32_i64. --- target/s390x/helper.h | 2 +- target/s390x/tcg/int_helper.c | 26 ++

[PULL 28/40] target/s390x: Use a single return for helper_divs64/u64

Pack the quotient and remainder into a single Int128. Use the divu128 primitive to remove the cpu_abort on 32-bit hosts. Reviewed-by: Philippe Mathieu-Daudé Acked-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- v2: Extended div test case to cover these insns. --- target/s390x/helper.

[PULL 29/40] target/s390x: Use Int128 for return from CLST

Reviewed-by: Philippe Mathieu-Daudé Acked-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/helper.h | 2 +- target/s390x/tcg/mem_helper.c | 11 --- target/s390x/tcg/translate.c | 8 ++-- 3 files changed, 11 insertions(+), 10 deletions(-) diff --git

[PULL 22/40] target/ppc: Use tcg_gen_atomic_cmpxchg_i128 for STQCX

Note that the previous direct reference to reserve_val, - tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode -? offsetof(CPUPPCState, reserve_val2) -: offsetof(CPUPPCState, reserve_val))); was incorrect because all references should have go

[PULL 34/40] target/s390x: Use Int128 for passing float128

Acked-by: David Hildenbrand Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- v2: Fix SPEC_in1_x1. --- target/s390x/helper.h| 32 ++-- target/s390x/tcg/insn-data.h.inc | 30 +-- target/s390x/tcg/fpu_helper.c| 88 ++--

[PULL 23/40] tests/tcg/s390x: Add div.c

From: Ilya Leoshkevich Add a basic test to prevent regressions. Signed-off-by: Ilya Leoshkevich Message-Id: <2022110300.2539919-1-...@linux.ibm.com> Signed-off-by: Richard Henderson --- tests/tcg/s390x/div.c | 40 + tests/tcg/s390x/Makefile.target

[PULL 05/40] tcg: Allocate objects contiguously in temp_allocate_frame

When allocating a temp to the stack frame, consider the base type and allocate all parts at once. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/tcg.c | 34 ++ 1 file changed, 26 insertions(+), 8 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c

[PULL 07/40] tcg: Add TCG_CALL_{RET,ARG}_BY_REF

These will be used by some hosts, both 32 and 64-bit, to pass and return i128. Not yet used, because allocation is not yet enabled. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/tcg-internal.h | 3 + tcg/tcg.c | 135 -

[PULL 25/40] tests/tcg/s390x: Add long-double.c

Acked-by: Ilya Leoshkevich Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tests/tcg/s390x/long-double.c | 24 tests/tcg/s390x/Makefile.target | 1 + 2 files changed, 25 insertions(+) create mode 100644 tests/tcg/s390x/long-double.c diff --

[PULL 18/40] tcg: Add tcg_gen_{non}atomic_cmpxchg_i128

This will allow targets to avoid rolling their own. Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- accel/tcg/tcg-runtime.h | 11 + include/tcg/tcg-op.h | 5 +++ tcg/tcg-op.c | 85 +++

[PULL 19/40] tcg: Split out tcg_gen_nonatomic_cmpxchg_i{32,64}

Normally this is automatically handled by the CF_PARALLEL checks with in tcg_gen_atomic_cmpxchg_i{32,64}, but x86 has a special case of !PREFIX_LOCK where it always wants the non-atomic version. Split these out so that x86 does not have to roll its own. Reviewed-by: Alex Bennée Signed-off-by: Ri

[PULL 20/40] target/arm: Use tcg_gen_atomic_cmpxchg_i128 for STXP

Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-Id: <20221112042555.2622152-2-richard.hender...@linaro.org> --- target/arm/helper-a64.h| 6 --- target/arm/helper-a64.c| 104 - target/arm/translate-a64.c | 60 -

[PULL 38/40] target/i386: Inline cmpxchg8b

Use tcg_gen_atomic_cmpxchg_i64 for the atomic case, and tcg_gen_nonatomic_cmpxchg_i64 otherwise. Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/i386/helper.h | 2 -- target/i386/tcg/mem_helper.c | 57 ---

[PULL 09/40] tcg: Add TCG_CALL_RET_BY_VEC

This will be used by _WIN64 to return i128. Not yet used, because allocation is not yet enabled. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/tcg-internal.h | 1 + tcg/tcg.c | 19 +++ 2 files changed, 20 insertions(+) diff --git a/tcg/tcg-interna

[PULL 37/40] target/i386: Split out gen_cmpxchg8b, gen_cmpxchg16b

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 48 - 1 file changed, 31 insertions(+), 17 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 7e0b2a709a..a82131d635

[PULL 35/40] target/s390x: Use tcg_gen_atomic_cmpxchg_i128 for CDSG

Acked-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/helper.h| 2 -- target/s390x/tcg/insn-data.h.inc | 2 +- target/s390x/tcg/mem_helper.c| 52 -- target/s390x/tcg/translate.c | 55 +++- 4 file

[PULL 12/40] tcg/tci: Fix big-endian return register ordering

We expect the backend to require register pairs in host-endian ordering, thus for big-endian the first register of a pair contains the high part. We were forcing R0 to contain the low part for calls. Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson -

[PULL 15/40] tcg: Add temp allocation for TCGv_i128

This enables allocation of i128. The type is not yet usable, as we have not yet added data movement ops. Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 32 + tcg/tcg.c | 60 +

[PULL 17/40] tcg: Add guest load/store primitives for TCGv_i128

These are not yet considering atomicity of the 16-byte value; this is a direct replacement for the current target code which uses a pair of 8-byte operations. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- include/exec/cpu_ldst.h | 10 +++ include/tcg/tcg-op.h| 2 + accel/

[PULL 04/40] tcg: Handle dh_typecode_i128 with TCG_CALL_{RET, ARG}_NORMAL

Many hosts pass and return 128-bit quantities like sequential 64-bit quantities. Treat this just like we currently break down 64-bit quantities for a 32-bit host. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/tcg.c | 37 + 1 file changed,

[PULL 21/40] target/arm: Use tcg_gen_atomic_cmpxchg_i128 for CASP

Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-Id: <20221112042555.2622152-3-richard.hender...@linaro.org> --- target/arm/helper-a64.h| 2 -- target/arm/helper-a64.c| 43 --- target/arm/translate-a64.c | 61 +++

[PULL 14/40] tcg: Add TCG_TARGET_CALL_{RET,ARG}_I128

Fill in the parameters for the host ABI for Int128 for those backends which require no extra modification. Reviewed-by: Alex Bennée Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 2 ++ tcg/arm/tcg-target.h | 2 ++ tcg/loongarch6

[PULL 11/40] tcg/i386: Add TCG_TARGET_CALL_{RET,ARG}_I128

Fill in the parameters for the host ABI for Int128. Adjust tcg_target_call_oarg_reg for _WIN64, and tcg_out_call for i386 sysv. Allow TCG_TYPE_V128 stores without AVX enabled. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 10 ++ tcg/i386/tcg-

[PULL 08/40] tcg: Introduce tcg_target_call_oarg_reg

Replace the flat array tcg_target_call_oarg_regs[] with a function call including the TCGCallReturnKind. Extend the set of registers for ARM to r0-r3 to match the ABI: https://github.com/ARM-software/abi-aa/blob/main/aapcs32/aapcs32.rst#result-return Reviewed-by: Alex Bennée Reviewed-by: Daniel

[PULL 39/40] target/i386: Inline cmpxchg16b

Use tcg_gen_atomic_cmpxchg_i128 for the atomic case, and tcg_gen_qemu_ld/st_i128 otherwise. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/i386/helper.h | 4 --- target/i386/tcg/mem_helper.c | 69 target/i386/tcg/tra

[PULL 16/40] tcg: Add basic data movement for TCGv_i128

Add code generation functions for data movement between TCGv_i128 (mov) and to/from TCGv_i64 (concat, extract). Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg-op.h | 4 tcg/tcg-internal.h | 13 + tcg/tcg-op.

[PULL 26/40] tests/tcg/s390x: Add cdsg.c

From: Ilya Leoshkevich Add a simple test to prevent regressions. Signed-off-by: Ilya Leoshkevich Message-Id: <20230201133257.3223115-1-...@linux.ibm.com> Signed-off-by: Richard Henderson --- tests/tcg/s390x/cdsg.c | 93 + tests/tcg/s390x/Makefile.targe

[PULL 03/40] tcg: Define TCG_TYPE_I128 and related helper macros

Begin staging in support for TCGv_i128 with Int128. Define the type enumerator, the typedef, and the helper-head.h macros. This cannot yet be used, because you can't allocate temporaries of this new type. Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Hender

[PULL 40/40] tcg/aarch64: Fix patching of LDR in tb_target_set_jmp_target

'offset' should be bits [23:5] of LDR instruction, rather than [4:0]. Fixes: d59d83a1c388 ("tcg/aarch64: Reorg goto_tb implementation") Reviewed-by: Zenghui Yu Reported-by: Zenghui Yu Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 de

[PULL 31/40] target/s390x: Use Int128 for return from TRE

Acked-by: Ilya Leoshkevich Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/s390x/helper.h | 2 +- target/s390x/tcg/mem_helper.c | 7 +++ target/s390x/tcg/translate.c | 7 +-- 3 files changed, 9 insertions(+), 7 deletions(-) diff --git a/target/s

[PULL 13/40] tcg/tci: Add TCG_TARGET_CALL_{RET,ARG}_I128

Fill in the parameters for libffi for Int128. Adjust the interpreter to allow for 16-byte return values. Adjust tcg_out_call to record the return value length. Call parameters are no longer all the same size, so we cannot reuse the same call_slots array for every function. Compute it each time now

[PULL 00/40] tcg patch queue

The following changes since commit 579510e196a544b42bd8bca9cc61688d4d1211ac: Merge tag 'pull-monitor-2023-02-03-v2' of https://repo.or.cz/qemu/armbru into staging (2023-02-04 10:19:55 +) are available in the Git repository at: https://gitlab.com/rth7680/qemu.git tags/pull-tc

[PULL 02/40] tcg: Init temp_subindex in liveness_pass_2

Correctly handle large types while lowering. Fixes: fac87bd2a49b ("tcg: Add temp_subindex to TCGTemp") Signed-off-by: Richard Henderson --- tcg/tcg.c | 1 + 1 file changed, 1 insertion(+) diff --git a/tcg/tcg.c b/tcg/tcg.c index fd557d55d3..bc60fd0fe8 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -

[PULL 30/40] target/s390x: Use Int128 for return from CKSM

Acked-by: Ilya Leoshkevich Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/s390x/helper.h | 2 +- target/s390x/tcg/mem_helper.c | 7 +++ target/s390x/tcg/translate.c | 6 -- 3 files changed, 8 insertions(+), 7 deletions(-) diff --git a/target/s3

[PULL 01/40] accel/tcg: Test CPUJumpCache in tb_jmp_cache_clear_page

From: Eric Auger After commit 4e4fa6c12d ("accel/tcg: Complete cpu initialization before registration"), it looks the CPUJumpCache pointer can be NULL. This causes a SIGSEV when running debug-wp-migration kvm unit test. At the first place it should be clarified why this TCG code is called with K

[PULL 33/40] target/s390x: Use Int128 for returning float128

Acked-by: David Hildenbrand Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- v2: Remove extraneous return_low128. --- target/s390x/helper.h| 22 +++--- target/s390x/tcg/insn-data.h.inc | 20 ++--- target/s390x/tcg/fpu_helper.c| 29

[PULL 10/40] include/qemu/int128: Use Int128 structure for TCI

We are about to allow passing Int128 to/from tcg helper functions, but libffi doesn't support __int128_t, so use the structure. In order for atomic128.h to continue working, we must provide a mechanism to frob between real __int128_t and the structure. Provide a new union, Int128Alias, for this.

[PULL 36/40] target/s390x: Implement CC_OP_NZ in gen_op_calc_cc

This case is trivial to implement inline. Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 9ea28b3e52..ac5bd98f04 100644 --- a

Re: pixman_blt on aarch64

This has just bounced, I hoped to still be able to post after moderation but now I'm resending it after subscribing to the pixman list. Meanwhile I've found this ticket as well: https://gitlab.freedesktop.org/pixman/pixman/-/merge_requests/71 See the rest of the message below. Looks like this is

Re: [PULL 0/1] M68k next patches

On Wed, 1 Feb 2023 at 09:54, Laurent Vivier wrote: > > The following changes since commit 13356edb87506c148b163b8c7eb0695647d00c2a: > > Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into > staging (2023-01-24 09:45:33 +) > > are available in the Git repository at: > >

[PATCH 1/4] pcie: pcie_cap_slot_write_config(): use correct macro

PCI_EXP_SLTCTL_PIC_OFF is a value, and PCI_EXP_SLTCTL_PIC is a mask. Happily PCI_EXP_SLTCTL_PIC_OFF is a maximum value for this mask and is equal to the mask itself. Still the code looks like a bug. Let's make it more reader-friendly. Signed-off-by: Vladimir Sementsov-Ogievskiy --- hw/pci/pcie.c

[PATCH 0/4] pcie: cleanup code and add trace point

Hi all! Here is tiny code cleanup + on trace point to track power indicator changes (which may help to analyze "Hot-unplug failed: guest is busy (power indicator blinking)" error message). Vladimir Sementsov-Ogievskiy (4): pcie: pcie_cap_slot_write_config(): use correct macro pcie_regs: drop

[PATCH 4/4] pcie: add trace-point for power indicator transitions

Signed-off-by: Vladimir Sementsov-Ogievskiy --- hw/pci/pcie.c | 20 hw/pci/trace-events | 3 +++ 2 files changed, 23 insertions(+) diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index ccdb2377e1..1a19368994 100644 --- a/hw/pci/pcie.c +++ b/hw/pci/pcie.c @@ -28,6 +28,7 @@

[PATCH 4/4] pcie: add trace-poing for power indicator transitions

Signed-off-by: Vladimir Sementsov-Ogievskiy --- hw/pci/pcie.c | 20 hw/pci/trace-events | 3 +++ 2 files changed, 23 insertions(+) diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index ccdb2377e1..1a19368994 100644 --- a/hw/pci/pcie.c +++ b/hw/pci/pcie.c @@ -28,6 +28,7 @@

[PATCH 2/4] pcie_regs: drop duplicated indicator value macros

We already have indicator values in include/standard-headers/linux/pci_regs.h , no reason to reinvent them in include/hw/pci/pcie_regs.h. (and we already have usage of PCI_EXP_SLTCTL_PWR_IND_BLINK and PCI_EXP_SLTCTL_PWR_IND_OFF in hw/pci/pcie.c, so let's be consistent) Signed-off-by: Vladimir Seme

[PATCH 3/4] pcie: drop unused PCIExpressIndicator

The structure type is unused. Also, it's the only user of corresponding macros, so drop them too. Signed-off-by: Vladimir Sementsov-Ogievskiy --- include/hw/pci/pcie.h | 8 include/hw/pci/pcie_regs.h | 5 - 2 files changed, 13 deletions(-) diff --git a/include/hw/pci/pcie.h b/

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