ping
On Tue, Jan 31, 2023 at 2:30 PM wlfightup wrote:
>
> When vfio-pci devices are attached to the downstream, pcie acs
> capability may be needed, Consistent with physical machine.
>
> It has been tested in our environment, and pcie acs capability
> is required in some scenarios.
>
> Claim ACS
On 2/17/23 10:11, Fabiano Rosas wrote:
diff --git a/target/arm/meson.build b/target/arm/meson.build
index a5191b57e1..b0bc8a3cea 100644
--- a/target/arm/meson.build
+++ b/target/arm/meson.build
@@ -1,6 +1,7 @@
arm_ss = ss.source_set()
arm_ss.add(files(
'cpu.c',
+ 'cpu64.c',
'debug_he
On 2/17/23 10:11, Fabiano Rosas wrote:
The next few patches will move helpers under CONFIG_TCG. We'd prefer
to keep the debug helpers and debug registers close together, so
rearrange the file a bit to be able to wrap the helpers with a TCG
ifdef.
Signed-off-by: Fabiano Rosas
---
target/arm/deb
On 2/17/23 10:11, Fabiano Rosas wrote:
This is in preparation for restricting compilation of some parts of
debug_helper.c to TCG only.
Signed-off-by: Fabiano Rosas
---
Dropped r-bs because I added a few more ifs in debug_helper.c
---
target/arm/cpu.c | 6 --
target/arm/debug_hel
On 2/17/23 10:34, Daniel Henrique Barboza wrote:
+/*
+ * Section 2.5.2 of cmobase v1.0.1:
+ *
+ * "A cache-block management instruction is permitted to
+ * access the specified cache block whenever a load instruction
+ * or store instruction is permitted to access the corr
On 2/17/23 10:34, Daniel Henrique Barboza wrote:
+void helper_cbo_zero(CPURISCVState *env, target_ulong address)
+{
+RISCVCPU *cpu = env_archcpu(env);
+uintptr_t ra = GETPC();
+uint16_t cbozlen;
+void *mem;
+
+check_zicbo_envcfg(env, MENVCFG_CBZE, ra);
+
+/* Get the size o
Thanks to everyone.
Ok , so I need to run QEMU in Full System Emulation mode to run the
Solaris binary.
Is the *qemu-kvm* , the only package required to be installed ( on RHEL
machine) to launch QEMU or there are some packages also.
Also I would need the Solars OS image, right?
Regards,
Ginu
在 2023/2/18 0:54, Strahinja Jankovic 写道:
Hi,
I tried running Avocado tests for cubieboard with following command:
ARMBIAN_ARTIFACTS_CACHED=yes AVOCADO_ALLOW_LARGE_STORAGE=yes avocado
--show=app,console run-t machine:cubieboard
tests/avocado/boot_linux_console.py
Without this patch all
ping. Is there anything I can do to help this get merged?
Best regards,
John Berberian, Jr.
Am 17. Februar 2023 14:18:31 UTC schrieb "Philippe Mathieu-Daudé"
:
>Following the recommendation added in commit a98c370c46
>("typedefs: (Re-)sort entries alphabetically"), and similarly
>to commit 64baadc272 ("Sort include/qemu/typedefs.h"), sort
>again the type definitions (in case-insensiti
Tests that when RMFD_HUGEPAGE is specified, restrictedmem will be
backed by Transparent HugePages.
Signed-off-by: Ackerley Tng
---
.../restrictedmem_hugepage_test.c | 25 +++
1 file changed, 25 insertions(+)
diff --git
a/tools/testing/selftests/restrictedmem/restric
Allow userspace to hint the kernel to use Transparent HugePages to
back restricted memory on a per-file basis.
Signed-off-by: Ackerley Tng
---
include/uapi/linux/restrictedmem.h | 1 +
mm/restrictedmem.c | 27 +--
2 files changed, 18 insertions(+), 10 del
Hello,
This patchset builds upon the memfd_restricted() system call that has
been discussed in the ‘KVM: mm: fd-based approach for supporting KVM’
patch series, at
https://lore.kernel.org/lkml/20221202061347.1070246-1-chao.p.p...@linux.intel.com/T/#m7e944d7892afdd1d62a03a287bd488c56e377b0c
The tr
On Tue, Feb 14, 2023 at 12:26 PM Kevin Wolf wrote:
>
> Am 14.02.2023 um 15:03 hat Paolo Bonzini geschrieben:
> > In the case of Python the issue is not the interpreter per se, though
> > there are a couple new feature in Python 3.7 that are quite nice (for
> > example improved data classes[1] or c
On 2/17/23 10:29 AM, Jonathan Cameron wrote:
CXL uses PCI AER Internal errors to signal to the host that an error has
occurred. The host can then read more detailed status from the CXL RAS
capability.
For uncorrectable errors: support multiple injection in one operation
as this is needed to r
On 2/17/23 10:29 AM, Jonathan Cameron wrote:
As these are about to be modified, fix the endian handle for
this set of registers rather than making it worse.
Note that CXL is currently only supported in QEMU on
x86 (arm64 patches out of tree) so we aren't going to yet hit
an problems with big
Remove a pointless cast in ptimer_tick() and rename 'ptimer_state'
as 'PTimer' to follow the Structure naming convention.
See docs/devel/style.rst:
Variables are lower_case_with_underscores; easy to type and
read. Structured type names are in CamelCase; harder to type
but standing out. En
On 2/17/23 10:29 AM, Jonathan Cameron wrote:
This infrastructure will be reused for CXL RAS error injection
in patches that follow.
Signed-off-by: Jonathan Cameron
Reviewed-by: Dave Jiang
---
hw/pci/pci-internal.h | 1 -
include/hw/pci/pcie_aer.h | 1 +
2 files changed, 1 insert
On 2/17/23 10:29 AM, Jonathan Cameron wrote:
This enables AER error injection to function as expected.
It is intended as a building block in enabling CXL RAS error injection
in the following patches.
Signed-off-by: Jonathan Cameron
Reviewed-by: Dave Jiang
---
hw/mem/cxl_type3.c | 13 +
On 2/17/23 10:29 AM, Jonathan Cameron wrote:
Done to avoid fixing ACPI route description of traditional PCI interrupts on q35
and because we should probably move with the times anyway.
Signed-off-by: Jonathan Cameron
Reviewed-by: Dave Jiang
---
hw/pci-bridge/cxl_root_port.c | 61 +
On 2/17/23 10:29 AM, Jonathan Cameron wrote:
We are missing necessary config write handling for AER emulation in
the CXL root port. Add it based on pcie_root_port.c
Signed-off-by: Jonathan Cameron
Reviewed-by: Dave Jiang
---
hw/pci-bridge/cxl_root_port.c | 3 +++
1 file changed, 3 in
I think it's guest memory again. IMHO It's a part of a memory pool and
not real IO data (unless this was pagefile data).
The first 16 bytes look like POOL_HEADER structure.
The first dump contained signature from FilterManager and the latest
contains two structures from Ntfs.
It's not clear to me w
On 2/17/23 10:29 AM, Jonathan Cameron wrote:
PCIe r6.0 Figure 6-3 "Pseudo Logic Diagram for Selected Error Message Control
and Status Bits" includes a right hand branch under "All PCI Express devices"
that allows for messages to be generated or sent onwards without SERR#
being set as long as t
On 2/17/23 10:29 AM, Jonathan Cameron wrote:
This register in AER should be both writeable and should
have a default value with a couple of the errors masked
including the Uncorrectable Internal Error used by CXL for
it's error reporting.
Signed-off-by: Jonathan Cameron
Reviewed-by: Dave J
On 17/2/23 19:52, Thomas Huth wrote:
On 17/02/2023 15.18, Philippe Mathieu-Daudé wrote:
"hw/ptimer.h" API is mostly used by timer / watchdog device
models. Since the SoC / machines only access the ptimer via
reference, they don't need its definition: the declartion is
enough.
On order to reduce
On Thu, Feb 16, 2023 at 5:58 AM Thomas Huth wrote:
>
> On 15/02/2023 20.05, Markus Armbruster wrote:
> > The discussion under PATCH 6 makes me think there's a bit of confusion
> > about the actual impact of dropping support for Python 3.6. Possibly
> > because it's spelled out in the commit messa
QEMU configure script goes into an infinite error printing loop
when in read only directory due to 'build' dir never being created.
Checking if 'mkdir dir' succeeds prevents this error.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/321
Signed-off-by: Dinah Baum
---
Changes since v2:
Up
Hi,
This new version contains a change in patch 2 based on Richard's
feedback in v5 [1].
Changes from v5:
- patch 2:
- check if 'mem' is mapped into RAM with 'tlb_vaddr_to_host' before
zeroing it.
- v5 link: https://lists.gnu.org/archive/html/qemu-devel/2023-02/msg04414.html
[1] https://li
From: Christoph Muellner
The cmo.prefetch instructions are nops for QEMU (no emulation of the
memory hierarchy, no illegal instructions, no permission faults, no
traps).
Add a comment noting where they would be decoded in case cbo.prefetch
instructions become relevant in the future.
Co-develope
From: Christoph Muellner
The existing probe_access* functions do not allow to specify the
access size and a non-faulting behavior at the same time.
This is resolved by adding a generalization of probe_access_flags()
that takes an additional size parameter.
The semantics is basically the same as
From: Christoph Muellner
Zicbom is the Cache-Block Management extension defined in the already
ratified RISC-V Base Cache Management Operation (CBO) ISA extension [1].
The extension contains three instructions: cbo.clean, cbo.flush and
cbo.inval. All of them must be implemented in the same group
From: Christoph Muellner
The RISC-V base cache management operation (CBO) ISA extension has been
ratified. It defines three extensions: Cache-Block Management, Cache-Block
Prefetch and Cache-Block Zero. More information about the spec can be
found at [1].
Let's start by implementing the Cache-Bl
Move the 64-bit CPUs that are TCG-only:
- cortex-a35
- cortex-a55
- cortex-a72
- cortex-a76
- a64fx
- neoverse-n1
Keep the CPUs that can be used with KVM:
- cortex-a57
- cortex-a53
- max
- host
For the special case "max" CPU, there's a nuance that while KVM/HVF
use the "host" model instead, we st
Il ven 17 feb 2023, 19:47 Thomas Huth ha scritto:
> On 17/02/2023 16.59, Daniel P. Berrangé wrote:
> > On Fri, Feb 17, 2023 at 04:55:49PM +0100, Markus Armbruster wrote:
>
> > The cost/benefit tradeoff of dropping the platforms entirely
> > is not obviously favourable when we don't have clea
The migration tests are currently broken for an aarch64 host because
the tests pass no 'machine' and 'cpu' options on the QEMU command
line.
Add a separate class to each architecture so that we can specify
'machine' and 'cpu' options instead of relying on defaults.
Add a skip decorator to keep th
When TCG is disabled this part of the code should not be reachable, so
wrap it with an ifdef for now.
Signed-off-by: Fabiano Rosas
Reviewed-by: Richard Henderson
Tested-by: Philippe Mathieu-Daudé
---
target/arm/ptw.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/arm/ptw.c b/ta
The hflags are used only for TCG code, so introduce a new file
hflags.c to keep that code.
Signed-off-by: Fabiano Rosas
Reviewed-by: Richard Henderson
Tested-by: Philippe Mathieu-Daudé
---
target/arm/helper.c| 393 +---
target/arm/internals.h | 2 +
If a test was tagged with the "accel" tag and the specified
accelerator it not present in the qemu binary, cancel the test.
We can now write tests without explicit calls to require_accelerator,
just the tag is enough.
Signed-off-by: Fabiano Rosas
Reviewed-by: Richard Henderson
Tested-by: Philip
Now that the cortex-a15 is under CONFIG_TCG, use as default CPU for a
KVM-only build the 'max' cpu.
Note that we cannot use 'host' here because the qtests can run without
any other accelerator (than qtest) and 'host' depends on KVM being
enabled.
Signed-off-by: Fabiano Rosas
Acked-by: Richard He
We are about to enable the build without TCG, so CONFIG_SEMIHOSTING
and CONFIG_ARM_COMPATIBLE_SEMIHOSTING cannot be unconditionally set in
default.mak anymore. So reflect the change in a Kconfig.
Instead of using semihosting/Kconfig, use a target-specific file, so
that the change doesn't affect ot
Move all the CONFIG_FOO=y from default.mak into "default y if TCG"
statements in Kconfig. That way they won't be selected when
CONFIG_TCG=n.
I'm leaving CONFIG_ARM_VIRT in default.mak because it allows us to
keep the two default.mak files not empty and keep aarch64-default.mak
including arm-defaul
These tests set -accel tcg, so restrict them to when TCG is present.
Signed-off-by: Fabiano Rosas
Acked-by: Richard Henderson
Reviewed-by: Thomas Huth
---
Removed unneeded hunk restricting dependencies
Use config_all instead of config_devices_all to check for TCG
---
tests/qtest/meson.build |
This test currently fails when run on a host for which the QEMU target
has no default machine set:
ERROR| Output: qemu-system-aarch64: No machine specified, and there is
no default
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Fabiano Rosas
---
tests/avocado/version.py | 1 +
1 file chang
From: Claudio Fontana
Signed-off-by: Claudio Fontana
Signed-off-by: Fabiano Rosas
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Tested-by: Philippe Mathieu-Daudé
---
target/arm/meson.build | 1 -
target/arm/tcg/meson.build | 4
target/arm/{ => tcg}/psci.c | 0
3 files c
It is possible to have a build with both TCG and KVM disabled due to
Xen requiring the i386 and x86_64 binaries to be present in an aarch64
host.
If we build with --disable-tcg on the aarch64 host, we will end-up
with a QEMU binary (x86) that does not support TCG nor KVM.
Fix tests that crash or
From: Philippe Mathieu-Daudé
Add a manual new job to cross-build the aarch64 target with
only the KVM accelerator enabled (in particular, no TCG).
Re-enable running the similar job on the project Aarch64
custom runner.
Signed-off-by: Philippe Mathieu-Daudé
Signed-off-by: Fabiano Rosas
Reviewe
Signed-off-by: Fabiano Rosas
Reviewed-by: Richard Henderson
Acked-by: Thomas Huth
---
tests/qtest/arm-cpu-features.c | 22 +++---
1 file changed, 15 insertions(+), 7 deletions(-)
diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c
index 4ff2014bea..1555
From: Claudio Fontana
Signed-off-by: Claudio Fontana
Signed-off-by: Fabiano Rosas
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
---
target/arm/meson.build | 15 ++-
target/arm/tcg-stubs.c | 23 +++
This is in preparation to moving the hflags code into its own file
under the tcg/ directory.
Signed-off-by: Fabiano Rosas
Reviewed-by: Richard Henderson
Tested-by: Philippe Mathieu-Daudé
---
hw/arm/boot.c | 6 +-
hw/intc/armv7m_nvic.c | 20 +---
target/arm/
This struct has no dependencies on TCG code and it is being used in
target/arm/ptw.c to simplify the passing around of page table walk
results. Those routines can be reached by KVM code via the gdbstub
breakpoint code, so take the structure out of CONFIG_TCG to make it
visible when building with --
Since commit cf7c6d1004 ("target/arm: Split out cpregs.h") we now have
a cpregs.h header which is more suitable for this code.
Code moved verbatim.
Signed-off-by: Fabiano Rosas
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
---
target/arm
From: Claudio Fontana
make it clearer from the name that this is a tcg-only function.
Signed-off-by: Claudio Fontana
Signed-off-by: Fabiano Rosas
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
---
target/arm/helper.c | 4 ++--
1 file ch
Addressed Peter's comments and dropped the cpregs change which is not
related to fixing the --disable-tcg build. This unblocks the xenpvh
series and I can tackle the regs split without holding up the build
work.
changes:
- debug regs: I left debug_helper.c out of the movement to tcg/ along
with
From: Claudio Fontana
move the module containing cpu models definitions
for 32bit TCG-only CPUs to tcg/ and rename it for clarity.
Signed-off-by: Claudio Fontana
Signed-off-by: Fabiano Rosas
Reviewed-by: Richard Henderson
---
hw/arm/virt.c | 2 +-
target/arm/meson.bu
The file cpu_tcg.c is about to be moved into the tcg/ directory, so
move the register definitions into cpu64.c along with the cortex cpus
definition.
This code defines registers for 64-bit cpus but it is shared by the 32
bit "max" CPU, so use an ifdef instead of meson to keep the rest of
the file
The next few patches will move helpers under CONFIG_TCG. We'd prefer
to keep the debug helpers and debug registers close together, so
rearrange the file a bit to be able to wrap the helpers with a TCG
ifdef.
Signed-off-by: Fabiano Rosas
---
target/arm/debug_helper.c | 476 +++
Introduce the target/arm/tcg directory. Its purpose is to hold the TCG
code that is selected by CONFIG_TCG.
Signed-off-by: Claudio Fontana
Signed-off-by: Fabiano Rosas
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
This allows the test to be skipped when TCG is not present in the QEMU
binary.
Signed-off-by: Fabiano Rosas
Reviewed-by: Richard Henderson
Tested-by: Philippe Mathieu-Daudé
---
tests/avocado/boot_linux_console.py | 1 +
tests/avocado/reverse_debugging.py | 8
2 files changed, 9 inser
This function is needed by common code (ptw.c), so move it along with
the other regime_* functions in internal.h. When we enable the build
without TCG, the tlb_helper.c file will not be present.
Signed-off-by: Fabiano Rosas
Reviewed-by: Richard Henderson
Tested-by: Philippe Mathieu-Daudé
---
t
This is in preparation for restricting compilation of some parts of
debug_helper.c to TCG only.
Signed-off-by: Fabiano Rosas
---
Dropped r-bs because I added a few more ifs in debug_helper.c
---
target/arm/cpu.c | 6 --
target/arm/debug_helper.c | 16
target/arm/ma
From: Claudio Fontana
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
Signed-off-by: Fabiano Rosas
Tested-by: Philippe Mathieu-Daudé
---
target/arm/helper.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.
Move this earlier to make the next patch diff cleaner. While here
update the comment slightly to not give the impression that the
misalignment affects only TCG.
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Fabiano Rosas
Tested-by: Philippe Mathieu-Daudé
---
From: Claudio Fontana
for "all" builds (tcg + kvm), we want to avoid doing
the psci check if tcg is built-in, but not enabled.
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
Signed-off-by: Fabiano Rosas
Tested-by: Philippe Mathieu-Daudé
---
target/arm/helper.c | 3 ++-
1 file
On Fri, Feb 17, 2023 at 7:27 AM Philippe Mathieu-Daudé
wrote:
>
> On 17/2/23 11:31, Fiona Ebner wrote:
> > Fixes: e4baa9f00b ("AHCI: Replace DPRINTF with trace-events")
>
> Oops
Seconding the whoops.
>
> > Signed-off-by: Fiona Ebner
> > ---
> >
> > Or should it be sorted alphabetically below ex
On 17/02/2023 17.38, Paolo Bonzini wrote:
On 2/17/23 11:47, Daniel P. Berrangé wrote:
On Fri, Feb 17, 2023 at 11:36:41AM +0100, Markus Armbruster wrote:
I feel the discussion petered out without a conclusion.
I don't think letting the status quo win by inertia is a good outcome
here.
Which 32
On Fri, Feb 17, 2023 at 04:16:17PM +, Jonathan Cameron via wrote:
> On Tue, 31 Jan 2023 16:38:47 +
> Jonathan Cameron via wrote:
>
> > From: Gregory Price
> >
> > This commit enables each CXL Type-3 device to contain one volatile
> > memory region and one persistent region.
> >
> > Two
On Fri, Feb 17, 2023 at 11:14:18AM +, Jonathan Cameron wrote:
> On Thu, 16 Feb 2023 15:52:31 -0500
> Gregory Price wrote:
>
> >
> > I agree, it's certainly "not pretty".
> >
> > I'd go so far as to call the baby ugly :]. Like i said: "The Hackiest way"
> >
> > My understanding from lookin
On 17/02/2023 18.43, Philippe Mathieu-Daudé wrote:
(Cc'ing Huacai & Jiaxun).
On 17/2/23 17:38, Paolo Bonzini wrote:
On 2/17/23 11:47, Daniel P. Berrangé wrote:
On Fri, Feb 17, 2023 at 11:36:41AM +0100, Markus Armbruster wrote:
I feel the discussion petered out without a conclusion.
I don't t
On 17/02/2023 15.18, Philippe Mathieu-Daudé wrote:
"hw/ptimer.h" API is mostly used by timer / watchdog device
models. Since the SoC / machines only access the ptimer via
reference, they don't need its definition: the declartion is
enough.
On order to reduce the inclusion on the source files,
fo
On 17/02/2023 16.59, Daniel P. Berrangé wrote:
On Fri, Feb 17, 2023 at 04:55:49PM +0100, Markus Armbruster wrote:
The cost/benefit tradeoff of dropping the platforms entirely
is not obviously favourable when we don't have clear demand
to bump the min versions of native packages, and the co
On 17/02/2023 16.06, Daniel P. Berrangé wrote:
On Fri, Feb 17, 2023 at 02:26:31PM +0100, Thomas Huth wrote:
...
I'm also not so comfortable dropping the only version of SLES that we
explicitly target, when we don't know when their new major release
will arrive.
Let's hope that the next major
On 2/17/23 06:06, Reinoud Zandijk wrote:
On Fri, Feb 17, 2023 at 11:36:41AM +0100, Markus Armbruster wrote:
I feel the discussion petered out without a conclusion.
I don't think letting the status quo win by inertia is a good outcome
here.
Which 32-bit hosts are still useful, and why?
NetBSD
Current implementation is very simple so many of the corner
cases do not exist (e.g. fragmenting larger poison list entries)
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-mailbox-utils.c | 77 +
hw/mem/cxl_type3.c | 36 +
include/hw/
Very simple implementation to allow testing of corresponding
kernel code. Note that for now we track each 64 byte section
independently. Whilst a valid implementation choice, it may
make sense to fuse entries so as to prove out more complex
corners of the kernel code.
Signed-off-by: Jonathan Came
On 17/2/23 17:35, Mathis Marion wrote:
From: Mathis Marion
Fields sin6_flowinfo and sin6_scope_id use the host byte order, so there
is a conversion to be made when host and target endianness differ.
Signed-off-by: Mathis Marion
---
linux-user/syscall.c | 6 ++
1 file changed, 6 inserti
Inject poison using qmp command cxl-inject-poison to add an entry to the
poison list.
For now, the poison is not returned CXL.mem reads, but only via the
mailbox command Get Poison List.
See CXL rev 3.0, sec 8.2.9.8.4.1 Get Poison list (Opcode 4300h)
Kernel patches to use this interface here:
ht
From: Ira Weiny
There are new users of this functionality coming shortly so factor
it out from the GET_TIMESTAMP mailbox command handling.
Signed-off-by: Ira Weiny
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-device-utils.c | 15 +++
hw/cxl/cxl-mailbox-utils.c | 11 +-
This enum typedef used to be local to one file, so having a generic
name wasn't a big problem even if it wasn't compliant with QEMU naming
conventions. Now it is in cxl_device.h to support use outside of
cxl-mailbox-utils.c rename it.
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-mailbox-utils
Needs tidy up and rename to something more generic now it is
in a header.
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-mailbox-utils.c | 28
include/hw/cxl/cxl_device.h | 28
2 files changed, 28 insertions(+), 28 deletions(-)
diff --g
Note Alison has stated the kernel series will be post 6.3 material
so this one isn't quite as urgent as the patches it is based on.
However I think this series in a good state (plus I have lots more queued
behind it) hence promoting it from RFC.
Changes since RFC v2: Thanks to Markus for review.
On Fri, Feb 17, 2023 at 01:07:43PM +0100, Jesper Devantier wrote:
> +static void nvme_do_write_fdp(NvmeCtrl *n, NvmeRequest *req, uint64_t slba,
> + uint32_t nlb)
> +{
> +NvmeNamespace *ns = req->ns;
> +NvmeRwCmd *rw = (NvmeRwCmd *)&req->cmd;
> +uint64_t dat
On 2/17/23 04:18, Philippe Mathieu-Daudé wrote:
"hw/ptimer.h" API is mostly used by timer / watchdog device
models. Since the SoC / machines only access the ptimer via
reference, they don't need its definition: the declartion is
enough.
On order to reduce the inclusion on the source files,
forwa
From: Gregory Price
This commit enables each CXL Type-3 device to contain one volatile
memory region and one persistent region.
Two new properties have been added to cxl-type3 device initialization:
[volatile-memdev] and [persistent-memdev]
The existing [memdev] property has been deprecated
On 2/17/23 04:18, Philippe Mathieu-Daudé wrote:
Following the recommendation added in commit a98c370c46
("typedefs: (Re-)sort entries alphabetically"), and similarly
to commit 64baadc272 ("Sort include/qemu/typedefs.h"), sort
again the type definitions (in case-insensitive alphabetical
order, usi
From: Gregory Price
Defines are starting to exceed line length limits, align them for
cleanliness before making modifications.
Signed-off-by: Gregory Price
Signed-off-by: Jonathan Cameron
---
tests/qtest/cxl-test.c | 84 +++---
1 file changed, 46 insertions
v2:
- Fix an off by one in address space matching when both volatile and
persistent memory is in present (meant 1st byte of persistent memory
not readale)
- Picked up tags (thanks to all who tested!)
Based on following series (in order)
1. [PATCH v4 00/10] hw/cxl: CXL emulation cleanups and mi
From: Daniel Henrique Barboza
Next patch will move all calls to riscv_load_initrd() to
riscv_load_kernel(). Machines that want to load initrd will be able to
do via an extra flag to riscv_load_kernel().
This change will expose a sign-extend behavior that is happening in
load_elf_ram_sym() when r
From: LIU Zhiwei
vslide1up_##BITWIDTH is used by the vslide1up.vx and vslide1up.vf. So its
scalar input should be uint64_t to hold the 64 bits float register.And the
same for vslide1down_##BITWIDTH.
This bug is caught when run these instructions on qemu-riscv32.
Signed-off-by: LIU Zhiwei
Revie
The following changes since commit 417296c8d8588f782018d01a317f88957e9786d6:
tests/qtest/netdev-socket: Raise connection timeout to 60 seconds (2023-02-09
11:23:53 +)
are available in the Git repository at:
https://github.com/palmer-dabbelt/qemu.git tags/pull-riscv-to-apply-20230217
From: Frank Chang
The RVV specification does not require that the core needs to support
the privileged specification v1.12.0 to support RVV, and there is no
dependency from ISA level.
This commit removes the restriction from both RVV CSRs and extension CPU
ISA string.
Signed-off-by: Frank Chang
From: Daniel Henrique Barboza
We have a RISCVCPU *cpu pointer available at the start of the function.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Weiwei Li
Message-ID: <20230210123836.506286-1-dbarb...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
From: Daniel Henrique Barboza
The microchip_icicle_kit, sifive_u, spike and virt boards are now doing
the same steps when '-kernel' is used:
- execute load_kernel()
- load init_rd()
- write kernel_cmdline
Let's fold everything inside riscv_load_kernel() to avoid code
repetition. To not change t
From: Alistair Francis
This patch adds some active RISC-V members as reviewers to the
MAINTAINERS file.
Signed-off-by: Alistair Francis
Acked-by: LIU Zhiwei
Acked-by: Weiwei Li
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Bin Meng
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Frank
From: Daniel Henrique Barboza
The only remaining caller is riscv_load_kernel_and_initrd() which
belongs to the same file.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Bin Meng
Reviewed-by: Alistair Francis
Message-Id: <20230206140022.2748401-4-dbarb
From: Himanshu Chauhan
When MSECCFG.MML is set, after checking the address range in PMP if the
asked permissions are not same as programmed in PMP, the default
permissions are applied. This should only be the case when there
is no matching address is found.
This patch skips applying default rule
On 2/17/23 13:10, Ivan Klokov wrote:
Due to typo in opcode list, ctzw is disassembled as clzw instruction.
Fixes: 02c1b569a15b ("disas/riscv: Add Zb[abcs] instructions")
Signed-off-by: Ivan Klokov
---
Reviewed-by: Daniel Henrique Barboza
v2:
- added fixes line
---
disas/riscv.c |
(Cc'ing Huacai & Jiaxun).
On 17/2/23 17:38, Paolo Bonzini wrote:
On 2/17/23 11:47, Daniel P. Berrangé wrote:
On Fri, Feb 17, 2023 at 11:36:41AM +0100, Markus Armbruster wrote:
I feel the discussion petered out without a conclusion.
I don't think letting the status quo win by inertia is a good
On 2/16/23 13:33, Warner Losh wrote:
h2g_old_sysctl does the byte swapping in the data to return it to the
target for the 'well known' types. For most of the types, either the
data is returned verbatim (strings, byte size, opaque we don't know
about) or it's returned with byte swapping (for all t
On 2/16/23 13:33, Warner Losh wrote:
cap_memory - Caps the memory to just below MAXINT
scale_to_guest_pages - Account for difference in host / guest page size
h2g_long_sat - converts a int64_t to a int32_t, saturating at max / min values
h2g_ulong_sat - converts a uint64_t to a uint32_t, saturati
CXL uses PCI AER Internal errors to signal to the host that an error has
occurred. The host can then read more detailed status from the CXL RAS
capability.
For uncorrectable errors: support multiple injection in one operation
as this is needed to reliably test multiple header logging support in an
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