Hi Dorinda,
I've started to write down my suggestions and comments. After more than
one page of text, I think that without sample code, the text is not very
understandable. Therefore I will write three mails.
In this mail I describe the problem with the QEMU Pipewire audio
backend. My next m
On Thu, Mar 09, 2023 at 02:09:30PM -0800, Simon Glass wrote:
> Hi Gerd,
>
> Where did these binaries come from? What commit and how were they built?
See patch 1/3 for the source (edk2 submodule) update and patch 2/3 for
the build scripts.
take care,
Gerd
On Wed, Mar 8, 2023 at 8:26 PM Damian Hobson-Garcia
wrote:
> Check that a widget has a window before trying
> to update its contents.
> ---
> ui/gtk.c | 4
> 1 file changed, 4 insertions(+)
>
Reviewed-by: Marc-André Lureau
>
> diff --git a/ui/gtk.c b/ui/gtk.c
> index fd82e9b1ca..e4e098
On Mon, Feb 27, 2023 at 7:06 PM Ivan Klokov wrote:
>
> The decoding of the slli_uw currently contains decoding
> error: shamt part of opcode has six bits, not five.
>
> Fixes 3de1fb71("target/riscv: update disas.c for xnor/orn/andn and slli.uw")
>
> Signed-off-by: Ivan Klokov
Thanks!
Applied to
Hi
(adding Sam Lantinga, SDL maintainer, in CC. I noticed he worked on QEMU
SDL backend yesterday! ;)
On Thu, Mar 9, 2023 at 8:40 PM Philippe Mathieu-Daudé
wrote:
> On 7/3/23 12:56, marcandre.lur...@redhat.com wrote:
> > From: Marc-André Lureau
> >
> > Apparently, there is no environment varia
On Fri, Dec 23, 2022 at 12:50 AM Alexander Graf wrote:
>
> An ITT entry is opaque to the OS. The only thing it does get told by HW is
> its size. In theory, that size can be any byte aligned number, in practice
> HW will always use power of 2s to simplify offset calculation. We currently
> expose
On Mon, Dec 19, 2022 at 2:08 PM Alexander Graf wrote:
>
> We currently only support GICv2 emulation. To also support GICv3, we will
> need to pass a few system registers into their respective handler functions.
>
> This patch adds support for HVF to call into the TCG callbacks for GICv3
> system r
On Mon, Feb 27, 2023 at 7:06 PM Ivan Klokov wrote:
>
> The decoding of the slli_uw currently contains decoding
> error: shamt part of opcode has six bits, not five.
>
> Fixes 3de1fb71("target/riscv: update disas.c for xnor/orn/andn and slli.uw")
>
> Signed-off-by: Ivan Klokov
Acked-by: Alistair
On Tue, Feb 28, 2023 at 12:53 AM Mikhail Tyutin wrote:
>
> Fix incorrect register name in RISC-V disassembler for fmv,fabs,fneg
> instructions
>
> Signed-off-by: Mikhail Tyutin
It looks like this needs to be rebased. Do you mind rebasing it and
sending a v2?
Alistair
> ---
> disas/riscv.c |
On Sun, Mar 5, 2023 at 7:43 PM Jim Shu wrote:
>
> This patch also enables debugger to set current privilege mode to
> VU/VS-mode.
>
> Extend previous commit 81d2929c41d32af138f3562f5a7b309f6eac7ca7 to
> support H-extension.
I'm not sure we want this. What is the use case for this?
Changing the v
On 3/1/2023 9:51 PM, David Woodhouse wrote:
From: David Woodhouse
The xen_overlay device (and later similar devices for event channels and
grant tables) need to be instantiated. Do this from a kvm_type method on
the PC machine derivatives, since KVM is only way to support Xen emulation
for now.
Hi Peter
>-Original Message-
>From: Peter Xu
>Sent: Thursday, March 9, 2023 10:56 PM
>To: Duan, Zhenzhong
>Cc: qemu-devel@nongnu.org; m...@redhat.com; jasow...@redhat.com;
>pbonz...@redhat.com; richard.hender...@linaro.org; edua...@habkost.net;
>marcel.apfelb...@gmail.com
>Subject: Re: [
In last patch, we wrap vm_load with begin/commit, here we introduce
address_space_to_flatview_rcu() to avoid unnecessary enforce commit
during vm_load.
Signed-off-by: Chuang Xu
---
include/exec/memory-internal.h | 2 +-
include/exec/memory.h | 20
softmmu/memory.c
Before using any flatview, sanity check whether BQL or rcu is held. And
if we're during a memory region transaction, try to immediately update
mappings, or the map can be invalid.
Signed-off-by: Chuang Xu
---
include/exec/memory.h | 23 +++
softmmu/memory.c | 5 +
2
Add rcu_read_is_locked() to detect holding of rcu lock.
Signed-off-by: Chuang Xu
---
include/qemu/rcu.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/include/qemu/rcu.h b/include/qemu/rcu.h
index 313fc414bc..7bf45602e1 100644
--- a/include/qemu/rcu.h
+++ b/include/qemu/rcu.h
@@ -115
Split memory_region_transaction_do_commit() from
memory_region_transaction_commit().
We'll call do_commit() in address_space_to_flatview() in the later patch.
Signed-off-by: Chuang Xu
---
softmmu/memory.c | 47 +++
1 file changed, 27 insertions(+), 20
From: Peter Xu
Calling RCU variance of address_space_get|to_flatview() during memory
commit (flatview updates, triggering memory listeners, or updating
ioeventfds, etc.) is not 100% accurate, because commit() requires BQL
rather than RCU read lock, so the context exclusively owns current_map and
The duration of loading non-iterable vmstate accounts for a significant
portion of downtime (starting with the timestamp of source qemu stop and
ending with the timestamp of target qemu start). Most of the time is spent
committing memory region changes repeatedly.
This patch packs all the changes
In this version:
- introduce address_space_to_flatview_rcu()
- squash peter's fix into patch 1
- rebase to latest upstream
- update test results
The duration of loading non-iterable vmstate accounts for a significant
portion of downtime (starting with the timestamp of source qemu stop and
endin
On 2023/3/8 20:34, chenyi2...@zju.edu.cn wrote:
From: Yi Chen
Trap accesses to hgatp if MSTATUS_TVM is enabled.
Don't trap accesses to vsatp even if MSTATUS_TVM is enabled.
By the way, do you know why mstatus_tvm and hstatus_tvm are needed?
The specification said,
The TVM mechanism improves
On Fri, Mar 10, 2023 at 2:23 AM Daniel Henrique Barboza
wrote:
>
>
>
> On 3/9/23 04:28, LIU Zhiwei wrote:
> >
> > On 2023/3/9 4:19, Daniel Henrique Barboza wrote:
> >> The setter is doing nothing special. Just set env->priv_ver directly.
> > IMHO, No better than the older implementation.
>
> In th
On Sun, Mar 5, 2023 at 7:43 PM Jim Shu wrote:
>
> This patch enables a debugger to read current virtualization mode via
> virtual "virt" register. After it, we could get full current privilege
> mode via both "priv" and "virt" register.
>
> Extend previous commit ab9056ff9bdb3f95db6e7a666d10522d28
On Tue, Feb 28, 2023 at 12:53 AM Mikhail Tyutin wrote:
>
> Fix incorrect register name in RISC-V disassembler for fmv,fabs,fneg
> instructions
>
> Signed-off-by: Mikhail Tyutin
Reviewed-by: Alistair Francis
Alistair
> ---
> disas/riscv.c | 19 ++-
> 1 file changed, 10 inse
On Wed, Mar 8, 2023 at 12:10 AM 김진홍 wrote:
>
> Dear Developer of QEMU.
>
>
>
> I have a question to run QEMU by RISC-V board.
>
>
>
> Currently, sifive has "HiFive Unleashed" and "HiFive Unmatched" boards.
>
>
>
> HiFive Unleashed board is set when executed with "-M sifive_u" option in QEMU
> (v7
Currently, any captured output (via `capture-output`) is segregated into
separate GuestExecStatus fields (`out-data` and `err-data`). This means
that downstream consumers have no way to reassemble the captured data
back into the original stream.
This is relevant for chatty and semi-interactive (ie
Currently, the captured output (via `capture-output`) is segregated into
separate GuestExecStatus fields (`out-data` and `err-data`). This means
that downstream consumers have no way to reassemble the captured data
back into the original stream.
This is relevant for chatty and semi-interactive (ie
Previously capture-output was an optional boolean flag that either
captured all output or captured none. While this is OK in most cases, it
lacks flexibility for more advanced capture cases, such as wanting to
only capture stdout.
This commits refactors guest-exec qapi to take an enum for capture
This commit adds a test to ensure `merged` functions as expected.
We also add a negative test to ensure we haven't regressed previous
functionality.
Signed-off-by: Daniel Xu
---
tests/unit/test-qga.c | 158 +-
1 file changed, 141 insertions(+), 17 deletion
Hi Gerd,
Where did these binaries come from? What commit and how were they built?
Regards,
Simon
On 07.03.23 20:31, Michael S. Tsirkin wrote:
On Tue, Mar 07, 2023 at 07:05:35PM +0300, Vladimir Sementsov-Ogievskiy wrote:
We have DEVICE_DELETED event, that signals that device_del command is
actually completed. But we don't have a counter-part for device_add.
Still it's sensible for SHPC and P
On Tue, 7 Mar 2023 at 23:55, Mark Cave-Ayland
wrote:
>
> The following changes since commit 9832009d9dd2386664c15cc70f6e6bfe062be8bd:
>
> Merge tag 'pull-riscv-to-apply-20230306' of
> https://gitlab.com/palmer-dabbelt/qemu into staging (2023-03-07 12:53:00
> +)
>
> are available in the Git
On Tue, 7 Mar 2023 at 21:21, Alex Bennée wrote:
>
> The following changes since commit 9832009d9dd2386664c15cc70f6e6bfe062be8bd:
>
> Merge tag 'pull-riscv-to-apply-20230306' of
> https://gitlab.com/palmer-dabbelt/qemu into staging (2023-03-07 12:53:00
> +)
>
> are available in the Git repo
Just realized that the subject doesn't mention 'riscv' anywhere.
Yes, this is target/riscv specific. I'll make sure to mention that in the
future versions.
Thanks,
Daniel
On 3/8/23 17:19, Daniel Henrique Barboza wrote:
Hi,
During the review of a series that did some work in the RISCV_FEATUR
On 3/9/23 12:14, Fabiano Rosas wrote:
In preparation to moving the cpu_tcg.c code into a 32-bit, tcg-only
file, move the aa32_max_features function which is shared between
32/64/tcg/non-tcg into cpu.c.
Signed-off-by: Fabiano Rosas
---
target/arm/cpu.c | 69
On 3/9/23 04:13, Weiwei Li wrote:
Remove RISCVCPU argument, and get cfg infomation from CPURISCVState
directly.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
Reviewed-by: Daniel Henrique Barboza
target/riscv/csr.c | 12
1 file changed, 4 insertions(+), 8 del
On 3/9/23 04:13, Weiwei Li wrote:
Use CPURISCVState as argument directly in riscv_cpu_update_mip and
riscv_timer_write_timecmp, since type converts from CPURISCVState to
RISCVCPU in many caller of them and then back to CPURISCVState in them.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang W
On 3/9/23 04:13, Weiwei Li wrote:
Use env_archcpu() to get RISCVCPU pointer from env directly.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
Reviewed-by: Daniel Henrique Barboza
target/riscv/pmu.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git
On 3/9/23 04:13, Weiwei Li wrote:
Use riscv_cpu_cfg(env) instead of env_archcpu().cfg.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
Reviewed-by: Daniel Henrique Barboza
target/riscv/cpu_helper.c | 9 -
target/riscv/csr.c| 40
On 3/9/23 12:14, Fabiano Rosas wrote:
We currently don't have the reading of pauth regs implemented for KVM
so wrap the pauth registration with CONFIG_TCG.
This avoids the build error when using --disable-tcg:
libqemu-aarch64-softmmu.fa.p/target_arm_gdbstub64.c.o: in function
`aarch64_gdb_get_p
On 3/9/23 12:14, Fabiano Rosas wrote:
This code is only relevant when TCG is present in the build. If we try
to build with --disable-tcg we currently get:
libqemu-aarch64-softmmu.fa.p/target_arm_gdbstub.c.o: in function
`m_sysreg_ptr': ../target/arm/gdbstub.c:356: undefined reference to
`arm_v7m
Use tcg_constant_i32 for the bounds.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/tricore/translate.c | 14 +++---
1 file changed, 3 insertions(+), 11 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index a3a5263a5d..
In preparation to moving the cpu_tcg.c code into a 32-bit, tcg-only
file, move the aa32_max_features function which is shared between
32/64/tcg/non-tcg into cpu.c.
Signed-off-by: Fabiano Rosas
---
target/arm/cpu.c | 69
target/arm/cpu_tcg.c | 69 -
In theory this should never happen, as all such instructions
are illegal. This is checked in e.g. gen_lea_mode and
gen_ea_mode_fp but not here. In case something higher up
isn't checking modes properly, return NULL_QREG. This will
result in an illegal instruction exception being raised.
Signed-
Fix incorrect read from rD.
Avoid adding 0 when rA == 0.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Richard Henderson
---
target/ppc/translate.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index df324fc7ff..7
All remaining uses are strictly read-only.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/mips/tcg/mxu_translate.c | 4 +-
target/mips/tcg/translate.c | 56 +++
target/mips/tcg/tx79_translate.c | 4 +-
targe
Move the 64-bit CPUs that are TCG-only:
- cortex-a35
- cortex-a55
- cortex-a72
- cortex-a76
- a64fx
- neoverse-n1
Keep the CPUs that can be used with KVM:
- cortex-a57
- cortex-a53
- max
- host
For the special case "max" CPU, there's a nuance that while KVM/HVF
use the "host" model instead, we st
All uses are strictly read-only.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Richard Henderson
---
target/ppc/translate/fp-impl.c.inc | 26 --
1 file changed, 12 insertions(+), 14 deletions(-)
diff --git a/target/ppc/translat
This exception can be raised by illegal instructions.
Signed-off-by: Richard Henderson
---
linux-user/m68k/cpu_loop.c | 5 -
tests/tcg/m68k/excp-address.c | 32
tests/tcg/m68k/Makefile.target | 1 +
3 files changed, 37 insertions(+), 1 deletion(-)
cre
Initialize a new temp instead of tcg_const_*.
Fix a pasto in a comment.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Richard Henderson
---
target/ppc/translate/vsx-impl.c.inc | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/
Return a constant for an immediate input.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/m68k/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index 44c3ac0bc3..422f4652f1 100644
--
Compute all carry bits in parallel instead of a loop.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Richard Henderson
---
target/ppc/translate/fixedpoint-impl.c.inc | 44 +++---
1 file changed, 23 insertions(+), 21 deletions(-)
diff --git a/target/ppc/translate/fixedpoint
Since we're assigning to cpu_sr_t in the end,
use that as the intermediate temp as well.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/sh4/translate.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/target/sh4/translate.c b/target/s
All remaining uses are strictly read-only.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Richard Henderson
---
target/ppc/translate.c | 142 +
1 file changed, 72 insertions(+), 70 deletions(-)
diff --git a/targe
From: Claudio Fontana
move the module containing cpu models definitions
for 32bit TCG-only CPUs to tcg/ and rename it for clarity.
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
Acked-by: Thomas Huth
Signed-off-by: Fabiano Rosas
---
hw/arm/virt.c | 2
Move all the CONFIG_FOO=y from default.mak into "default y if TCG"
statements in Kconfig. That way they won't be selected when
CONFIG_TCG=n.
I'm leaving CONFIG_ARM_VIRT in default.mak because it allows us to
keep the two default.mak files not empty and keep aarch64-default.mak
including arm-defaul
We are about to enable the build without TCG, so CONFIG_SEMIHOSTING
and CONFIG_ARM_COMPATIBLE_SEMIHOSTING cannot be unconditionally set in
default.mak anymore. So reflect the change in a Kconfig.
Instead of using semihosting/Kconfig, use a target-specific file, so
that the change doesn't affect ot
Use proper enumeration types for input and output.
Use a const array to perform the mapping, with an
assert that the input is valid.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/arm/internals.h | 12 +---
target/arm/tcg/translate-mve.c | 2 +-
All remaining uses are strictly read-only.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/sh4/translate.c | 26 +-
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index 70a45
The file cpu_tcg.c is about to be moved into the tcg/ directory, so
move the register definitions into a new file.
Also move the function declaration to the more appropriate cpregs.h.
Reviewed-by: Richard Henderson
Signed-off-by: Fabiano Rosas
---
target/arm/cortex-regs.c | 69
All remaining uses are strictly read-only.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Richard Henderson
---
target/ppc/translate/vsx-impl.c.inc | 28 ++--
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/target
The migration tests are currently broken for an aarch64 host because
the tests pass no 'machine' and 'cpu' options on the QEMU command
line.
Add a separate class to each architecture so that we can specify
'machine' and 'cpu' options instead of relying on defaults.
Add a skip decorator to keep th
Here it is not trivial to notice first initialization, so explicitly
zero the temps. Use an array for the output, rather than separate
tcg_rd/tcg_rd_hi variables.
Fixes a bug by adding a missing clear_vec_high.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/ar
Changes since v7:
- patch 8: moved calls to qtest_has_accel after g_test_init to avoid
the TAP error;
- moved the avocado patch towards the end of the series so we can
merge the rest without it if needed;
- two new patches to fix regressions due to gdbstub changes.
CI run: https://
The translate.c fix is extracted from a larger patch set.
I then add a test case and fix cpu_loop to raise the proper signal.
r~
Richard Henderson (2):
target/m68k: Reject immediate as destination in gen_ea_mode
linux-user/m68k: Handle EXCP_ADDRESS in cpu_loop
linux-user/m68k/cpu_loop.c
These functions are no longer used.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/tcg/tcg-op.h | 4
include/tcg/tcg.h| 6 --
tcg/tcg.c| 16
3 files changed, 26 deletions(-)
diff --git a/include/tcg/tcg-op.h b/includ
In several instances, a temp is initialized with a
for use as a constant, and then subsequently used
as an unrelated temp. Split them.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/m68k/translate.c | 29 -
1 file changed, 16 inserti
Since PSW_Z = PSW_S, we can move that assignment to the end
and use PSW_Z as a temporary while computing PSW_O.
Use tcg_constant_i32 instead of tcg_const_i32.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/rx/translate.c | 28 +---
1 file
From: Philippe Mathieu-Daudé
Add a manual new job to cross-build the aarch64 target with
only the KVM accelerator enabled (in particular, no TCG).
Re-enable running the similar job on the project Aarch64
custom runner.
Signed-off-by: Philippe Mathieu-Daudé
Signed-off-by: Fabiano Rosas
Reviewe
Allocate a separate temp for modification.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/mips/tcg/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 7018c427be..bbc
While this enumerator has been present since the first commit,
it isn't ever used. The first actual use of round-to-odd came
with SVE, which currently uses float_round_to_odd instead of
the arm-specific enumerator.
Amusingly, the comment about unhandled TIEAWAY has been
out of date since the init
This code is only relevant when TCG is present in the build. If we try
to build with --disable-tcg we currently get:
libqemu-aarch64-softmmu.fa.p/target_arm_gdbstub.c.o: in function
`m_sysreg_ptr': ../target/arm/gdbstub.c:356: undefined reference to
`arm_v7m_get_sp_ptr'
Signed-off-by: Fabiano Ros
It is easy enough to use mov instead of or-with-zero and relying
on the optimizer to fold away the or. Use an array for the output,
rather than separate tcg_res{l,h} variables.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-a64.c | 41
As required, allocate temp separately.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/tricore/translate.c | 268 +++--
1 file changed, 140 insertions(+), 128 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/t
Split out common subroutines for handing rounding mode
changes during translation. Use tcg_constant_i32 and
tcg_temp_new_i32 instead of tcg_const_i32.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate.h | 17
target/arm/tcg/trans
All remaining uses are strictly read-only.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/tricore/translate.c | 127 +++--
1 file changed, 64 insertions(+), 63 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore
All remaining uses are strictly read-only.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/cris/translate.c | 46 +++--
target/cris/translate_v10.c.inc | 26 +--
2 files changed, 34 insertions(+), 38 deletions(-
It is possible to have a build with both TCG and KVM disabled due to
Xen requiring the i386 and x86_64 binaries to be present in an aarch64
host.
If we build with --disable-tcg on the aarch64 host, we will end-up
with a QEMU binary (x86) that does not support TCG nor KVM.
Fix tests that crash or
All uses are strictly read-only.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Richard Henderson
---
target/ppc/power8-pmu-regs.c.inc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/ppc/power8-pmu-regs.c.inc b/target/ppc/
All uses are strictly read-only.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/s390x/tcg/translate.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index 796
All uses are strictly read-only. Most of the obviously so,
as direct arguments to gen_helper_*.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 83 +++--
1 file changed, 42 insertions(+), 41 deletions(-)
di
Replace with tcg_constant_vec*.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 4
tcg/tcg-op-vec.c | 34 ++
tcg/i386/tcg-target.c.inc | 9 -
3 files changed, 6 insertions(+), 41 deletio
These three instances got missed in previous conversion.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tcg-op.c | 12 +++-
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index 1a039a292c..ddab20a6a6 100644
--- a/t
Remove the local definition of rx_abs.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/rx/translate.c | 12 +---
1 file changed, 1 insertion(+), 11 deletions(-)
diff --git a/target/rx/translate.c b/target/rx/translate.c
index 6624414739..998e6e0b7e 10064
Compute both partial results separately and accumulate
at the end, instead of accumulating in the middle.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Richard Henderson
---
target/ppc/translate/vmx-impl.c.inc | 21 +++--
1 file changed
Translators are no longer required to free tcg temporaries.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/mips/tcg/translate.c | 537 +---
1 file changed, 14 insertions(+), 523 deletions(-)
diff --git a/target/mips/tcg/translate
From: Anton Johansson
Signed-off-by: Anton Johansson
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
Reviewed-by: Richard Henderson
Message-Id: <20230306175230.7110-17-a...@rev.ng>
Signed-off-by: Richard Henderson
---
target/riscv/cpu-param.h | 1 -
1 file changed, 1 deletion(-
Common subroutine for LDR and LWR.
Use tcg_constant_tl of ~1 instead of tcg_const_tl of 0x..fe.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/mips/tcg/translate.c | 116 +---
1 file changed, 40 insertions(+), 76 deletions(-)
dif
We currently don't have the reading of pauth regs implemented for KVM
so wrap the pauth registration with CONFIG_TCG.
This avoids the build error when using --disable-tcg:
libqemu-aarch64-softmmu.fa.p/target_arm_gdbstub64.c.o: in function
`aarch64_gdb_get_pauth_reg': ../target/arm/gdbstub64.c:233
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/ppc/translate/vmx-impl.c.inc | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/ppc/translate/vmx-impl.c.inc
b/target/ppc/translate/vmx-impl.c.inc
index ee656d6a44..7af6d7217d 100644
--- a
All remaining uses are strictly read-only.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Richard Henderson
---
target/ppc/translate/vmx-impl.c.inc | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/ppc/translate/vmx-i
Translators are no longer required to free tcg temporaries.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/mips/tcg/octeon_translate.c | 23 ---
1 file changed, 23 deletions(-)
diff --git a/target/mips/tcg/octeon_translate.c
b/target/mips/t
Translators are no longer required to free tcg temporaries.
Acked-by: David Hildenbrand
Reviewed-by: Ilya Leoshkevich
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/s390x/tcg/translate.c | 105 ---
1 file changed, 105 deletions(
Reorg temporary usage so that we can use tcg_constant_i32.
tcg_gen_deposit_i32 already has a width == 32 special case,
so remove the check here.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate.c | 13 +
1 file changed, 5 insertions(+
While temp3 could simply be initialized with tcg_constant_i32,
the renaming makes the purpose clearer.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/tricore/translate.c | 56 ++
1 file changed, 27 insertions(+), 29 deletions(
Common subroutine for LDL and LWL.
Use tcg_constant_tl instead of tcg_const_tl and t2.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/mips/tcg/translate.c | 106
1 file changed, 36 insertions(+), 70 deletions(-)
diff --git a
Move the body out of this large macro.
Use tcg_constant_i64.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/ppc/translate/vmx-impl.c.inc | 95 +++--
1 file changed, 49 insertions(+), 46 deletions(-)
diff --git a/target/ppc/translate/vmx-
From: Anton Johansson
Signed-off-by: Anton Johansson
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
Reviewed-by: Richard Henderson
Message-Id: <20230306175230.7110-13-a...@rev.ng>
Signed-off-by: Richard Henderson
---
target/mips/cpu-param.h | 1 -
1 file changed, 1 deletion(-)
It is easy enough to use mov instead of or-with-zero
and relying on the optimizer to fold away the or.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-a64.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/target/arm/t
Initialize rmode to -1 instead of keeping two variables.
This is already used elsewhere in translate-a64.c.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-a64.c | 34 ++
1 file changed, 6 insertions(+), 28 deleti
Push tcg_constant_tl into the shift argument directly.
Since t1 no longer exists as a temp, replace with lo1,
whose last use was just above.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/sparc/translate.c | 14 ++
1 file changed, 6 insertions(+), 8
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