From: Chen Baozi
Add implementation defined registers for neoverse-n1 which
would be accessed by TF-A. Since there is no DSU in Qemu,
CPUCFR_EL1.SCU bit is set to 1 to avoid DSU registers definition.
Signed-off-by: Chen Baozi
Reviewed-by: Peter Maydell
Tested-by: Marcin Juszkiewicz
Message-id
Hi Mostafa,
On 3/21/23 14:06, Mostafa Saleh wrote:
> Hi Eric,
>
>>> + * According to 6.3.6 SMMU_IDR5, OAS must match the system physical
>>> address
>>> + * size.
>>> + */
>>> +ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0));
>>> +uint8_t oas = FIELD_EX64(armcpu->isar.id_aa64mmfr0,
From: Viktor Prutyanov
Originally elf2dmp were added with some code style issues,
especially in pe.h header, and some were introduced by
2d0fc797faaa73fbc1d30f5f9e90407bf3dd93f0. Fix them now.
Signed-off-by: Viktor Prutyanov
Reviewed-by: Annie Li
Message-id: 2023011246.883679-2-vik...@dayn
On 3/21/2023 8:58 PM, liweiwei wrote:
>
> On 2023/3/21 14:37, fei2...@intel.com wrote:
>> From: Fei Wu
>>
>> Kernel needs to access user mode memory e.g. during syscalls, the window
>> is usually opened up for a very limited time through MSTATUS.SUM, the
>> overhead is too much if tlb_flush() get
From: Viktor Prutyanov
Move out PE directory search functionality to be reused not only
for Debug Directory processing but for arbitrary PE directory.
Signed-off-by: Viktor Prutyanov
Reviewed-by: Annie Li
Message-id: 2023011246.883679-3-vik...@daynix.com
Signed-off-by: Peter Maydell
---
This is a documentation change for I2C TPM device support.
Qemu already supports devices attached to ISA and sysbus.
This drop adds support for the I2C bus attached TPM devices.
Signed-off-by: Ninad Palsule
---
docs/specs/tpm.rst | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff -
Qemu already supports devices attached to ISA and sysbus. This drop adds
support for the I2C bus attached TPM devices.
This commit includes changes for the common code.
- Added support for the new checksum registers which are required for
the I2C support. The checksum calculation is handled in t
Unfortunately a bug in older versions of gdb means that they will
crash if QEMU sends them the aarch64-pauth.xml. This bug is fixed in
gdb commit 1ba3a3222039eb25, and there are plans to backport that to
affected gdb release branches, but since the bug affects gdb 9
through 12 it is very widely de
Qemu already supports devices attached to ISA and sysbus. This drop adds
support for the I2C bus attached TPM devices. I2C model only supports
TPM2 protocol.
This commit includes changes for the common code.
- Added I2C emulation model. Logic was added in the model to temporarily
cache the data
This drop adds support for the TPM devices attached to the I2C bus. It
only supports the TPM2 protocol. You need to run it with the external
TPM emulator like swtpm. I have tested it with swtpm.
I have refered to the work done by zhdan...@meta.com but at the core
level out implementation is differ
The markup for the Arm CPU feature documentation is incorrect,
and results in the HTML not rendering correctly -- the first
line of each description is rendered in boldface as if it
were part of the option name.
Reformat to match the styling used in cpu-models-x86.rst.inc.
Resolves: https://gitla
From: Guenter Roeck
The i.MX USB Phy driver does not check register ranges, resulting in out of
bounds accesses if an attempt is made to access non-existing PHY registers.
Add range check and conditionally report bad accesses to fix the problem.
While at it, also conditionally log attempted writ
From: Viktor Prutyanov
Since its inception elf2dmp has checked MZ signatures within an
address space above IDT[0] interrupt vector and took first PE image
found as Windows Kernel.
But in Windows Server 2022 memory dump this address space range is
full of invalid PE fragments and the tool must che
The cadence UART attempts to avoid allowing the guest to set invalid
baud rate register values in the uart_write() function. However it
does the "mask to the size of the register field" and "check for
invalid values" in the wrong order, which means that a malicious
guest can get a bogus value into
ydell/qemu-arm.git
tags/pull-target-arm-20230321
for you to fetch changes up to 5787d17a42f7af4bd117e5d6bfa54b1fdf93c255:
target/arm: Don't advertise aarch64-pauth.xml to gdb (2023-03-21 13:19:08
+)
target-arm queue:
*
Hi Eric,
> > + * According to 6.3.6 SMMU_IDR5, OAS must match the system physical
> > address
> > + * size.
> > + */
> > +ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0));
> > +uint8_t oas = FIELD_EX64(armcpu->isar.id_aa64mmfr0, ID_AA64MMFR0,
> > PARANGE);
> is this working in accel
On 3/21/23 13:16, Cédric Le Goater wrote:
+ /*
+ * GCC13 [-Werror=dangling-pointer=] complains that the local variable
+ * 'slice' is being stored in the global list 'ctx->bh_slice_list'.
+ */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wdangling-pointer="
On 2023/3/21 14:37, fei2...@intel.com wrote:
From: Fei Wu
Kernel needs to access user mode memory e.g. during syscalls, the window
is usually opened up for a very limited time through MSTATUS.SUM, the
overhead is too much if tlb_flush() gets called for every SUM change.
This patch saves addre
Philippe Mathieu-Daudé wrote:
> Under MSYS2, G_NORETURN is expanded to '[[noreturn]]'.
> Simpler to use the same definition everywhere, unifying
> the code style.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Juan Quintela
On 2023/3/21 20:00, Wu, Fei wrote:
On 3/21/2023 5:47 PM, liweiwei wrote:
On 2023/3/21 17:14, Wu, Fei wrote:
On 3/21/2023 4:50 PM, liweiwei wrote:
On 2023/3/21 16:40, Wu, Fei wrote:
On 3/21/2023 4:28 PM, liweiwei wrote:
On 2023/3/21 14:37,fei2...@intel.com wrote:
From: Fei Wu
Kernel needs
On Tue, Mar 21 2023, Peter Maydell wrote:
> On Thu, 16 Mar 2023 at 11:41, Peter Maydell wrote:
>>
>> On Thu, 16 Mar 2023 at 11:11, Cornelia Huck wrote:
>> >
>> > On Thu, Mar 16 2023, Peter Maydell wrote:
>> >
>> > > The markup for the Arm CPU feature documentation is incorrect,
>> > > and resu
On 3/21/23 12:57, Paolo Bonzini wrote:
On 3/21/23 09:33, Cédric Le Goater wrote:
+static void aio_bh_slice_insert(AioContext *ctx, BHListSlice *slice)
+{
+ QSIMPLEQ_INSERT_TAIL(&ctx->bh_slice_list, slice, next);
+}
+
/* Multiple occurrences of aio_bh_poll cannot be called concurrently. */
On Fri, Mar 10, 2023 at 10:16 AM Lawrence Hunter
wrote:
>
> This patchset provides an implementation for Zvkb, Zvkned, Zvknh, Zvksh,
> Zvkg, and Zvksed of the draft RISC-V vector cryptography extensions as per
> the 20230303 version of the specification(1) (1fcbb30). Please note that the
> Zvkt
On Fri, Mar 10, 2023 at 5:06 PM Lawrence Hunter
wrote:
>
> From: Kiran Ostrolenk
>
> Summary of refactoring:
>
> * take some functions/macros out of `vector_helper` and put them in a
> new module called `vector_internals`
>
> * factor the non SEW-specific stuff out of `GEN_OPIVV_TRANS` into
> fun
On 3/21/2023 5:47 PM, liweiwei wrote:
>
> On 2023/3/21 17:14, Wu, Fei wrote:
>> On 3/21/2023 4:50 PM, liweiwei wrote:
>>> On 2023/3/21 16:40, Wu, Fei wrote:
On 3/21/2023 4:28 PM, liweiwei wrote:
> On 2023/3/21 14:37, fei2...@intel.com wrote:
>> From: Fei Wu
>>
>> Kernel needs
On 3/21/23 09:33, Cédric Le Goater wrote:
+static void aio_bh_slice_insert(AioContext *ctx, BHListSlice *slice)
+{
+QSIMPLEQ_INSERT_TAIL(&ctx->bh_slice_list, slice, next);
+}
+
/* Multiple occurrences of aio_bh_poll cannot be called concurrently. */
int aio_bh_poll(AioContext *ctx)
{
@@
On Thu, 16 Mar 2023 at 11:41, Peter Maydell wrote:
>
> On Thu, 16 Mar 2023 at 11:11, Cornelia Huck wrote:
> >
> > On Thu, Mar 16 2023, Peter Maydell wrote:
> >
> > > The markup for the Arm CPU feature documentation is incorrect,
> > > and results in the HTML not rendering correctly -- the first
On Fri, Mar 17, 2023 at 4:29 PM Gavin Shan wrote:
>
> There are two RISCV machines where NUMA is aware: 'virt' and 'spike'.
> Both of them are required to follow cluster-NUMA-node boundary. To
> enable the validation to warn about the irregular configuration where
> multiple CPUs in one cluster ha
On Fri, Mar 17, 2023 at 4:29 PM Gavin Shan wrote:
>
> For some architectures like ARM64, multiple CPUs in one cluster can be
> associated with different NUMA nodes, which is irregular configuration
> because we shouldn't have this in baremetal environment. The irregular
> configuration causes Linu
Hi, Richard
在 2022/12/25 上午5:12, Richard Henderson 写道:
On 12/24/22 00:16, Song Gao wrote:
+TRANS(vreplve_b, gen_vvr, gen_helper_vreplve_b)
+TRANS(vreplve_h, gen_vvr, gen_helper_vreplve_h)
+TRANS(vreplve_w, gen_vvr, gen_helper_vreplve_w)
+TRANS(vreplve_d, gen_vvr, gen_helper_vreplve_d)
+TRANS(vr
A recent attempt to let avocado run more tests on the CentOS stream
build failed because there was no gating on the multiprocess feature.
Like missing accelerators avocado should gracefully skip when the
feature is not enabled.
In this case we use the existence of the proxy device as a proxy for
m
On Tue, Mar 21, 2023 at 09:33:20AM +0100, Cédric Le Goater wrote:
> From: Cédric Le Goater
>
> GCC13 reports an error :
>
> ../util/async.c: In function ‘aio_bh_poll’:
> include/qemu/queue.h:303:22: error: storing the address of local variable
> ‘slice’ in ‘*ctx.bh_slice_list.sqh_last’ [-Werror
> -Original Message-
> From: qemu-devel-bounces+sriram.yagnaraman=est.t...@nongnu.org
> On Behalf
> Of Sriram Yagnaraman
> Sent: Friday, 17 March 2023 16:26
> To: Akihiko Odaki
> Cc: qemu-devel@nongnu.org; Jason Wang ; Dmitry
> Fleytman ; quint...@redhat.com; Philippe
> Mathieu-Daudé
>
On 3/21/23 05:33, Cédric Le Goater wrote:
From: Cédric Le Goater
GCC13 reports an error:
../target/ppc/excp_helper.c:2625:6: error: conflicting types for
‘helper_pminsn’ due to enum/integer mismatch; have ‘void(CPUPPCState *,
powerpc_pm_insn_t)’ {aka ‘void(struct CPUArchState *, powerpc_p
Il mar 21 mar 2023, 11:30 Daniel P. Berrangé ha
scritto:
> On Tue, Mar 21, 2023 at 11:22:33AM +0100, Paolo Bonzini wrote:
> > On 3/21/23 09:33, Cédric Le Goater wrote:
> > > From: Cédric Le Goater
> > >
> > > GCC13 reports an error :
> > >
> > > ../util/async.c: In function ‘aio_bh_poll’:
> > > i
On 17/03/2023 14:11, Pavel Pisa wrote:
Hello Ben,
thanks for update.
On Thursday 16 of March 2023 13:41:13 Ben Dooks wrote:
From: Ben Dooks
Add support for Microchip MCP25625 SPI based CAN controller which is
very similar to the MCP2515 (and covered by the same Linux driver).
This can be ad
On Tue, Mar 21, 2023 at 11:22:33AM +0100, Paolo Bonzini wrote:
> On 3/21/23 09:33, Cédric Le Goater wrote:
> > From: Cédric Le Goater
> >
> > GCC13 reports an error :
> >
> > ../util/async.c: In function ‘aio_bh_poll’:
> > include/qemu/queue.h:303:22: error: storing the address of local variable
From: qianfan Zhao
R40 has two ethernet controllers named as emac and gmac. The emac is
compatibled with A10, and the GMAC is compatibled with H3.
Signed-off-by: qianfan Zhao
---
hw/arm/allwinner-r40.c | 48 --
hw/arm/bananapi_m2u.c | 3 +++
in
From: qianfan Zhao
This patch adds minimal support for AXP-221 PMU and connect it to
bananapi M2U board.
Signed-off-by: qianfan Zhao
---
hw/arm/Kconfig| 1 +
hw/arm/bananapi_m2u.c | 5 ++
hw/misc/Kconfig | 4 +
hw/misc/axp221.c | 196 +++
From: qianfan Zhao
Add documents for Banana Pi M2U
Signed-off-by: qianfan Zhao
---
docs/system/arm/bananapi_m2u.rst | 138 +++
1 file changed, 138 insertions(+)
create mode 100644 docs/system/arm/bananapi_m2u.rst
diff --git a/docs/system/arm/bananapi_m2u.rst b/doc
From: qianfan Zhao
R40 has SAMP_DL_REG register and mmc2 controller has only 8K dma buffer.
Fix it's compatible string.
Signed-off-by: qianfan Zhao
---
hw/arm/allwinner-r40.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/hw/arm/allwinner-r40.c b/hw/arm/allwinner-
From: qianfan Zhao
TWI(i2c) is designed to be used as an interface between CPU host and the
serial 2-Wire bus. It can support all standard 2-Wire transfer, can be
operated in standard mode(100kbit/s) or fast-mode, supporting data rate
up to 400kbit/s.
Signed-off-by: qianfan Zhao
---
hw/arm/all
From: qianfan Zhao
Add test case for booting from initrd and sd card.
Signed-off-by: qianfan Zhao
---
tests/avocado/boot_linux_console.py | 173
1 file changed, 173 insertions(+)
diff --git a/tests/avocado/boot_linux_console.py
b/tests/avocado/boot_linux_console.
From: qianfan Zhao
The CCU provides the registers to program the PLLs and the controls
most of the clock generation, division, distribution, synchronization
and gating.
This commit adds support for the Clock Control Unit which emulates
a simple read/write register interface.
Signed-off-by: qian
From: qianfan Zhao
A64's sd register was similar to H3, and it introduced a new register
named SAMP_DL_REG location at 0x144. The dma descriptor buffer size of
mmc2 is only 8K and the other mmc controllers has 64K.
Signed-off-by: qianfan Zhao
---
hw/sd/allwinner-sdhost.c | 70 +
From: qianfan Zhao
Types of memory that the SDRAM controller supports are DDR2/DDR3
and capacities of up to 2GiB. This commit adds emulation support
of the Allwinner R40 SDRAM controller.
This driver only support 256M, 512M and 1024M memory now.
Signed-off-by: qianfan Zhao
---
hw/arm/allwinne
From: qianfan Zhao
Allwinner R40 (sun8i) SoC features a Quad-Core Cortex-A7 ARM CPU,
and a Mali400 MP2 GPU from ARM. It's also known as the Allwinner T3
for In-Car Entertainment usage, A40i and A40pro are variants that
differ in applicable temperatures range (industrial and military).
This patch
From: qianfan Zhao
*** history ***
# v1: 2023-03-21
The first version which add allwinner-r40 support, supported features:
+ ccu
+ dram controller
+ uart
+ i2c and pmic(axp221)
+ sdcard
+ emac/gmac
Also provide a test case under avocado, running quickly test:
$ AVOCADO_ALLOW_LARGE_STORAGE=ye
From: qianfan Zhao
R40 has eight UARTs, support both 16450 and 16550 compatible modes.
Signed-off-by: qianfan Zhao
---
hw/arm/allwinner-r40.c | 32
include/hw/arm/allwinner-r40.h | 7 +++
2 files changed, 39 insertions(+)
diff --git a/hw/arm/allwi
On 3/21/23 09:33, Cédric Le Goater wrote:
From: Cédric Le Goater
GCC13 reports an error :
../util/async.c: In function ‘aio_bh_poll’:
include/qemu/queue.h:303:22: error: storing the address of local variable
‘slice’ in ‘*ctx.bh_slice_list.sqh_last’ [-Werror=dangling-pointer=]
303 | (hea
On 3/21/23 01:34, LIU Zhiwei wrote:
Vector implicitly enables zve64d, zve64f, zve32f sub extensions. As vector
only requires PRIV_1_10_0, these sub extensions should not require priv version
higher than that.
The same for Zfh.
Signed-off-by: LIU Zhiwei
---
Reviewed-by: Daniel Henrique Bar
Hello everyone, I am a Third-Year University Student from India. I am
interested in implementing the RDP server for Qemu in Rust [1]. I have
already introduced myself to the mailing list earlier.
In short, the project will involve the following:
1. Improve and implement missing portions required f
Use the FloatRelation enum to hold the comparison result (missed
in commit 71bfd65c5f "softfloat: Name compare relation enum").
Inspired-by: Cédric Le Goater
Signed-off-by: Philippe Mathieu-Daudé
---
target/m68k/fpu_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
On 2023/3/21 17:14, Wu, Fei wrote:
On 3/21/2023 4:50 PM, liweiwei wrote:
On 2023/3/21 16:40, Wu, Fei wrote:
On 3/21/2023 4:28 PM, liweiwei wrote:
On 2023/3/21 14:37, fei2...@intel.com wrote:
From: Fei Wu
Kernel needs to access user mode memory e.g. during syscalls, the
window
is usually o
On 21/3/23 09:33, Cédric Le Goater wrote:
From: Cédric Le Goater
GCC13 reports an error :
../target/s390x/tcg/fpu_helper.c:123:5: error: conflicting types for
‘float_comp_to_cc’ due to enum/integer mismatch; have ‘int(CPUS390XState *,
FloatRelation)’ {aka ‘int(struct CPUArchState *, FloatRel
> 2023年3月15日 08:18，Philippe Mathieu-Daudé 写道：
>
> On 11/3/23 13:39, Jiaxun Yang wrote:
>>> 2023年3月9日 12:32，Philippe Mathieu-Daudé 写道：
>>>
>>> Hi Jiaxun,
>>>
>>> On 11/2/23 18:34, Jiaxun Yang wrote:
Previously switchable NaN2008 requires fcsr31.nan2008 to be writable
for guest. How
On 3/21/2023 4:50 PM, liweiwei wrote:
>
> On 2023/3/21 16:40, Wu, Fei wrote:
>> On 3/21/2023 4:28 PM, liweiwei wrote:
>>> On 2023/3/21 14:37, fei2...@intel.com wrote:
From: Fei Wu
Kernel needs to access user mode memory e.g. during syscalls, the
window
is usually opened u
Hi Yuval,
Dropping and . This is CVE-2023-1544.
The patch looks good to me. Thank you.
On Mon, Mar 20, 2023 at 1:07 PM Yuval Shaia wrote:
>
> Hi,
> Patch is currently under review.
> From my end, it was tested and proved to solve the problem.
>
> To follow up you may need to check qemu-devel@n
From: Marc-André Lureau
For ex, when resetting the xlnx-zcu102 machine:
(lldb) bt
* thread #1, queue = 'com.apple.main-thread', stop reason =
EXC_BAD_ACCESS (code=1, address=0x50)
* frame #0: 0x10020a740 gd_vc_send_chars(vc=0x0) at
gtk.c:1759:41 [opt]
frame #1: 0x100636264 qemu_c
From: Marc-André Lureau
VNC code relies on con==NULL to mean the default console.
Fixes:
https://gitlab.com/qemu-project/qemu/-/issues/1548
Fixes: commit 385ac97f8 ("ui: keep current cursor with QemuConsole")
Signed-off-by: Marc-André Lureau
Reported-by: Helge Konetzka
Reviewed-by: Philippe M
From: Marc-André Lureau
Close the given file descriptor, but returns the underlying SOCKET.
Signed-off-by: Marc-André Lureau
Reviewed-by: Daniel P. Berrangé
Message-Id: <20230320133643.1618437-2-marcandre.lur...@redhat.com>
---
include/sysemu/os-win32.h | 15 ++--
util/oslib-win32.c
From: Marc-André Lureau
Do not attempt to move the pointer if the widget is not yet realized.
The mouse cursor is placed to the corner of the screen, on X11 at least,
as x_root and y_root are then miscalculated. (this is not reproducible
on Wayland, because Gtk doesn't implement device warping th
From: Marc-André Lureau
-display dbus is not currently available to win32 users, so it's not
considered a regression.
Note also the close() leak fix in case of error.
Signed-off-by: Marc-André Lureau
Reviewed-by: Daniel P. Berrangé
Message-Id: <20230320133643.1618437-4-marcandre.lur...@redhat
From: Marc-André Lureau
The following changes since commit aa9e7fa4689d1becb2faf67f65aafcbcf664f1ce:
Merge tag 'edk2-stable202302-20230320-pull-request' of
https://gitlab.com/kraxel/qemu into staging (2023-03-20 13:43:35 +)
are available in the Git repository at:
https://gitlab.com/ma
From: Erico Nunes
This workaround was put in place in the original implementation almost
10 years ago, considering a very old SDL2 version. Currently it prevents
users to run in a wayland-only environment without manually forcing the
backend.
The SDL2 wayland backend has been supported by distrib
From: Marc-André Lureau
Spice uses SOCKET on win32, but QEMU now uses file-descriptors.
Fixes "8.0.0rc0 Regression: spicy windows doesn't open":
https://gitlab.com/qemu-project/qemu/-/issues/1549
Fixes: commit abe34282b ("win32: avoid mixing SOCKET and file descriptor space")
Signed-off-by: Mar
On 2023/3/21 16:40, Wu, Fei wrote:
On 3/21/2023 4:28 PM, liweiwei wrote:
On 2023/3/21 14:37, fei2...@intel.com wrote:
From: Fei Wu
Kernel needs to access user mode memory e.g. during syscalls, the window
is usually opened up for a very limited time through MSTATUS.SUM, the
overhead is too m
On 3/20/23 16:34, Philippe Mathieu-Daudé wrote:
> On 20/3/23 16:23, Claudio Fontana wrote:
>> Hi Alex, all,
>>
>> again, this moves TCG-only code to common code, no?
>
> Oh, good point.
>
>> Even if this happens to work, the idea is to avoid adding unneeded accel TCG
>> code to a KVM-only binary
On Tue, Mar 21, 2023 at 01:52:22PM +0530, Ani Sinha wrote:
> On Mon, Mar 20, 2023 at 3:08 PM Gerd Hoffmann wrote:
> >
> > Recent edk2 versions don't boot with very small numa nodes.
> > Bump the size from 64M to 128M.
>
> Can you please add the ASL diff between the binary blobs as a result
> of t
On 3/21/2023 4:28 PM, liweiwei wrote:
>
> On 2023/3/21 14:37, fei2...@intel.com wrote:
>> From: Fei Wu
>>
>> Kernel needs to access user mode memory e.g. during syscalls, the window
>> is usually opened up for a very limited time through MSTATUS.SUM, the
>> overhead is too much if tlb_flush() get
Hi all,
I start a VM in openstack, and openstack use libvirt to start qemu VM, but
now log show this ERROR.
Is there any one know this?
The ERROR log from /var/log/libvirt/qemu/instance-000e.log
```
2023-03-14T10:09:17.674114Z qemu-system-x86_64: kvm_set_user_memory_region:
KVM_SET_USER_MEMOR
Hello,
I activated a GH workflow using fedora rawhide and found out that
there were a couple of compile breakage with the new GCC. Here are
fixes, the first requiring more attention.
Thanks,
C.
Cédric Le Goater (3):
async: Suppress GCC13 false positive in aio_bh_poll()
target/s390x: Fix fl
From: Cédric Le Goater
GCC13 reports an error :
../target/s390x/tcg/fpu_helper.c:123:5: error: conflicting types for
‘float_comp_to_cc’ due to enum/integer mismatch; have ‘int(CPUS390XState *,
FloatRelation)’ {aka ‘int(struct CPUArchState *, FloatRelation)’}
[-Werror=enum-int-mismatch]
123
From: Cédric Le Goater
GCC13 reports an error:
../target/ppc/excp_helper.c:2625:6: error: conflicting types for
‘helper_pminsn’ due to enum/integer mismatch; have ‘void(CPUPPCState *,
powerpc_pm_insn_t)’ {aka ‘void(struct CPUArchState *, powerpc_pm_insn_t)’}
[-Werror=enum-int-mismatch]
2625
From: Cédric Le Goater
GCC13 reports an error :
../util/async.c: In function ‘aio_bh_poll’:
include/qemu/queue.h:303:22: error: storing the address of local variable
‘slice’ in ‘*ctx.bh_slice_list.sqh_last’ [-Werror=dangling-pointer=]
303 | (head)->sqh_last = &(elm)->field.sqe_next;
On 2023/3/21 14:37, fei2...@intel.com wrote:
From: Fei Wu
Kernel needs to access user mode memory e.g. during syscalls, the window
is usually opened up for a very limited time through MSTATUS.SUM, the
overhead is too much if tlb_flush() gets called for every SUM change.
This patch saves addre
On Mon, Mar 20, 2023 at 3:08 PM Gerd Hoffmann wrote:
>
> Signed-off-by: Gerd Hoffmann
> ---
> tests/qtest/bios-tables-test-allowed-diff.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
> b/tests/qtest/bios-tables-test-allowed-diff.h
> index
On Mon, Mar 20, 2023 at 3:08 PM Gerd Hoffmann wrote:
>
> Recent edk2 versions don't boot with very small numa nodes.
> Bump the size from 64M to 128M.
Can you please add the ASL diff between the binary blobs as a result
of the change?
Otherwise.
>
> Signed-off-by: Gerd Hoffmann
Reviewed-by: Ani
On Tue, Mar 21, 2023 at 11:21 AM Jason Wang wrote:
>
> On Tue, Mar 21, 2023 at 12:20 AM Cindy Lu wrote:
> >
> > 1. The vIOMMU support will make vDPA can work in IOMMU mode. This
> > will fix security issues while using the no-IOMMU mode.
> > To support this feature we need to add new functions fo
Hi
On Tue, Mar 7, 2023 at 4:32 PM wrote:
>
> From: Marc-André Lureau
>
> This seems to be the preferred style.
>
> The EditorConfig property is not supported by all editors:
> https://github.com/editorconfig/editorconfig/wiki/EditorConfig-Properties#max_line_length
>
> Signed-off-by: Marc-André
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