QMP command set-vcpu-dirty-limit hangs

Watch this: $ qemu-system-x86_64 -S -display none -qmp stdio -accel kvm,dirty-ring-size=1024 {"QMP": {"version": {"qemu": {"micro": 90, "minor": 2, "major": 7}, "package": "v8.0.0-rc0-15-g918ee397b6-dirty"}, "capabilities": ["oob"]}} {"execute": "qmp_capabilities"} {"return": {}}

QMP command dumpdtb crash bug

Watch this: $ gdb --args ../qemu/bld/qemu-system-aarch64 -S -M virt -display none -qmp stdio [...] (gdb) r [...] {"QMP": {"version": {"qemu": {"micro": 50, "minor": 2, "major": 7}, "package": "v7.2.0-2331-gda89f78a7d"}, "capabilities": ["oob"]}} [New Thread 0x7fffed62c6c0

Re: [PATCH v4 1/2] target/riscv: separate priv from mmu_idx

On 3/23/2023 2:00 PM, Wu, Fei wrote: > On 3/23/2023 1:37 PM, LIU Zhiwei wrote: >> >> On 2023/3/23 10:44, Fei Wu wrote: >>> Currently it's assumed the 2 low bits of mmu_idx map to privilege mode, >>> this assumption won't last as we are about to add more mmu_idx. >> For patch set has more than 1 pat

Re: [PATCH v4 1/2] target/riscv: separate priv from mmu_idx

On 3/23/2023 1:37 PM, LIU Zhiwei wrote: > > On 2023/3/23 10:44, Fei Wu wrote: >> Currently it's assumed the 2 low bits of mmu_idx map to privilege mode, >> this assumption won't last as we are about to add more mmu_idx. > For patch set has more than 1 patch, usually add a cover letter. This is co

Re: About the instance_finalize callback in VFIO PCI

On Wed, Mar 22, 2023 at 12:22:27PM -0600, Alex Williamson wrote: > On Wed, 22 Mar 2023 09:10:20 -0400 > Yang Zhong wrote: > > > On Wed, Mar 22, 2023 at 01:56:13PM +0100, Cédric Le Goater wrote: > > > On 3/22/23 13:28, Yang Zhong wrote: > > > > On Tue, Mar 21, 2023 at 06:30:14PM +0100, Cédric Le

Re: [BUG][KVM_SET_USER_MEMORY_REGION] KVM_SET_USER_MEMORY_REGION failed

This is happened in ubuntu22.04. QEMU is install by apt like this: apt install -y qemu qemu-kvm qemu-system and QEMU version is 6.2.0 Simon Jones Simon Jones 于2023年3月21日周二 08:40写道： > > > Hi all, > > I start a VM in openstack, and openstack use libvirt to start qemu VM, but > now log sho

Re: [PATCH v4 1/2] target/riscv: separate priv from mmu_idx

On 2023/3/23 10:44, Fei Wu wrote: Currently it's assumed the 2 low bits of mmu_idx map to privilege mode, this assumption won't last as we are about to add more mmu_idx. For patch set has more than 1 patch, usually add a cover letter. Signed-off-by: Fei Wu --- target/riscv/cpu.h

[PATCH v8 2/4] virtio-blk: add zoned storage emulation for zoned devices

This patch extends virtio-blk emulation to handle zoned device commands by calling the new block layer APIs to perform zoned device I/O on behalf of the guest. It supports Report Zone, four zone oparations (open, close, finish, reset), and Append Zone. The VIRTIO_BLK_F_ZONED feature bit will only

[PATCH v8 4/4] virtio-blk: add some trace events for zoned emulation

Signed-off-by: Sam Li Reviewed-by: Stefan Hajnoczi --- hw/block/trace-events | 7 +++ hw/block/virtio-blk.c | 12 2 files changed, 19 insertions(+) diff --git a/hw/block/trace-events b/hw/block/trace-events index 2c45a62bd5..34be8b9135 100644 --- a/hw/block/trace-events +++ b/

[PATCH v8 3/4] block: add accounting for zone append operation

Taking account of the new zone append write operation for zoned devices, BLOCK_ACCT_ZONE_APPEND enum is introduced as other I/O request type (read, write, flush). Signed-off-by: Sam Li --- block/qapi-sysemu.c| 11 +++ block/qapi.c | 18 +++ hw/block/virtio-blk.c

[PATCH v8 1/4] include: update virtio_blk headers to v6.3-rc1

Use scripts/update-linux-headers.sh to update headers to 6.3-rc1. Signed-off-by: Sam Li Reviewed-by: Stefan Hajnoczi Reviewed-by: Dmitry Fomichev --- include/standard-headers/drm/drm_fourcc.h| 12 +++ include/standard-headers/linux/ethtool.h | 48 - include/standard-headers/l

[PATCH v8 0/4] Add zoned storage emulation to virtio-blk driver

This patch adds zoned storage emulation to the virtio-blk driver. The patch implements the virtio-blk ZBD support standardization that is recently accepted by virtio-spec. The link to related commit is at https://github.com/oasis-tcs/virtio-spec/commit/b4e8efa0fa6c8d844328090ad15db65af8d7d981 Th

[PATCH v7 3/4] qemu-iotests: test zone append operation

The patch tests zone append writes by reporting the zone wp after the completion of the call. "zap -p" option can print the sector offset value after completion, which should be the start sector where the append write begins. Signed-off-by: Sam Li --- qemu-io-cmds.c | 75

[PATCH v7 1/4] file-posix: add tracking of the zone write pointers

Since Linux doesn't have a user API to issue zone append operations to zoned devices from user space, the file-posix driver is modified to add zone append emulation using regular writes. To do this, the file-posix driver tracks the wp location of all zones of the device. It uses an array of uint64_

[PATCH v7 4/4] block: add some trace events for zone append

Signed-off-by: Sam Li Reviewed-by: Dmitry Fomichev --- block/file-posix.c | 3 +++ block/trace-events | 2 ++ 2 files changed, 5 insertions(+) diff --git a/block/file-posix.c b/block/file-posix.c index 60ad3970f3..9866d073f5 100644 --- a/block/file-posix.c +++ b/block/file-posix.c @@ -2497,6 +2

[PATCH v7 2/4] block: introduce zone append write for zoned devices

A zone append command is a write operation that specifies the first logical block of a zone as the write position. When writing to a zoned block device using zone append, the byte offset of the call may point at any position within the zone to which the data is being appended. Upon completion the d

[PATCH v7 0/4] Add zone append write for zoned device

This patch series add zone append operation based on the previous zoned device support part. The file-posix driver is modified to add zone append emulation using regular writes. v7: - address review comments * fix wp assignment [Stefan] * fix reset_all cases, skip R/O & offline zones [Dmitry,

[PATCH v17 3/8] block: add block layer APIs resembling Linux ZonedBlockDevice ioctls

Add zoned device option to host_device BlockDriver. It will be presented only for zoned host block devices. By adding zone management operations to the host_block_device BlockDriver, users can use the new block layer APIs including Report Zone and four zone management operations (open, close, finis

[PATCH v17 8/8] docs/zoned-storage: add zoned device documentation

Add the documentation about the zoned device support to virtio-blk emulation. Signed-off-by: Sam Li Reviewed-by: Stefan Hajnoczi Reviewed-by: Damien Le Moal Reviewed-by: Dmitry Fomichev --- docs/devel/zoned-storage.rst | 43 ++ docs/system/qemu-block-drivers.

[PATCH v17 5/8] config: add check to block layer

Putting zoned/non-zoned BlockDrivers on top of each other is not allowed. Signed-off-by: Sam Li Reviewed-by: Stefan Hajnoczi Reviewed-by: Hannes Reinecke Reviewed-by: Dmitry Fomichev --- block.c | 19 +++ block/file-posix.c | 12 +

[PATCH v17 6/8] qemu-iotests: test new zone operations

The new block layer APIs of zoned block devices can be tested by: $ tests/qemu-iotests/check zoned Run each zone operation on a newly created null_blk device and see whether it outputs the same zone information. Signed-off-by: Sam Li Reviewed-by: Stefan Hajnoczi --- tests/qemu-iotests/tests/zon

[PATCH v17 4/8] raw-format: add zone operations to pass through requests

raw-format driver usually sits on top of file-posix driver. It needs to pass through requests of zone commands. Signed-off-by: Sam Li Reviewed-by: Stefan Hajnoczi Reviewed-by: Damien Le Moal Reviewed-by: Hannes Reinecke Reviewed-by: Dmitry Fomichev --- block/raw-format.c | 17 +++

[PATCH v17 7/8] block: add some trace events for new block layer APIs

Signed-off-by: Sam Li Reviewed-by: Stefan Hajnoczi Reviewed-by: Dmitry Fomichev --- block/file-posix.c | 3 +++ block/trace-events | 2 ++ 2 files changed, 5 insertions(+) diff --git a/block/file-posix.c b/block/file-posix.c index 5fa80933c9..65efe5147e 100644 --- a/block/file-posix.c +++ b/bl

[PATCH v17 1/8] include: add zoned device structs

Signed-off-by: Sam Li Reviewed-by: Stefan Hajnoczi Reviewed-by: Damien Le Moal Reviewed-by: Hannes Reinecke Reviewed-by: Dmitry Fomichev --- include/block/block-common.h | 43 1 file changed, 43 insertions(+) diff --git a/include/block/block-common.h b/in

[PATCH v17 2/8] file-posix: introduce helper functions for sysfs attributes

Use get_sysfs_str_val() to get the string value of device zoned model. Then get_sysfs_zoned_model() can convert it to BlockZoneModel type of QEMU. Use get_sysfs_long_val() to get the long value of zoned device information. Signed-off-by: Sam Li Reviewed-by: Hannes Reinecke Reviewed-by: Stefan H

[PATCH v17 0/8] Add support for zoned device

Zoned Block Devices (ZBDs) devide the LBA space to block regions called zones that are larger than the LBA size. It can only allow sequential writes, which reduces write amplification in SSD, leading to higher throughput and increased capacity. More details about ZBDs can be found at: https://zone

Re: [PATCH for-8.0] aio-posix: fix race between epoll upgrade and aio_set_fd_handler()

Il mer 22 mar 2023, 15:55 Stefan Hajnoczi ha scritto: > +/* The list must not change while we add fds to epoll */ > +if (!qemu_lockcnt_dec_if_lock(&ctx->list_lock)) { > +return false; > +} > + > +ok = fdmon_epoll_try_enable(ctx); > + > +qemu_lockcnt_unlock(&ctx->list_l

RE: [PATCH 1/2] ui/gtk: use widget size for cursor motion event

Hi Erico, > > > >> > >> The gd_motion_event size has some calculations for the cursor position, > >> which also take into account things like different size of the > >> framebuffer compared to the window size. > >> The use of window size makes things more difficult though, as at least > >> in the

Re: [PATCH v15 1/4] vhost: expose function vhost_dev_has_iommu()

On Tue, Mar 21, 2023 at 10:23 PM Cindy Lu wrote: > > To support vIOMMU in vdpa, need to exposed the function > vhost_dev_has_iommu, vdpa will use this function to check > if vIOMMU enable. > > Signed-off-by: Cindy Lu It looks like you missed my acks for patches 1 - 3. Thanks > --- > hw/virtio

Re: [PATCH v15 4/4] vhost-vdpa: Add support for vIOMMU.

On Tue, Mar 21, 2023 at 10:24 PM Cindy Lu wrote: > > 1. The vIOMMU support will make vDPA can work in IOMMU mode. This > will fix security issues while using the no-IOMMU mode. > To support this feature we need to add new functions for IOMMU MR adds and > deletes. > > Also since the SVQ does not s

Re: [PATCH for-8.1 v4 12/25] target/riscv/cpu.c: redesign register_cpu_props()

Hi Daniel, I want to share my opinions about the cpu->cfg and misa. Two suggestions: 1) The cpu->cfg should be set only once in cpu initialization phrase(cpu_init_fn or cpu_realize_fn), and never changes any more in other times(for example write_misa). 2) Set the misa only when cpu->cfg is

[PATCH 0/3] Add support for TPM devices over I2C bus

This drop adds support for the TPM devices attached to the I2C bus. It only supports the TPM2 protocol. You need to run it with the external TPM emulator like swtpm. I have tested it with swtpm. I have refered to the work done by zhdan...@meta.com but at the core level out implementation is differ

[PATCH 1/3] docs: Add support for TPM devices over I2C bus

This is a documentation change for I2C TPM device support. Qemu already supports devices attached to ISA and sysbus. This drop adds support for the I2C bus attached TPM devices. Signed-off-by: Ninad Palsule --- V2: Incorporated Stephen's review comments - Added example in the document. --- do

[PATCH 2/3] TPM TIS: Add support for TPM devices over I2C bus

Qemu already supports devices attached to ISA and sysbus. This drop adds support for the I2C bus attached TPM devices. This commit includes changes for the common code. - Added support for the new checksum registers which are required for the I2C support. The checksum calculation is handled in t

[PATCH 3/3] New I2C: Add support for TPM devices over I2C bus

Qemu already supports devices attached to ISA and sysbus. This drop adds support for the I2C bus attached TPM devices. I2C model only supports TPM2 protocol. This commit includes changes for the common code. - Added I2C emulation model. Logic was added in the model to temporarily cache the data

Re: [PATCH v2] tests/avocado: re-factor igb test to avoid timeouts

On 2023/03/22 23:55, Alex Bennée wrote: The core of the test was utilising "ethtool -t eth1 offline" to run through a test sequence. For reasons unknown the test hangs under some configurations of the build on centos8-stream. Fundamentally running the old fedora-31 cloud-init is just too much for

[PATCH v4 0/2] target/riscv: reduce MSTATUS_SUM overhead

v3 -> v4: * seperate priv from mmu_idx * use index 2 for S+SUM mmu_idx * no tlb_flush for MPRV / MPP changes Fei Wu (2): target/riscv: separate priv from mmu_idx target/riscv: reduce overhead of MSTATUS_SUM change target/riscv/cpu.h| 2 -- target/riscv/cpu_helper

[PATCH v4 2/2] target/riscv: reduce overhead of MSTATUS_SUM change

Kernel needs to access user mode memory e.g. during syscalls, the window is usually opened up for a very limited time through MSTATUS.SUM, the overhead is too much if tlb_flush() gets called for every SUM change. This patch creates a separate MMU index for S+SUM, so that it's not necessary to flus

[PATCH v4 1/2] target/riscv: separate priv from mmu_idx

Currently it's assumed the 2 low bits of mmu_idx map to privilege mode, this assumption won't last as we are about to add more mmu_idx. Signed-off-by: Fei Wu --- target/riscv/cpu.h | 1 - target/riscv/cpu_helper.c | 2 +- target/riscv/insn_trans/t

[PATCH 3/6] target/ppc: Fix instruction loading endianness in alignment interrupt

powerpc ifetch endianness depends on MSR[LE] so it has to byteswap after cpu_ldl_code(). This corrects DSISR bits in alignment interrupts when running in little endian mode. Signed-off-by: Nicholas Piggin --- target/ppc/excp_helper.c | 27 ++- 1 file changed, 26 insertion

[PATCH 4/6] target/ppc: Alignment faults do not set DSISR in ISA v3.0 onward

This optional behavior was removed from the ISA in v3.0, see Summary of Changes preface: Data Storage Interrupt Status Register for Alignment Interrupt: Simplifies the Alignment interrupt by remov- ing the Data Storage Interrupt Status Register (DSISR) from the set of registers modified by

[PATCH 5/6] target/ppc: Add SRR1 prefix indication to interrupt handlers

ISA v3.1 introduced prefix instructions. Among the changes, various synchronous interrupts report whether they were caused by a prefix instruction in (H)SRR1. Signed-off-by: Nicholas Piggin --- target/ppc/excp_helper.c | 37 + 1 file changed, 37 insertions(+)

[PATCH 1/6] target/ppc: Fix width of some 32-bit SPRs

Some 32-bit SPRs are incorrectly implemented as 64-bits on 64-bit targets. This changes VRSAVE, DSISR, HDSISR, DAWRX0, PIDR, LPIDR, DEXCR, HDEXCR, CTRL, TSCR, MMCRH, and PMC[1-6] from to be 32-bit registers. This only goes by the 32/64 classification in the architecture, it does not try to implem

[PATCH 2/6] target/ppc: Better CTRL SPR implementation

The CTRL register is able to write bit zero, and that is reflected in a bit field in the register that reflects the state of all threads in the core. TCG does not implement SMT, so this just requires mirroring that bit into the first bit of the thread state field. Signed-off-by: Nicholas Piggin

[PATCH 6/6] target/ppc: Implement HEIR SPR

The hypervisor emulation assistance interrupt modifies HEIR to contain the value of the instruction which caused the exception. Signed-off-by: Nicholas Piggin --- target/ppc/cpu.h | 1 + target/ppc/cpu_init.c| 23 +++ target/ppc/excp_helper.c | 12 +++- 3

Re: [PATCH for-8.1 v4 11/25] target/riscv/cpu.c: set cpu config in set_misa()

On 2023/3/23 10:14, LIU Zhiwei wrote: On 2023/3/23 6:19, Daniel Henrique Barboza wrote: set_misa() is setting all 'misa' related env states and nothing else. But other functions, namely riscv_cpu_validate_set_extensions(), uses the config object to do its job. This creates a need to set the

Re: [PATCH for-8.1 v4 11/25] target/riscv/cpu.c: set cpu config in set_misa()

On 2023/3/23 6:19, Daniel Henrique Barboza wrote: set_misa() is setting all 'misa' related env states and nothing else. But other functions, namely riscv_cpu_validate_set_extensions(), uses the config object to do its job. This creates a need to set the single letter extensions in the cfg obje

Re: [PATCH for-8.1 v4 10/25] target/riscv/cpu.c: avoid set_misa() in validate_set_extensions()

On 2023/3/23 6:19, Daniel Henrique Barboza wrote: set_misa() will be tuned up to do more than it's already doing and it will be redundant to what riscv_cpu_validate_set_extensions() does. Note that we don't ever change env->misa_mlx typo. in this function, so set_misa() can be replaced by ju

Re: [PATCH for-8.1 v4 09/25] target/riscv/cpu.c: remove cfg setup from riscv_cpu_init()

On 2023/3/23 6:19, Daniel Henrique Barboza wrote: We have 4 config settings being done in riscv_cpu_init(): ext_ifencei, ext_icsr, mmu and pmp. This is also the constructor of the "riscv-cpu" device, which happens to be the parent device of every RISC-V cpu. The result is that these 4 configs

Re: [PATCH for-8.1 v4 08/25] target/riscv/cpu.c: validate extensions before riscv_timer_init()

On 2023/3/23 6:19, Daniel Henrique Barboza wrote: There is no need to init timers if we're not even sure that our extensions are valid. Execute riscv_cpu_validate_set_extensions() before riscv_timer_init(). Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 10 -- 1 fi

Re: [PATCH for-8.1 v4 07/25] target/riscv: move pmp and epmp validations to validate_set_extensions()

On 2023/3/23 6:19, Daniel Henrique Barboza wrote: In the near future, write_misa() will use a variation of what we have now as riscv_cpu_validate_set_extensions(). The pmp and epmp validation will be required in write_misa() I don't know why pmp and epmp should be checked in write_misa(). As

Re: [PATCH for-8.1 v4 06/25] target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl()

On 2023/3/23 6:19, Daniel Henrique Barboza wrote: Let's remove more code that is open coded in riscv_cpu_realize() and put it into a helper. Let's also add an error message instead of just asserting out if env->misa_mxl_max != env->misa_mlx. Signed-off-by: Daniel Henrique Barboza --- target

Re: [PATCH v10 0/9] KVM: mm: fd-based approach for supporting KVM

On Tue, Feb 21, 2023 at 08:11:35PM +0800, Chao Peng wrote: > > Hi Sean, > > > > We've rebased the SEV+SNP support onto your updated UPM base support > > tree and things seem to be working okay, but we needed some fixups on > > top of the base support get things working, along with 1 workaround > >

Re: [PATCH v3] target/riscv: reduce overhead of MSTATUS_SUM change

On 3/23/2023 8:38 AM, Wu, Fei wrote: > On 3/22/2023 9:19 PM, Richard Henderson wrote: >> On 3/22/23 05:12, Fei Wu wrote: >>> Kernel needs to access user mode memory e.g. during syscalls, the window >>> is usually opened up for a very limited time through MSTATUS.SUM, the >>> overhead is too much if

Re: [PATCH 3/3] Add support for TPM devices over I2C bus

On 3/22/23 8:04 AM, Stefan Berger wrote: On 3/22/23 07:50, Stefan Berger wrote: On 3/22/23 07:28, Ninad Palsule wrote: On 3/21/23 8:30 PM, Stefan Berger wrote: I think there should be tpm_tis_set_data_buffer function that you can call rather than transferring the data byte-by-byte

Re: [PATCH v10 9/9] KVM: Enable and expose KVM_MEM_PRIVATE

On Wed, Mar 08, 2023 at 03:40:26PM +0800, Chao Peng wrote: > On Wed, Mar 08, 2023 at 12:13:24AM +, Ackerley Tng wrote: > > Chao Peng writes: > > > > > On Sat, Jan 14, 2023 at 12:01:01AM +, Sean Christopherson wrote: > > > > On Fri, Dec 02, 2022, Chao Peng wrote: > > > ... > > > > Strong

Re: [PATCH v3] target/riscv: reduce overhead of MSTATUS_SUM change

On 3/22/2023 9:19 PM, Richard Henderson wrote: > On 3/22/23 05:12, Fei Wu wrote: >> Kernel needs to access user mode memory e.g. during syscalls, the window >> is usually opened up for a very limited time through MSTATUS.SUM, the >> overhead is too much if tlb_flush() gets called for every SUM chan

[PATCH v6 3/3] qga: test: Add tests for `merged` flag

This commit adds a test to ensure `merged` functions as expected. We also add a negative test to ensure we haven't regressed previous functionality. Reviewed-by: Daniel P. Berrangé Signed-off-by: Daniel Xu --- tests/unit/test-qga.c | 158 +- 1 file change

[PATCH v6 2/3] qga: Add `merged` variant to GuestExecCaptureOutputMode

Currently, any captured output (via `capture-output`) is segregated into separate GuestExecStatus fields (`out-data` and `err-data`). This means that downstream consumers have no way to reassemble the captured data back into the original stream. This is relevant for chatty and semi-interactive (ie

[PATCH v6 1/3] qga: Refactor guest-exec capture-output to take enum

Previously capture-output was an optional boolean flag that either captured all output or captured none. While this is OK in most cases, it lacks flexibility for more advanced capture cases, such as wanting to only capture stdout. This commits refactors guest-exec qapi to take an enum for capture

[PATCH v6 0/3] qga: Support merging output streams in guest-exec

Currently, the captured output (via `capture-output`) is segregated into separate GuestExecStatus fields (`out-data` and `err-data`). This means that downstream consumers have no way to reassemble the captured data back into the original stream. This is relevant for chatty and semi-interactive (ie

Re: [PATCH v5 2/3] qga: Add `merged` variant to GuestExecCaptureOutputMode

Hi Daniel, Sorry about the delay -- was out of town the past week. On Fri, Mar 10, 2023, at 2:24 AM, Daniel P. Berrangé wrote: > On Thu, Mar 09, 2023 at 03:40:57PM -0700, Daniel Xu wrote: >> Currently, any captured output (via `capture-output`) is segregated into >> separate GuestExecStatus field

[PATCH for-8.1 v4 15/25] target/riscv/cpu.c: split RVG code from validate_set_extensions()

We can set all RVG related extensions during realize time, before validate_set_extensions() itself. Put it in a separated function so the validate function already uses the updated state. Note that we're setting both cfg->ext_N and env->misa_ext bits, instead of just setting cfg->ext_N. The intent

[PATCH for-8.1 v4 25/25] target/riscv: handle RVG updates in write_misa()

RVG is enabled when IMAFD_Zicsr_Zifencei is also enabled. Change write_misa() to enable IMAFD if G is being written in the CSR. Likewise, RVG should be disabled if any of IMAFD got disabled during the process. Clear RVG in this case. Signed-off-by: Daniel Henrique Barboza --- target/riscv/csr.c

[PATCH for-8.1 v4 13/25] target/riscv: put env->misa_ext <-> cpu->cfg code into helpers

The extremely tedious code that sets cpu->cfg based on misa_ext, and vice-versa, is scattered around riscv_cpu_validate_set_extensions() and set_misa(). Introduce helpers to do this work, cleaning up the logic of both functions a bit. While we're at it, add a note in cpu.h informing that any futur

[PATCH for-8.1 v4 07/25] target/riscv: move pmp and epmp validations to validate_set_extensions()

In the near future, write_misa() will use a variation of what we have now as riscv_cpu_validate_set_extensions(). The pmp and epmp validation will be required in write_misa() and it's already required here in riscv_cpu_realize(), so move it to riscv_cpu_validate_set_extensions(). Signed-off-by: Da

Re: [PATCH RESEND v2] hw/i2c: Enable an id for the pca954x devices

On 22/3/23 22:19, Corey Minyard wrote: On Wed, Mar 22, 2023 at 10:21:36AM -0700, Patrick Venture wrote: This allows the devices to be more readily found and specified. Without setting the name field, they can only be found by device type name, which doesn't let you specify the second of the same

[PATCH for-8.1 v4 19/25] target/riscv: write env->misa_ext* in register_generic_cpu_props()

In the process of creating the user-facing flags in register_generic_cpu_props() we're also setting default values for the cpu->cfg flags that represents MISA bits. Leaving it as is will cause a discrepancy between users of this function (at this moment the non-named CPUs) and named CPUs. Named CP

[PATCH for-8.1 v4 12/25] target/riscv/cpu.c: redesign register_cpu_props()

Now that the function is a no-op if 'env.misa_ext != 0', and no one that are setting misa_ext != 0 is calling it because set_misa() is setting the cpu cfg accordingly, remove the now deprecated code and rename the function to register_generic_cpu_props(). This function is now doing exactly what th

RE: [PATCH] vfio/pci: add support for VF token

> On Mon, 20 Mar 2023 11:03:40 +0100 > Cédric Le Goater wrote: > > > On 3/20/23 08:35, Minwoo Im wrote: > > > VF token was introduced [1] to kernel vfio-pci along with SR-IOV > > > support [2]. This patch adds support VF token among PF and VF(s). To > > > passthu PCIe VF to a VM, kernel >= v5.7

[PATCH for-8.1 v4 05/25] target/riscv/cpu.c: add priv_spec validate/disable_exts helpers

We're doing env->priv_spec validation and assignment at the start of riscv_cpu_realize(), which is fine, but then we're doing a force disable on extensions that aren't compatible with the priv version. This second step is being done too early. The disabled extensions might be re-enabled again in r

Re: [PULL v2 for 8.0 00/35] various fixes (testing, plugins, gitdm)

Peter Maydell writes: > On Wed, 22 Mar 2023 at 16:33, Alex Bennée wrote: >> >> The following changes since commit c283ff89d11ff123efc9af49128ef58511f73012: >> >> Update version for v8.0.0-rc1 release (2023-03-21 17:15:43 +) >> >> are available in the Git repository at: >> >> https://gi

[Bug 1703506] Re: SMT not supported by QEMU on AMD Ryzen CPU

This affected me. Took me several days. The solution posted by asd fghjkl (ryzen27) worked for me as well: sudo nano /etc/modprobe.d/kvm.conf options kvm ignore_msrs=1 and then rebooted I'm very glad i found this thread. Don't know where to report this or if it's even a bug, But hope it gets f

[PATCH for-8.1 v4 22/25] target/riscv: use misa_ext val in riscv_cpu_validate_extensions()

Similar to what we did with riscv_cpu_validate_misa_ext(), let's read all MISA bits from a misa_ext val instead of reading from the cpu->cfg object. This will allow write_misa() to use riscv_cpu_validate_extensions(). Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 25 ++

[PATCH for-8.1 v4 14/25] target/riscv: add RVG

The 'G' bit in misa_ext is a virtual extension that enables a set of extensions (i, m, a, f, d, icsr and ifencei). We're already have code to handle it but no bit definition. Add it. Add RVG to set_misa() in rv64_thead_c906_cpu_init() and remove the manual cpu->cfg.ext_g assignment while we're at

Re: [PATCH RESEND v2] hw/i2c: Enable an id for the pca954x devices

On Wed, Mar 22, 2023 at 10:21:36AM -0700, Patrick Venture wrote: > This allows the devices to be more readily found and specified. > Without setting the name field, they can only be found by device type > name, which doesn't let you specify the second of the same device type > behind a bus. > > Te

[PATCH] hw/arm/virt: support both pl011 and 16550 uart

From: Shu-Chun Weng Select uart for virt machine from pl011 and ns16550a with -M virt,uart={pl011|ns16550a}. Signed-off-by: Shu-Chun Weng Signed-off-by: Patrick Venture --- hw/arm/virt.c | 85 ++- include/hw/arm/virt.h | 6 +++ 2 files changed,

Re: [PULL v2 for 8.0 00/35] various fixes (testing, plugins, gitdm)

On Wed, 22 Mar 2023 at 21:54, Alex Bennée wrote: > > > Peter Maydell writes: > > > On Wed, 22 Mar 2023 at 16:33, Alex Bennée wrote: > >> > >> The following changes since commit > >> c283ff89d11ff123efc9af49128ef58511f73012: > >> > >> Update version for v8.0.0-rc1 release (2023-03-21 17:15:43

Re: [PATCH v2 6/7] target/arm: Implement v8.3 FPAC and FPACCOMBINE

On 3/22/23 13:33, Aaron Lindsay wrote: On Feb 22 11:37, Richard Henderson wrote: On 2/22/23 09:35, Aaron Lindsay wrote: @@ -406,6 +421,16 @@ static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifier, uint64_t xor_mask = MAKE_64BIT_MASK(bot_bit, top_bit - bot_bit +

[PATCH for-8.1 v4 09/25] target/riscv/cpu.c: remove cfg setup from riscv_cpu_init()

We have 4 config settings being done in riscv_cpu_init(): ext_ifencei, ext_icsr, mmu and pmp. This is also the constructor of the "riscv-cpu" device, which happens to be the parent device of every RISC-V cpu. The result is that these 4 configs are being set every time, and every other CPU should a

Re: [PATCH] hw/acpi/cxl: Drop device-memory support from CFMWS entries

Jonathan Cameron wrote: > On Mon, 20 Mar 2023 23:08:31 -0700 > Dan Williams wrote: > > > While it was a reasonable idea to specify no window restricitions at the > > outset of the CXL emulation support, it turns out that in practice a > > platform will never follow the QEMU example of specifying

[PATCH] Hexagon (translate.c): avoid redundant PC updates on COF

When there is a conditional change of flow or an endloop instruction, we preload HEX_REG_PC with ctx->next_PC at gen_start_packet(). Nonetheless, we still generate TCG code to do this update again at gen_goto_tb() when the condition for the COF is not met, thus producing redundant instructions. Thi

[PATCH for-8.1 v4 04/25] target/riscv: add PRIV_VERSION_LATEST

All these generic CPUs are using the latest priv available, at this moment PRIV_VERSION_1_12_0: - riscv_any_cpu_init() - rv32_base_cpu_init() - rv64_base_cpu_init() - rv128_base_cpu_init() Create a new PRIV_VERSION_LATEST enum and use it in those cases. I'll make it easier to update everything at

[PATCH for-8.1 v4 11/25] target/riscv/cpu.c: set cpu config in set_misa()

set_misa() is setting all 'misa' related env states and nothing else. But other functions, namely riscv_cpu_validate_set_extensions(), uses the config object to do its job. This creates a need to set the single letter extensions in the cfg object to keep both in sync. At this moment this is being

[PATCH for-8.1 v4 08/25] target/riscv/cpu.c: validate extensions before riscv_timer_init()

There is no need to init timers if we're not even sure that our extensions are valid. Execute riscv_cpu_validate_set_extensions() before riscv_timer_init(). Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 10 -- 1 file changed, 4 insertions(+), 6 deletions(-) diff --git

[PATCH for-8.1 v4 06/25] target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl()

Let's remove more code that is open coded in riscv_cpu_realize() and put it into a helper. Let's also add an error message instead of just asserting out if env->misa_mxl_max != env->misa_mlx. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 51 ++---

[PATCH for-8.1 v4 18/25] target/riscv: error out on priv failure for RVH

riscv_cpu_disable_priv_spec_isa_exts(), at the end of riscv_cpu_validate_set_extensions(), will disable cpu->cfg.ext_h and cpu->cfg.ext_v if priv_ver check fails. This check can be done in riscv_cpu_validate_misa_ext(). The difference here is that we're not silently disable it: we'll error out. Si

[PATCH for-8.1 v4 20/25] target/riscv: make validate_misa_ext() use a misa_ext val

We have all MISA specific validations in riscv_cpu_validate_misa_ext(), and we have a guarantee that env->misa_ext will always be in sync with cpu->cfg at this point during realize time, so let's convert it to use a 'misa_ext' parameter instead of reading cpu->cfg. This will prepare the function t

[PATCH for-8.1 v4 21/25] target/riscv: split riscv_cpu_validate_set_extensions()

We're now ready to split riscv_cpu_validate_set_extensions() in two. None of these steps are going to touch env->misa_ext*. riscv_cpu_validate_extensions() will take care of all validations based on cpu->cfg values. cpu->cfg changes that are required for the validation are being tolerated here. Th

[PATCH for-8.1 v4 24/25] target/riscv: update cpu->cfg misa bits in commit_cpu_cfg()

write_misa() is able to use the same validation workflow riscv_cpu_realize() uses. But it's still not capable of updating cpu->cfg misa props yet. We have no way of blocking future (and current) code from checking env->misa_ext (via riscv_has_ext()) or reading cpu->cfg directly, so our best altern

[PATCH for-8.1 v4 23/25] target/riscv: rework write_misa()

write_misa() must use as much common logic as possible. We want to open code just the bits that are exclusive to the CSR write operation and TCG internals. Rewrite write_misa() to work as follows: - mask the write using misa_ext_mask to avoid enabling unsupported extensions; - suppress RVC if

[PATCH for-8.1 v4 01/25] target/riscv/cpu.c: add riscv_cpu_validate_v()

The RVV verification will error out if fails and it's being done at the end of riscv_cpu_validate_set_extensions(). Let's put it in its own function and do it earlier. We'll move it out of riscv_cpu_validate_set_extensions() in the near future, but for now this is enough to clean the code a bit.

[PATCH for-8.1 v4 16/25] target/riscv/cpu.c: add riscv_cpu_validate_misa_ext()

Even after taking RVG off from riscv_cpu_validate_set_extensions(), the function is still doing too much. It is validating misa bits, then validating named extensions, and if the validation succeeds it's doing more changes in both cpu->cfg and MISA bits. It works for the support we have today, sin

[PATCH for-8.1 v4 00/25] target/riscv: rework CPU extensions validation

Hi, In this version I simplified the logic used in write_misa() after reviews from Weiwei Li. The patch that handled RVV activation was removed, making RVV a regular MISA bit to activate/deactivate. We're also checking whether one of the IMAFD extensions got disabled during write_misa() and, if t

[PATCH for-8.1 v4 17/25] target/riscv: move riscv_cpu_validate_v() to validate_misa_ext()

riscv_cpu_validate_v() consists of checking RVV related attributes, such as vlen and elen, and setting env->vext_spec. This can be done during riscv_cpu_validate_misa_ext() time, allowing us to fail earlier if RVV constrains are not met. Signed-off-by: Daniel Henrique Barboza --- target/riscv/c

Re: [PATCH v2 7/7] target/arm: Add CPU properties for most v8.3 PAC features

On 3/22/23 13:36, Aaron Lindsay wrote: I have not played around with this further. Do you feel this is important to look into prior to merging this patchset (since QARMA3 isn't the default)? No, a mere curiosity. r~

[PATCH for-8.1 v4 02/25] target/riscv/cpu.c: remove set_vext_version()

This setter is doing nothing else but setting env->vext_ver. Assign the value directly. Signed-off-by: Daniel Henrique Barboza Reviewed-by: LIU Zhiwei --- target/riscv/cpu.c | 7 +-- 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1

[PATCH for-8.1 v4 10/25] target/riscv/cpu.c: avoid set_misa() in validate_set_extensions()

set_misa() will be tuned up to do more than it's already doing and it will be redundant to what riscv_cpu_validate_set_extensions() does. Note that we don't ever change env->misa_mlx in this function, so set_misa() can be replaced by just assigning env->misa_ext and env->misa_ext_mask to 'ext'. S

[PATCH for-8.1 v4 03/25] target/riscv/cpu.c: remove set_priv_version()

The setter is doing nothing special. Just set env->priv_ver directly. Signed-off-by: Daniel Henrique Barboza Reviewed-by: LIU Zhiwei --- target/riscv/cpu.c | 30 +- 1 file changed, 13 insertions(+), 17 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.

Re: [PATCH 4/4] hw/pci: Ensure pci_add_capability() is called before device is realized

On 22/3/23 09:52, Philippe Mathieu-Daudé wrote: On 22/3/23 03:18, Michael S. Tsirkin wrote: On Tue, Mar 14, 2023 at 12:14:35PM +0100, Philippe Mathieu-Daudé wrote: PCI capabilities can't appear magically at runtime. Guests aren't expecting that. Assert all capabilities are added _before_ a devi

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