On 29/03/2023 00.21, Nina Schoetterl-Glausch wrote:
On Tue, 2023-03-28 at 15:01 +0200, Thomas Huth wrote:
On 24/03/2023 19.41, Nina Schoetterl-Glausch wrote:
Hi,
We're seeing failures running s390x migration kvm-unit-tests tests with TCG.
Some initial findings:
What seems to be happening is th
Hmm I don't think we can reasonably make such a change for 8.0.
Seems too risky.
Also, I feel we want to have an internal (with "x-" prefix") flag to
revert to old behaviour, in case of breakage on some guests. and maybe
we want to keep old revision for old machine types.
On Tue, Mar 28, 2023 at
On Tue, Mar 28, 2023 at 11:59:26AM -0400, Eric DeVolder wrote:
> Currently i386 QEMU generates MADT revision 3, and reports
> MADT revision 1. ACPI 6.3 introduces MADT revision 5.
>
> For MADT revision 4, that introduces ARM GIC structures, which do
> not apply to i386.
>
> For MADT revision 5, t
On Mon, Mar 27, 2023 at 10:45:48PM +0800, Sam Li wrote:
> This patch adds zoned storage emulation to the virtio-blk driver. It
> implements the virtio-blk ZBD support standardization that is
> recently accepted by virtio-spec. The link to related commit is at
>
> https://github.com/oasis-tcs/virti
i440fx machine versions 2.3 and newer supports dynamic ram
resizing. See commit a1666142db6233 ("acpi-build: make ROMs RAM blocks
resizeable") .
Currently supported all q35 machine types (versions 2.4 and newer) supports
resizable RAM/ROM blocks.Therefore the warning generated when the ACPI table
From: Ani Sinha
Updating mailmap to indicate a...@anisinha.ca and anisi...@redhat.com are one
and the same person. Also updating my email in MAINTAINERS for all my acpi work
(reviewing patches and biosbits) to my work email. Also doing the same for
bios bits test framework documentation.
Signed-
Add a base save_pc For PC-relative translation(CF_PCREL).
Diable the directly sync pc from tb by riscv_cpu_synchronize_from_tb.
Sync pc before it's used or updated from tb related pc:
real_pc = (old)env->pc + target_pc(from tb) - ctx->save_pc
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wa
actual_address = (requested_address & ~mpmmask) | mpmbase.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: LIU Zhiwei
---
target/riscv/vector_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/vecto
在 2023/3/29 上午4:17, Richard Henderson 写道:
On 3/27/23 20:05, Song Gao wrote:
+#define DO_ODD_EVEN_S(NAME, BIT, T, E1, E2, DO_OP) \
+void HELPER(NAME)(CPULoongArchState *env, \
+ uint32_t vd, uint32_t vj, uint32_t vk) \
+{
We should sync cpu_pc before storing it into badaddr when mis-aligned
exception is triggered.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/insn_trans/trans_rvi.c.inc | 1 +
target/riscv/translate.c| 1 +
2 files changed, 2 insertions(+)
diff --git a/ta
write_mstatus() can only change current xl when in debug mode.
And we need update cur_pmmask/base in this case.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/csr.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/target/riscv/csr.c b/target/ri
This patchset tries to fix some problem in current implementation for pointer
mask, and add support for pointer mask of instruction fetch.
The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-pm-fix-v2
v2:
* drop some error patchs
* Add patch 2 and 3 to fix the new problems
Transform the fetch address in cpu_get_tb_cpu_state() when pointer
mask for instruction is enabled.
Enable PC-relative translation when J is enabled.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/cpu.c| 4
target/riscv/cpu.h| 1 +
target/riscv/cpu
> On 09.03.23 07:14, Yangming wrote:
> >> On 08.03.23 01:42, Michael S. Tsirkin wrote:
> >>> On Wed, Mar 01, 2023 at 06:38:13AM +, Yangming wrote:
> Optimize the virtio-balloon feature on the ARM platform by adding a
> variable to keep track of the current hot-plugged pc-dimm size,
>
在 2023/3/29 上午3:42, Richard Henderson 写道:
On 3/27/23 20:05, Song Gao wrote:
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -52,6 +52,7 @@ static const char * const excp_names[] = {
[EXCCODE_FPE] = "Floating Point Exception",
[EXCCODE_DBP] = "Debug breakpoint",
[
在 2023/3/29 上午3:56, Richard Henderson 写道:
@@ -33,7 +33,39 @@ const VMStateDescription vmstate_loongarch_cpu = {
VMSTATE_UINTTL_ARRAY(env.gpr, LoongArchCPU, 32),
VMSTATE_UINTTL(env.pc, LoongArchCPU),
- VMSTATE_UINT64_ARRAY(env.fpr, LoongArchCPU, 32),
+ VMSTATE_
Hello,
On behalf of the QEMU Team, I'd like to announce the availability of the
third release candidate for the QEMU 8.0 release. This release is meant
for testing purposes and should not be used in a production environment.
http://download.qemu.org/qemu-8.0.0-rc2.tar.xz
http://download.qemu.
Change the semantics to be the last byte of the guest va, rather
than the following byte. This avoids some overflow conditions.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/exec/cpu-all.h | 11 ++-
linux-user/arm/target_cpu.h | 2 +-
bsd-user/m
Pass the address of the last byte to be changed, rather than
the first address past the last byte. This avoids overflow
when the last page of the address space is involved.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/exec/exec-all.h | 2 +-
accel/tcg/tb-
From: Philippe Mathieu-Daudé
cpu_watchpoint_insert() calls error_report() which is declared
in "qemu/error-report.h". When moving this code in commit 2609ec2868
("softmmu: Extract watchpoint API from physmem.c") we neglected to
include this header. This works so far because it is indirectly
inclu
Pass the address of the last byte to be changed, rather than
the first address past the last byte. This avoids overflow
when the last page of the address space is involved.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1528
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Hen
User setting of -R reserved_va can lead to an assertion
failure in page_set_flags. Sanity check the value of
reserved_va and print an error message instead. Do not
allocate a commpage at all for m-profile cpus.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
linux-use
Pass the address of the last byte to be changed, rather than
the first address past the last byte. This avoids overflow
when the last page of the address space is involved.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/exec/cpu-all.h | 2 +-
accel/tcg/user-e
From: Philippe Mathieu-Daudé
CPU watchpoints can be use by non-TCG accelerators.
KVM uses them:
$ git grep CPUWatchpoint|fgrep kvm
target/arm/kvm64.c:1558:CPUWatchpoint *wp = find_hw_watchpoint(cs,
debug_exit->far);
target/i386/kvm/kvm.c:5216:static CPUWatchpoint hw_watchpoint;
Pass the address of the last byte of the image, rather than
the first address past the last byte. This avoids overflow
when the last page of the address space is involved.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
linux-user/user-internals.h | 12 ++--
li
Pass the address of the last byte to be changed, rather than
the first address past the last byte. This avoids overflow
when the last page of the address space is involved.
Fixes a bug in the loop comparision where "<= end" would lock
one more page than required.
Reviewed-by: Philippe Mathieu-Da
From: Emilio Cota
qemu-user can hang in a multi-threaded fork. One common
reason is that when creating a TB, between fork and exec
we manipulate a GTree whose memory allocator (GSlice) is
not fork-safe.
Although POSIX does not mandate it, the system's allocator
(e.g. tcmalloc, libc malloc) is pr
Pass the address of the last byte to be changed, rather than
the first address past the last byte. This avoids overflow
when the last page of the address space is involved.
Properly truncate tb_last to the end of the page; the comment about
tb_end being past the end of the page being ok is not co
From: Philippe Mathieu-Daudé
Both cpu_check_watchpoint() and cpu_watchpoint_address_matches()
are specific to TCG system emulation. Declare them in "tcg-cpu-ops.h"
to be sure accessing them from non-TCG code is a compilation error.
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <202303281731
The following changes since commit d37158bb2425e7ebffb167d611be01f1e9e6c86f:
Update version for v8.0.0-rc2 release (2023-03-28 20:43:21 +0100)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230328
for you to fetch changes up to
From: Emilio Cota
The only reason to add this implementation is to control the memory allocator
used. Some users (e.g. TCG) cannot work reliably in multi-threaded
environments (e.g. forking in user-mode) with GTree's allocator, GSlice.
See https://gitlab.com/qemu-project/qemu/-/issues/285 for det
Pass the address of the last byte to be changed, rather than
the first address past the last byte. This avoids overflow
when the last page of the address space is involved.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
accel/tcg/tb-maint.c | 28 --
We have been enforcing host page alignment for the non-R
fallback of MAX_RESERVED_VA, but failing to enforce for -R.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
linux-user/main.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/linux-user/main.c b/linux-use
On Tue, 2023-03-28 at 15:01 +0200, Thomas Huth wrote:
> On 24/03/2023 19.41, Nina Schoetterl-Glausch wrote:
> > Hi,
> >
> > We're seeing failures running s390x migration kvm-unit-tests tests with TCG.
> > Some initial findings:
> > What seems to be happening is that after migration a control block
aarch64_gdb_get_pauth_reg() -- although disabled since commit
5787d17a42 ("target/arm: Don't advertise aarch64-pauth.xml to
gdb") is still compiled in. It calls pauth_ptr_mask() which is
located in target/arm/tcg/pauth_helper.c, a TCG specific helper.
To avoid a linking error when TCG is not enabl
This patch changes how we detect and install meson.
This patch creates a lightweight Python virtual environment using the
user's configured $python that inherits system packages. If Meson is
installed there and meets our minimum version requirements, we will use
that Meson.
In the event that Meso
This script will be responsible for building a Python virtual
environment at configure time. As such, it exists outside of the
installable python packages and *must* be runnable with minimal
dependencies.
Signed-off-by: John Snow
---
python/scripts/mkvenv.py | 445 +++
Several debian-based tests need the python3-venv dependency as a
consequence of Debian debundling the "ensurepip" module normally
included with Python.
As this series stands right now, in most cases, Debian requires EITHER:
(A) setuptools and pip, or
(B) ensurepip
It's quite likely most develope
This patch series creates a mandatory venv during configure time and
uses it to install meson.
The eventual point of this is to ensure that the Python used to run
meson is the same Python used to run Sphinx, tests, and any build-time
scripting we have. As it stands, meson and sphinx (and their ext
From: Philippe Mathieu-Daudé
GCC9 is confused when building with CFLAG -O3:
hw/scsi/megasas.c: In function ‘megasas_scsi_realize’:
hw/scsi/megasas.c:2387:26: error: duplicated ‘if’ condition
[-Werror=duplicated-cond]
2387 | } else if (s->fw_sge >= 128 - MFI_PASS_FRAME_SIZE) {
hw/sc
On 3/27/23 20:06, Song Gao wrote:
This patch includes:
- VDIV.{B/H/W/D}[U];
- VMOD.{B/H/W/D}[U].
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 17 +
target/loongarch/helper.h | 17 +
target/loongarch/insn_trans/trans_lsx.c.inc | 1
On 3/27/23 20:06, Song Gao wrote:
+static void gen_vmadd(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
+{
+TCGv_vec t1;
+
+t1 = tcg_temp_new_vec_matching(t);
+tcg_gen_mul_vec(vece, t1, a, b);
+tcg_gen_add_vec(vece, t, t, t1);
+}
+
+static void do_vmadd(unsigned vece, uint32_t
On 3/27/23 20:06, Song Gao wrote:
This patch includes:
- VMUL.{B/H/W/D};
- VMUH.{B/H/W/D}[U];
- VMULW{EV/OD}.{H.B/W.H/D.W/Q.D}[U];
- VMULW{EV/OD}.{H.BU.B/W.HU.H/D.WU.W/Q.DU.D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 38 ++
target/loongarch/helper.h
On 3/27/23 20:06, Song Gao wrote:
+static void do_vminmax(unsigned vece, TCGv_vec t, TCGv_vec a, int64_t imm,
+ void(*gen_vminmax_vec)(unsigned,
+ TCGv_vec, TCGv_vec, TCGv_vec))
+{
+TCGv_vec t1;
+
+t1 = tcg_temp_new_vec_ma
On 3/27/23 20:06, Song Gao wrote:
This patch includes:
- VADDA.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 5 ++
target/loongarch/helper.h | 5 ++
target/loongarch/insn_trans/trans_lsx.c.inc | 53 +
target/loon
On 3/27/23 20:05, Song Gao wrote:
This patch includes:
- VABSD.{B/H/W/D}[U].
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 9 ++
target/loongarch/helper.h | 9 ++
target/loongarch/insn_trans/trans_lsx.c.inc | 95 +
target/l
On 3/27/23 20:05, Song Gao wrote:
This patch includes:
- VAVG.{B/H/W/D}[U];
- VAVGR.{B/H/W/D}[U].
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 17 ++
target/loongarch/helper.h | 18 ++
target/loongarch/insn_trans/trans_lsx.c.inc | 197
On 3/27/23 20:05, Song Gao wrote:
+static void gen_vaddwev_w_h(TCGv_i32 t, TCGv_i32 a, TCGv_i32 b)
+{
+TCGv_i32 t1, t2;
+
+t1 = tcg_temp_new_i32();
+t2 = tcg_temp_new_i32();
+tcg_gen_shli_i32(t1, a, 16);
+tcg_gen_sari_i32(t1, t1, 16);
+tcg_gen_shli_i32(t2, b, 16);
+tcg
On 3/27/23 20:05, Song Gao wrote:
+#define DO_ODD_EVEN_S(NAME, BIT, T, E1, E2, DO_OP) \
+void HELPER(NAME)(CPULoongArchState *env, \
+ uint32_t vd, uint32_t vj, uint32_t vk) \
+{
On Tue, 28 Mar 2023 18:59:26 +0100
Daniel P. Berrangé wrote:
> I'm generally not in favour of creating many different ways to set
> the same thing, especially not multiple string based names, but if
> a single vocabulary for strings is insufficient, then having support
> for numbers feels reasona
On 3/27/23 20:05, Song Gao wrote:
This patch includes:
- VSADD.{B/H/W/D}[U];
- VSSUB.{B/H/W/D}[U].
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 17 +
target/loongarch/insn_trans/trans_lsx.c.inc | 17 +
target/loongarch/insns.decode
On 3/27/23 20:05, Song Gao wrote:
This patch includes;
- VNEG.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 10 ++
target/loongarch/insn_trans/trans_lsx.c.inc | 20
target/loongarch/insns.decode | 7 +++
On 3/27/23 20:05, Song Gao wrote:
+func(mop, vd_ofs, vj_ofs, vk_ofs, 16, 16);
Oh, reading about ASXD and 256-bit vectors makes me wonder if it would be better to plan
ahead and have a function, or DisasContext member, for the length of the vector.
r~
On 3/27/23 20:05, Song Gao wrote:
+tcg_gen_gvec_addi(mop, vd_ofs, vj_ofs, -(a->imm), 16, 16);
No need for parenthesis around a->imm.
Otherwise,
Reviewed-by: Richard Henderson
r~
On 3/27/23 20:05, Song Gao wrote:
Signed-off-by: Song Gao
---
linux-user/loongarch64/signal.c | 4 ++--
target/loongarch/cpu.c | 2 +-
target/loongarch/cpu.h | 31 +-
target/loongarch/gdbstub.c | 4 ++--
target/loongarch/machine.c
On 3/27/23 20:05, Song Gao wrote:
This patch includes:
- VADD.{B/H/W/D/Q};
- VSUB.{B/H/W/D/Q}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 23
target/loongarch/helper.h | 4 +++
target/loongarch/insn_trans/trans_lsx.c.inc | 40 ++
On 3/27/23 20:05, Song Gao wrote:
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -52,6 +52,7 @@ static const char * const excp_names[] = {
[EXCCODE_FPE] = "Floating Point Exception",
[EXCCODE_DBP] = "Debug breakpoint",
[EXCCODE_BCE] = "Bound Check Exception",
+
On Tue, 28 Mar 2023 at 13:35, Kevin Wolf wrote:
>
> The following changes since commit e3debd5e7d0ce031356024878a0a18b9d109354a:
>
> Merge tag 'pull-request-2023-03-24' of https://gitlab.com/thuth/qemu into
> staging (2023-03-24 16:08:46 +)
>
> are available in the Git repository at:
>
>
On 3/27/23 20:05, Song Gao wrote:
Signed-off-by: Song Gao
---
target/loongarch/insn_trans/trans_lsx.c.inc | 5 +
target/loongarch/lsx_helper.c | 6 ++
target/loongarch/meson.build| 1 +
target/loongarch/translate.c| 1 +
4 files changed,
On 3/27/23 20:05, Song Gao wrote:
Signed-off-by: Song Gao
---
target/loongarch/cpu.c | 1 +
1 file changed, 1 insertion(+)
This patch should be sorted last, once the entire extension is present.
Reviewed-by: Richard Henderson
On 3/28/23 11:27, Peter Maydell wrote:
On Tue, 28 Mar 2023 at 18:27, Richard Henderson
wrote:
On 3/28/23 09:28, Peter Maydell wrote:
+/*
+ * gen_exception_insn() will set is_jmp to DISAS_NORETURN,
+ * but since we're conditionally branching over it, we want
On 3/28/23 11:27, Peter Maydell wrote:
On Tue, 28 Mar 2023 at 18:27, Richard Henderson
wrote:
On 3/28/23 09:28, Peter Maydell wrote:
+/*
+ * gen_exception_insn() will set is_jmp to DISAS_NORETURN,
+ * but since we're conditionally branching over it, we want
On Tue, 28 Mar 2023 at 13:44, Peter Maydell wrote:
>
> ppc64 host:
>
> 737/761 qemu:block / io-qcow2-copy-before-write
>ERROR 6.77s exit status 1
> ― ✀ ―
> stderr:
> --- /home/pm215/qemu/tests/qemu-iot
On Tue, 28 Mar 2023 at 18:27, Richard Henderson
wrote:
>
> On 3/28/23 09:28, Peter Maydell wrote:
> > +/*
> > + * gen_exception_insn() will set is_jmp to DISAS_NORETURN,
> > + * but since we're conditionally branching over it, we want
> > + * to reta
Am 28.03.23 um 16:37 schrieb Rene Engel:
Sorry I was on the wrong branch.
I forget that every time, however that is trace test performed with ac97 under
Pegasos 2 Emulation with AmigaOs4.1, startsound played and an mp3 with TuneNet.
audio_open_out 0.000 pid=8358 card=b'via-ac97' name=b'via-ac97
On 27/3/23 23:18, Richard Henderson wrote:
User setting of -R reserved_va can lead to an assertion
failure in page_set_flags. Sanity check the value of
reserved_va and print an error message instead. Do not
allocate a commpage at all for m-profile cpus.
Signed-off-by: Richard Henderson
---
On Tue, Mar 28, 2023 at 04:36:29PM +, Durrant, Paul wrote:
> > -Original Message-
> > From: Stefan Hajnoczi
> > Sent: 28 March 2023 16:51
> > To: Woodhouse, David ; Durrant, Paul
> >
> > Cc: qemu-devel@nongnu.org; qemu-bl...@nongnu.org
> > Subject: [EXTERNAL] aio_set_event_notifier(is
On Tue, Mar 28, 2023 at 07:19:58PM +0200, Henrik Carlqvist wrote:
> Thanks for your feedback!
>
> On Tue, 28 Mar 2023 15:01:55 +0100
> Daniel P. Berrangé wrote:
>
> > This is another reason why use of the '-k' switch is a bad idea. Its
> > range of permissible values / vocabulary does not match
On 3/28/23 13:59, Markus Armbruster wrote:
At this moment, arm_load_dtb() can free machine->fdt when
binfo->dtb_filename is NULL. If there's no 'dtb_filename', 'fdt' will be
retrieved by binfo->get_dtb(). If get_dtb() returns machine->fdt, as is
the case of machvirt_dtb() from hw/arm/virt.c, f
On 28/3/23 19:47, Richard Henderson wrote:
On 3/28/23 06:51, Philippe Mathieu-Daudé wrote:
Hi Richard,
On 27/3/23 23:18, Richard Henderson wrote:
Pass the address of the last byte of the image, rather than
the first address past the last byte. This avoids overflow
when the last page of the ad
According to specification:
For Sv39x4, address bits of the guest physical address 63:41 must all be zeros,
or else a
guest-page-fault exception occurs.
Likewise for Sv48x4 and Sv57x4.
For Sv48x4 address bits 63:50 must all be zeros, or else a guest-page-fault
exception occurs.
For Sv57x4 addres
On 3/28/23 06:51, Philippe Mathieu-Daudé wrote:
Hi Richard,
On 27/3/23 23:18, Richard Henderson wrote:
Pass the address of the last byte of the image, rather than
the first address past the last byte. This avoids overflow
when the last page of the address space is involved.
Signed-off-by: Ric
On 3/28/23 06:30, Philippe Mathieu-Daudé wrote:
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 673519a24a..a617466fa8 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1389,6 +1389,14 @@ int exception_target_el(CPUARMState *env);
bool arm_singlestep_active
write_misa() must use as much common logic as possible. We want to open
code just the bits that are exclusive to the CSR write operation and TCG
internals.
Our validation is done with riscv_cpu_validate_set_extensions(), but we
need a small tweak first. When enabling RVG we're doing:
env-
There is no need to init timers if we're not even sure that our
extensions are valid. Execute riscv_cpu_validate_set_extensions() before
riscv_timer_init().
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: LIU Zhiwei
---
target/riscv/cpu.c | 11 ---
1 file changed, 4 insertions(+), 7
The RVV verification will error out if fails and it's being done at the
end of riscv_cpu_validate_set_extensions(), after we've already set some
extensions that are dependent on RVV. Let's put it in its own function
and do it earlier.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: LIU Zhiwe
All these generic CPUs are using the latest priv available, at this
moment PRIV_VERSION_1_12_0:
- riscv_any_cpu_init()
- rv32_base_cpu_init()
- rv64_base_cpu_init()
- rv128_base_cpu_init()
Create a new PRIV_VERSION_LATEST enum and use it in those cases. I'll
make it easier to update everything at
The setter is doing nothing special. Just set env->priv_ver directly.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: LIU Zhiwei
---
target/riscv/cpu.c | 29 -
1 file changed, 12 insertions(+), 17 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
Let's remove more code that is open coded in riscv_cpu_realize() and put
it into a helper. Let's also add an error message instead of just
asserting out if env->misa_mxl_max != env->misa_mlx.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: LIU Zhiwei
---
target/riscv/cpu.c | 50
This setter is doing nothing else but setting env->vext_ver. Assign the
value directly.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: LIU Zhiwei
---
target/riscv/cpu.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index b
Hi,
This v5 is based on top of:
"[PATCH v2 00/19] remove MISA ext_N flags from cpu->cfg"
We went from 25 patches to 9 because we no longer need to mirror changes
from env->misa_ext to cpu->cfg.ext_N back and forth. A lot of patches
got cut because of it.
write_misa() now uses the validate funct
We have 4 config settings being done in riscv_cpu_init(): ext_ifencei,
ext_icsr, mmu and pmp. This is also the constructor of the "riscv-cpu"
device, which happens to be the parent device of every RISC-V cpu.
The result is that these 4 configs are being set every time, and every
other CPU should a
We're doing env->priv_spec validation and assignment at the start of
riscv_cpu_realize(), which is fine, but then we're doing a force disable
on extensions that aren't compatible with the priv version.
This second step is being done too early. The disabled extensions might be
re-enabled again in r
cpu_watchpoint_insert() calls error_report() which is declared
in "qemu/error-report.h". When moving this code in commit 2609ec2868
("softmmu: Extract watchpoint API from physmem.c") we neglected to
include this header. This works so far because it is indirectly
included by TCG headers -> "qemu/plu
Both cpu_check_watchpoint() and cpu_watchpoint_address_matches()
are specific to TCG system emulation. Declare them in "tcg-cpu-ops.h"
to be sure accessing them from non-TCG code is a compilation error.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/core/cpu.h | 37
Commit 2609ec2868 ("softmmu: Extract watchpoint API from physmem.c")
restricted CPU watchpoints to TCG accelerator. This is wrong, as
other accelerators such KVM do use watchpoints. Revert (partially)
this commit.
Since v1:
- Include "hw/core/tcg-cpu-ops.h" where cpu_check_watchpoint()
and cpu_w
CPU watchpoints can be use by non-TCG accelerators.
KVM uses them:
$ git grep CPUWatchpoint|fgrep kvm
target/arm/kvm64.c:1558:CPUWatchpoint *wp = find_hw_watchpoint(cs,
debug_exit->far);
target/i386/kvm/kvm.c:5216:static CPUWatchpoint hw_watchpoint;
target/ppc/kvm.c:443:static CP
On 3/28/23 09:28, Peter Maydell wrote:
+/*
+ * gen_exception_insn() will set is_jmp to DISAS_NORETURN,
+ * but since we're conditionally branching over it, we want
+ * to retain the existing value.
+ */
+old_is_jmp = s->base.
On 3/28/23 09:28, Peter Maydell wrote:
In commit 049edada we added some code to handle HSTR_EL2 traps, which
we did as an inline "conditionally branch over a
gen_exception_insn()". Unfortunately this fails to take account of
the fact that gen_exception_insn() will set s->base.is_jmp to
DISAS_NOR
Thanks for your feedback!
On Tue, 28 Mar 2023 15:01:55 +0100
Daniel P. Berrangé wrote:
> This is another reason why use of the '-k' switch is a bad idea. Its
> range of permissible values / vocabulary does not match the range of
> values / vocabulary needed for this hardware device.
>
> In htt
To be able to remove tpm_tis_base_addr from test cases that do not really
need it move the tpm_util_tis_transmit() function into tpm-tis-utils.c and
rename it to tpm_tis_transmit().
Fix a locality parameter in a test case on the way.
Signed-off-by: Stefan Berger
Reviewed-by: Ninad Palsule
---
Add read and write functions for accessing registers of I2C devices
connected to the Aspeed I2C controller.
Signed-off-by: Stefan Berger
Reviewed-by: Cédric Le Goater
Reviewed-by: Ninad Palsule
---
include/hw/i2c/aspeed_i2c.h | 7 +++
tests/qtest/qtest_aspeed.c | 117 +++
Add a test case for the TPM TIS I2C device exercising most of its
functionality, including localities.
Signed-off-by: Stefan Berger
Tested-by: Cédric Le Goater
---
tests/qtest/meson.build| 3 +
tests/qtest/tpm-tis-i2c-test.c | 637 +
2 files changed, 64
This series adds test cases exercising much of the TPM TIS I2C device model
assuming that the device is connected to the Aspeed I2C controller. Tests
are passing on little and big endian hosts.
This series of patches builds on the following series of patches
providing the TPM TIS I2C device emulat
On 3/28/23 11:05, Thomas Huth wrote:
On 28/03/2023 15.51, Stefan Berger wrote:
+
+void aspeed_i2c_writeb(uint32_t baseaddr, uint8_t slave_addr,
+ uint8_t reg, uint8_t v)
+{
+ aspeed_i2c_write_n(baseaddr, slave_addr, reg, v, sizeof(v));
+}
For helper functions like
This change adds set of boot tests on SBSA-ref machine:
1. boot firmware up to the EDK2 banner
2. boot Alpine Linux
Prebuilt flash volumes are included, built using upstream documentation.
To unify tests for AArch64/virt and AArch64/sbsa-ref we boot
the same Alpine Linux image on both.
Signed-o
On 20/3/23 17:58, Nathan Chancellor wrote:
On Wed, Mar 08, 2023 at 12:33:38AM +0100, Philippe Mathieu-Daudé wrote:
On 23/2/23 17:19, Jiaxun Yang wrote:
145e2198d749 ("hw/mips/gt64xxx_pci: Endian-swap using PCI_HOST_BRIDGE
MemoryRegionOps") converted CFGADDR/CFGDATA registers to use PCI_HOST_BRI
At this moment, arm_load_dtb() can free machine->fdt when
binfo->dtb_filename is NULL. If there's no 'dtb_filename', 'fdt' will be
retrieved by binfo->get_dtb(). If get_dtb() returns machine->fdt, as is
the case of machvirt_dtb() from hw/arm/virt.c, fdt now has a pointer to
machine->fdt. And, in th
Daniel Henrique Barboza writes:
> On 3/28/23 06:53, Markus Armbruster wrote:
>> Daniel Henrique Barboza writes:
[...]
>>> I believe we can improve the ARM boot code to not create ms->fdt at init(),
>>> leaving it unassigned, and make get_dtb() return the machine FDT on a common
>>> "void *" po
I forgot to include the updated ACPI tables. I will do that as part of v2.
In the meantime, I appreciate any feedback...
eric
On 3/28/23 10:59, Eric DeVolder wrote:
The following Linux kernel change broke CPU hotplug for MADT revision
less than 5.
commit e2869bd7af60 ("x86/acpi/boot: Do not r
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