On 3/27/23 20:06, Song Gao wrote:
+temp.D(1) = int128_getlo(Vd->D(0));
Typo here.
You should build i386 host. E.g.
make docker-test-build@fedora-i386-cross
r~
On 3/27/23 20:06, Song Gao wrote:
This patch includes:
- VSRLN.{B.H/H.W/W.D};
- VSRAN.{B.H/H.W/W.D};
- VSRLNI.{B.H/H.W/W.D/D.Q};
- VSRANI.{B.H/H.W/W.D/D.Q}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 16 +++
target/loongarch/helper.h | 16 ++
On 3/27/23 20:06, Song Gao wrote:
This patch includes:
- VSRLR[I].{B/H/W/D};
- VSRAR[I].{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 18
target/loongarch/helper.h | 18
target/loongarch/insn_trans/trans_lsx.c.inc | 18 +++
On 3/27/23 20:06, Song Gao wrote:
This patch includes:
- VSLLWIL.{H.B/W.H/D.W};
- VSLLWIL.{HU.BU/WU.HU/DU.WU};
- VEXTL.Q.D, VEXTL.QU.DU.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 9 +
target/loongarch/helper.h | 9 +
target/loongarc
On 3/27/23 20:06, Song Gao wrote:
This patch includes:
- VSLL[I].{B/H/W/D};
- VSRL[I].{B/H/W/D};
- VSRA[I].{B/H/W/D};
- VROTR[I].{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 36 +
target/loongarch/insn_trans/trans_lsx.c.inc | 36
On 3/27/23 20:06, Song Gao wrote:
+static void gen_vnori(unsigned vece, TCGv_vec t, TCGv_vec a, int64_t imm)
+{
+TCGv_vec t1;
+
+t1 = tcg_temp_new_vec_matching(t);
+tcg_gen_dupi_vec(vece, t1, imm);
+tcg_gen_nor_vec(vece, t, a, t1);
+}
tcg_constant_vec_matching.
+
+static void
On 3/27/23 20:06, Song Gao wrote:
+void HELPER(vmskltz_b)(CPULoongArchState *env, uint32_t vd, uint32_t vj)
+{
+VReg temp;
+VReg *Vd = &(env->fpr[vd].vreg);
+VReg *Vj = &(env->fpr[vj].vreg);
+
+temp.D(0) = 0;
+temp.D(1) = 0;
+temp.H(0) = do_vmskltz_b(Vj->D(0));
+temp.H
On 2023/3/31 20:12, Gerd Hoffmann wrote:
On Fri, Mar 31, 2023 at 08:54:16AM +0800, maobibo wrote:
Xuerui,
Thanks for your mail, it is a good suggestion. Now we are planing to
move LoongArch uefi bios from edk2-platform to edk2 repo, so that uefi
bios supporting LoongArch can be auto compiled
On 3/27/23 20:06, Song Gao wrote:
+static void gen_vsigncov(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
+{
+TCGv_vec t1, t2;
+
+t1 = tcg_temp_new_vec_matching(t);
+t2 = tcg_temp_new_vec_matching(t);
+
+tcg_gen_neg_vec(vece, t1, b);
+tcg_gen_dupi_vec(vece, t2, 0);
tcg_
On 3/27/23 20:06, Song Gao wrote:
This patch includes:
- VEXTH.{H.B/W.H/D.W/Q.D};
- VEXTH.{HU.BU/WU.HU/DU.WU/QU.DU}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 9 ++
target/loongarch/helper.h | 9 ++
target/loongarch/insn_trans/trans
On 3/27/23 20:06, Song Gao wrote:
+static void gen_vsat_s(unsigned vece, TCGv_vec t, TCGv_vec a, int64_t imm)
+{
+TCGv_vec t1;
+int64_t max = (1l << imm) - 1;
This needed 1ull, but better to just use
max = MAKE_64BIT_MASK(0, imm - 1);
+int64_t min = ~max;
Extra space.
+
From: Weiwei Li
CPUs often set CF_PCREL in tcg_cflags before qemu_init_vcpu(), in which
tcg_cflags will be overwrited by tcg_cpu_init_cflags().
Fixes: 4be790263ffc ("accel/tcg: Replace `TARGET_TB_PCREL` with `CF_PCREL`")
Reviewed-by: Richard Henderson
Signed-off-by: Weiwei Li
Signed-off-by: Ju
Assign pc and use store_release to assign tb.
Fixes: 2dd5b7a1b91 ("accel/tcg: Move jmp-cache `CF_PCREL` checks to caller")
Reported-by: Weiwei Li
Signed-off-by: Richard Henderson
---
accel/tcg/cpu-exec.c | 17 +
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/acce
Fix a bug just exposed concerning qemu-arm commpage, leading to an
immediate crash on any 64k page host. Fix two bugs regressing
pc-relative tb generation, found by Weiwei Li.
r~
Richard Henderson (2):
Revert "linux-user/arm: Take more care allocating commpage"
accel/tcg: Fix jump cache se
This reverts commit 4f5c67f8df7f26e559509c68c45e652709edd23f.
This exposes bugs in target_mmap et al with respect to overflow
with the final page of the guest address space. To be fixed in
the next development cycle.
Signed-off-by: Richard Henderson
---
linux-user/elfload.c | 37 ++
在 2023/3/31 下午8:12, Gerd Hoffmann 写道:
On Fri, Mar 31, 2023 at 08:54:16AM +0800, maobibo wrote:
Xuerui,
Thanks for your mail, it is a good suggestion. Now we are planing to
move LoongArch uefi bios from edk2-platform to edk2 repo, so that uefi
bios supporting LoongArch can be auto compiled and
On 3/31/23 08:06, Weiwei Li wrote:
Transform the fetch address in cpu_get_tb_cpu_state() when pointer
mask for instruction is enabled.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/cpu.h| 1 +
target/riscv/cpu_helper.c | 20 +++-
target/riscv
On 3/31/23 08:06, Weiwei Li wrote:
The existence of CF_PCREL can improve performance with the guest
kernel's address space randomization. Each guest process maps
libc.so (et al) at a different virtual address, and this allows
those translations to be shared.
Signed-off-by: Weiwei Li
Signed-off-
On 3/31/23 18:26, Richard Henderson wrote:
On 3/31/23 08:06, Weiwei Li wrote:
A corner case is triggered when tb block with first_pc = 0x8008
and first_pc = 0x80200 has the same jump cache hash, and share
the same tb entry with the same tb information except PC.
The executed sequence is
On 3/31/23 18:33, Richard Henderson wrote:
On 3/31/23 18:18, Richard Henderson wrote:
On 3/31/23 08:06, Weiwei Li wrote:
CPUs often set CF_PCREL in tcg_cflags before qemu_init_vcpu(), in which
tcg_cflags will be overwrited by tcg_cpu_init_cflags().
Signed-off-by: Weiwei Li
Signed-off-by: Junqi
On 3/31/23 18:18, Richard Henderson wrote:
On 3/31/23 08:06, Weiwei Li wrote:
CPUs often set CF_PCREL in tcg_cflags before qemu_init_vcpu(), in which
tcg_cflags will be overwrited by tcg_cpu_init_cflags().
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
accel/tcg/tcg-accel-ops.c | 2
On 3/31/23 08:06, Weiwei Li wrote:
A corner case is triggered when tb block with first_pc = 0x8008
and first_pc = 0x80200 has the same jump cache hash, and share
the same tb entry with the same tb information except PC.
The executed sequence is as follows:
tb(0x8008) -> tb(0x8008
On 3/31/23 08:06, Weiwei Li wrote:
CPUs often set CF_PCREL in tcg_cflags before qemu_init_vcpu(), in which
tcg_cflags will be overwrited by tcg_cpu_init_cflags().
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
accel/tcg/tcg-accel-ops.c | 2 +-
1 file changed, 1 insertion(+), 1 dele
On 3/31/23 08:06, Weiwei Li wrote:
Add a base save_pc For PC-relative translation(CF_PCREL).
Diable the directly sync pc from tb by riscv_cpu_synchronize_from_tb.
Sync pc before it's used or updated from tb related pc:
real_pc = (old)env->pc + target_pc(from tb) - ctx->save_pc
Signed-off-by:
On 3/31/23 08:06, Weiwei Li wrote:
Compute the target address before storing it into badaddr
when mis-aligned exception is triggered.
Use a target_pc temp to store the target address to avoid
the confusing operation that udpate target address into
cpu_pc before misalign check, then update it int
Christian Brauner writes:
On Tue, Mar 21, 2023 at 08:15:32PM +, Ackerley Tng wrote:
By default, the backing shmem file for a restrictedmem fd is created
on shmem's kernel space mount.
...
Thanks for reviewing this patch!
This looks like you can just pass in some tmpfs fd and you ju
For memfd_restricted() calls without a userspace mount, the backing
file should be the shmem mount in the kernel, and the size of backing
pages should be as defined by system-wide shmem configuration.
If a userspace mount is provided, the size of backing pages should be
as defined in the mount.
A
Hello,
This patchset builds upon the memfd_restricted() system call that was
discussed in the ‘KVM: mm: fd-based approach for supporting KVM’ patch
series, at
https://lore.kernel.org/lkml/20221202061347.1070246-1-chao.p.p...@linux.intel.com/T/
The tree can be found at:
https://github.com/googlepr
By default, the backing shmem file for a restrictedmem fd is created
on shmem's kernel space mount.
With this patch, an optional tmpfs mount can be specified via an fd,
which will be used as the mountpoint for backing the shmem file
associated with a restrictedmem fd.
This will help restrictedmem
On 3/31/23 07:18, Warner Losh wrote:
The NetBSD and OpenBSD support in bsd-user hasn't built since before the meson
conversion. It's also out of sync with many of the recent changes in the
bsd-user fork and has just been removed there. Remove it from master for the
same reasons: it generates a nu
On Fri, Mar 31, 2023 at 03:18:37PM -0300, Fabiano Rosas wrote:
> Peter Xu writes:
>
> > On Fri, Mar 31, 2023 at 05:10:16PM +0100, Daniel P. Berrangé wrote:
> >> On Fri, Mar 31, 2023 at 11:55:03AM -0400, Peter Xu wrote:
> >> > On Fri, Mar 31, 2023 at 12:30:45PM -0300, Fabiano Rosas wrote:
> >> > >
On 3/31/23 11:22, Christoph Müllner wrote:
On Mon, Mar 27, 2023 at 7:18 PM Richard Henderson
wrote:
On 3/27/23 01:00, Christoph Muellner wrote:
+uint64_t helper_fminm_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
+{
+float32 frs1 = check_nanbox_s(env, rs1);
+float32 frs2 = check_n
Nicholas Piggin writes:
> powerpc ifetch endianness depends on MSR[LE] so it has to byteswap
> after cpu_ldl_code(). This corrects DSISR bits in alignment
> interrupts when running in little endian mode.
>
> Signed-off-by: Nicholas Piggin
Reviewed-by: Fabiano Rosas
Nicholas Piggin writes:
> ISA v3.1 introduced prefix instructions. Among the changes, various
> synchronous interrupts report whether they were caused by a prefix
> instruction in (H)SRR1.
>
> Signed-off-by: Nicholas Piggin
Reviewed-by: Fabiano Rosas
Nicholas Piggin writes:
> This optional behavior was removed from the ISA in v3.0, see
> Summary of Changes preface:
>
> Data Storage Interrupt Status Register for Alignment Interrupt:
> Simplifies the Alignment interrupt by remov- ing the Data Storage
> Interrupt Status Register (DSISR) fr
Hi Daniel,
On Thu, Mar 23, 2023, at 3:26 AM, Daniel P. Berrangé wrote:
> On Wed, Mar 22, 2023 at 06:19:27PM -0600, Daniel Xu wrote:
>> Currently, any captured output (via `capture-output`) is segregated into
>> separate GuestExecStatus fields (`out-data` and `err-data`). This means
>> that downstr
Hi Jonathan,
Thanks for the response, effort and time you spent to list down the
TODOs in CXL space.
I just started understanding CXL2.0, am part of a startup developing a
CXL2.0 switch to build
compostable architecture, it's been 6 weeks.
As part of it I have built QEMU and configured with CXL
On 3/31/23 12:30 PM, Stefan Berger wrote:
Add a test case for the TPM TIS I2C device exercising most of its
functionality, including localities.
Signed-off-by: Stefan Berger
Tested-by: Cédric Le Goater
---
Tested-by: Ninad Palsule
From: Christoph Müllner
This patch introduces the RISC-V Zfa extension, which introduces
additional floating-point extensions:
* fli (load-immediate) with pre-defined immediates
* fminm/fmaxm (like fmin/fmax but with different NaN behaviour)
* fround/froundmx (round to integer)
* fcvtmod.w.d (Mod
On Mon, Mar 27, 2023 at 10:42 AM liweiwei wrote:
>
>
> On 2023/3/27 16:00, Christoph Muellner wrote:
> > From: Christoph Müllner
> >
> > This patch introduces the RISC-V Zfa extension, which introduces
> > additional floating-point extensions:
> > * fli (load-immediate) with pre-defined immediate
On Mon, Mar 27, 2023 at 7:18 PM Richard Henderson
wrote:
>
> On 3/27/23 01:00, Christoph Muellner wrote:
> > +uint64_t helper_fminm_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
> > +{
> > +float32 frs1 = check_nanbox_s(env, rs1);
> > +float32 frs2 = check_nanbox_s(env, rs2);
> > +
> >
Peter Xu writes:
> On Fri, Mar 31, 2023 at 05:10:16PM +0100, Daniel P. Berrangé wrote:
>> On Fri, Mar 31, 2023 at 11:55:03AM -0400, Peter Xu wrote:
>> > On Fri, Mar 31, 2023 at 12:30:45PM -0300, Fabiano Rosas wrote:
>> > > Peter Xu writes:
>> > >
>> > > > On Fri, Mar 31, 2023 at 11:37:50AM -030
The Fedora CI and coverity runs are using a slightly different set of
packages. Copy most of the content over from tests/docker while
keeping the commands at the end that unpack the tools.
Signed-off-by: Paolo Bonzini
---
scripts/coverity-scan/coverity-scan.docker | 250 -
1
To be able to remove tpm_tis_base_addr from test cases that do not really
need it move the tpm_util_tis_transmit() function into tpm-tis-utils.c and
rename it to tpm_tis_transmit().
Fix a locality parameter in a test case on the way.
Signed-off-by: Stefan Berger
Reviewed-by: Ninad Palsule
Revie
This series adds test cases exercising much of the TPM TIS I2C device model
assuming that the device is connected to the Aspeed I2C controller. Tests
are passing on little and big endian hosts.
This series of patches builds on the following series of patches
providing the TPM TIS I2C device emulat
Add read and write functions for accessing registers of I2C devices
connected to the Aspeed I2C controller.
Signed-off-by: Stefan Berger
Reviewed-by: Cédric Le Goater
Reviewed-by: Ninad Palsule
Acked-by: Thomas Huth
---
include/hw/i2c/aspeed_i2c.h | 7 +++
tests/qtest/qtest_aspeed.c | 117
Add a test case for the TPM TIS I2C device exercising most of its
functionality, including localities.
Signed-off-by: Stefan Berger
Tested-by: Cédric Le Goater
---
tests/qtest/meson.build| 3 +
tests/qtest/tpm-tis-i2c-test.c | 663 +
2 files changed, 66
On 3/30/23 03:37, Joel Stanley wrote:
On Tue, 28 Mar 2023 at 22:59, Richard Henderson
wrote:
The following changes since commit d37158bb2425e7ebffb167d611be01f1e9e6c86f:
Update version for v8.0.0-rc2 release (2023-03-28 20:43:21 +0100)
are available in the Git repository at:
https://g
On 3/31/23 07:50, Peter Maydell wrote:
FEAT_PAN3 adds an EPAN bit to SCTLR_EL1 and SCTLR_EL2, which allows
the PAN bit to make memory non-privileged-read/write if it is
user-executable as well as if it is user-read/write.
Implement this feature and enable it in the AArch64 'max' CPU.
Signed-off
On Wed, 29 Mar 2023 08:16:26 -0500
Eric DeVolder wrote:
> On 3/29/23 00:03, Michael S. Tsirkin wrote:
> > On Tue, Mar 28, 2023 at 11:59:26AM -0400, Eric DeVolder wrote:
> >> Currently i386 QEMU generates MADT revision 3, and reports
> >> MADT revision 1. ACPI 6.3 introduces MADT revision 5.
> >
On Fri, Mar 31, 2023 at 05:10:16PM +0100, Daniel P. Berrangé wrote:
> On Fri, Mar 31, 2023 at 11:55:03AM -0400, Peter Xu wrote:
> > On Fri, Mar 31, 2023 at 12:30:45PM -0300, Fabiano Rosas wrote:
> > > Peter Xu writes:
> > >
> > > > On Fri, Mar 31, 2023 at 11:37:50AM -0300, Fabiano Rosas wrote:
>
On Wed, 29 Mar 2023 12:47:05 -0400
"Michael S. Tsirkin" wrote:
> On Wed, Mar 29, 2023 at 08:14:37AM -0500, Eric DeVolder wrote:
> >
> >
> > On 3/29/23 00:19, Michael S. Tsirkin wrote:
> > > Hmm I don't think we can reasonably make such a change for 8.0.
> > > Seems too risky.
> > > Also, I fe
IDE TRIM is a BB user that wants to elevate its BB's in-flight counter
for a "macro" operation that consists of several actual I/O operations.
Each of those operations is individually started and awaited. It does
this so that blk_drain() will drain the whole TRIM, and not just a
single one of the
From: Ninad Palsule
Qemu already supports devices attached to ISA and sysbus. This drop adds
support for the I2C bus attached TPM devices. I2C model only supports
TPM2 protocol.
This commit includes changes for the common code.
- Added I2C emulation model. Logic was added in the model to tempora
From: Ninad Palsule
This is a documentation change for I2C TPM device support.
Qemu already supports devices attached to ISA and sysbus.
This drop adds support for the I2C bus attached TPM devices.
Signed-off-by: Ninad Palsule
Reviewed-by: Stefan Berger
Reviewed-by: Cédric Le Goater
Reviewed
From: Ninad Palsule
Qemu already supports devices attached to ISA and sysbus. This drop adds
support for the I2C bus attached TPM devices.
This commit includes changes for the common code.
- Added support for the new checksum registers which are required for
the I2C support. The checksum calcu
On Fri, Mar 31, 2023 at 04:34:57PM +0100, Daniel P. Berrangé wrote:
> On Fri, Mar 31, 2023 at 10:39:23AM -0400, Peter Xu wrote:
> > On Fri, Mar 31, 2023 at 08:56:01AM +0100, Daniel P. Berrangé wrote:
> > > On Thu, Mar 30, 2023 at 06:01:51PM -0400, Peter Xu wrote:
> > > > On Thu, Mar 30, 2023 at 03:
Hello,
Incorporated review comments from Stefan. Please review.
This drop adds support for the TPM devices attached to the I2C bus. It
only supports the TPM2 protocol. You need to run it with the external
TPM emulator like swtpm. I have tested it with swtpm.
I have refered to the work done by z
On Fri, Mar 31, 2023 at 11:55:03AM -0400, Peter Xu wrote:
> On Fri, Mar 31, 2023 at 12:30:45PM -0300, Fabiano Rosas wrote:
> > Peter Xu writes:
> >
> > > On Fri, Mar 31, 2023 at 11:37:50AM -0300, Fabiano Rosas wrote:
> > >> >> Outgoing migration to file. NVMe disk. XFS filesystem.
> > >> >>
> >
On Fri, Mar 31, 2023 at 12:30:45PM -0300, Fabiano Rosas wrote:
> Peter Xu writes:
>
> > On Fri, Mar 31, 2023 at 11:37:50AM -0300, Fabiano Rosas wrote:
> >> >> Outgoing migration to file. NVMe disk. XFS filesystem.
> >> >>
> >> >> - Single migration runs of stopped 32G guest with ~90% RAM usage.
On 3/31/23 07:50, Peter Maydell wrote:
The syndrome value reported to ESR_EL2 should only contain the
detailed instruction syndrome information when the fault has been
caused by a stage 2 abort, not when the fault was a stage 1 abort
(i.e. caused by execution at EL2). We were getting this wrong
On Fri, Mar 31, 2023 at 10:52:09AM -0400, Peter Xu wrote:
> On Fri, Mar 31, 2023 at 11:37:50AM -0300, Fabiano Rosas wrote:
> > >> Outgoing migration to file. NVMe disk. XFS filesystem.
> > >>
> > >> - Single migration runs of stopped 32G guest with ~90% RAM usage. Guest
> > >> running `stress-ng
On 3/31/23 07:50, Peter Maydell wrote:
We already pass merge_syn_data_abort() two fields from the
ARMMMUFaultInfo struct, and we're about to want to use a third field.
Refactor to just pass a pointer to the fault info.
Signed-off-by: Peter Maydell
---
target/arm/tcg/tlb_helper.c | 15 +++--
On Fri, Mar 31, 2023 at 10:39:23AM -0400, Peter Xu wrote:
> On Fri, Mar 31, 2023 at 08:56:01AM +0100, Daniel P. Berrangé wrote:
> > On Thu, Mar 30, 2023 at 06:01:51PM -0400, Peter Xu wrote:
> > > On Thu, Mar 30, 2023 at 03:03:20PM -0300, Fabiano Rosas wrote:
> > > > From: Nikolay Borisov
> > > >
Peter Xu writes:
> On Fri, Mar 31, 2023 at 11:37:50AM -0300, Fabiano Rosas wrote:
>> >> Outgoing migration to file. NVMe disk. XFS filesystem.
>> >>
>> >> - Single migration runs of stopped 32G guest with ~90% RAM usage. Guest
>> >> running `stress-ng --vm 4 --vm-bytes 90% --vm-method all --ve
Add a base save_pc For PC-relative translation(CF_PCREL).
Diable the directly sync pc from tb by riscv_cpu_synchronize_from_tb.
Sync pc before it's used or updated from tb related pc:
real_pc = (old)env->pc + target_pc(from tb) - ctx->save_pc
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wa
Compute the target address before storing it into badaddr
when mis-aligned exception is triggered.
Use a target_pc temp to store the target address to avoid
the confusing operation that udpate target address into
cpu_pc before misalign check, then update it into badaddr
and restore cpu_pc to curre
This patchset tries to fix some problem in current implementation for pointer
mask, and add support for pointer mask of instruction fetch.
The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-pm-fix-v4
v2:
* drop some error patchs
* Add patch 2 and 3 to fix the new problems
A corner case is triggered when tb block with first_pc = 0x8008
and first_pc = 0x80200 has the same jump cache hash, and share
the same tb entry with the same tb information except PC.
The executed sequence is as follows:
tb(0x8008) -> tb(0x8008)-> tb(0x80200) -> tb(0x8008)
Transform the fetch address in cpu_get_tb_cpu_state() when pointer
mask for instruction is enabled.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/cpu.h| 1 +
target/riscv/cpu_helper.c | 20 +++-
target/riscv/csr.c| 2 --
3 files changed
actual_address = (requested_address & ~mpmmask) | mpmbase.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: LIU Zhiwei
---
target/riscv/vector_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/vecto
write_mstatus() can only change current xl when in debug mode.
And we need update cur_pmmask/base in this case.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: LIU Zhiwei
---
target/riscv/csr.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/targe
CPUs often set CF_PCREL in tcg_cflags before qemu_init_vcpu(), in which
tcg_cflags will be overwrited by tcg_cpu_init_cflags().
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
accel/tcg/tcg-accel-ops.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/accel/tcg/tcg-a
The existence of CF_PCREL can improve performance with the guest
kernel's address space randomization. Each guest process maps
libc.so (et al) at a different virtual address, and this allows
those translations to be shared.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: LIU
Peter Xu writes:
>>
>> * pc - refers to the page_size/mr->addr members, so newly added members
>> begin from "bitmap_size".
>
> Could you elaborate more on what's the pc?
>
> I also didn't see this *pc in below migration.rst update.
>
Yeah, you need to be looking at the code to figure that one
I'd like to be notified on SVQ patches and review them.
Signed-off-by: Eugenio Pérez
---
MAINTAINERS | 4
1 file changed, 4 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index ef45b5e71e..986119e8ab 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2061,6 +2061,10 @@ F: backends/vhost-
On 3/31/23 07:54, Richard Henderson wrote:
On 3/30/23 03:46, Paolo Bonzini wrote:
- cc.find_library('gpg-error', required: true)])
+ cc.find_library('gpg-error', required: true)],
+ version: gcrypt.version())
Indentation.
Bah, mis-read the patch.
Reviewed-by: Richard
On 3/30/23 03:46, Paolo Bonzini wrote:
-cc.find_library('gpg-error', required: true)])
+cc.find_library('gpg-error', required: true)],
+version: gcrypt.version())
Indentation.
Reviewed-by: Richard Henderson
r~
On Fri, Mar 31, 2023 at 11:37:50AM -0300, Fabiano Rosas wrote:
> >> Outgoing migration to file. NVMe disk. XFS filesystem.
> >>
> >> - Single migration runs of stopped 32G guest with ~90% RAM usage. Guest
> >> running `stress-ng --vm 4 --vm-bytes 90% --vm-method all --verify -t
> >> 10m -v`:
>
The main purpose of this patchset is to implement FEAT_PAN3,
which allows the guest to force privileged code to not be able
to access memory that can be executed by user code. (This is
an extension of the existing FEAT_PAN which denies access
if user code could read or write the memory.) That is al
The syndrome value reported to ESR_EL2 should only contain the
detailed instruction syndrome information when the fault has been
caused by a stage 2 abort, not when the fault was a stage 1 abort
(i.e. caused by execution at EL2). We were getting this wrong and
reporting the detailed ISV informati
We already pass merge_syn_data_abort() two fields from the
ARMMMUFaultInfo struct, and we're about to want to use a third field.
Refactor to just pass a pointer to the fault info.
Signed-off-by: Peter Maydell
---
target/arm/tcg/tlb_helper.c | 15 +++
1 file changed, 7 insertions(+),
FEAT_PAN3 adds an EPAN bit to SCTLR_EL1 and SCTLR_EL2, which allows
the PAN bit to make memory non-privileged-read/write if it is
user-executable as well as if it is user-read/write.
Implement this feature and enable it in the AArch64 'max' CPU.
Signed-off-by: Peter Maydell
---
docs/system/arm/
On Fri, Mar 31, 2023 at 08:56:01AM +0100, Daniel P. Berrangé wrote:
> On Thu, Mar 30, 2023 at 06:01:51PM -0400, Peter Xu wrote:
> > On Thu, Mar 30, 2023 at 03:03:20PM -0300, Fabiano Rosas wrote:
> > > From: Nikolay Borisov
> > >
> > > Implement 'fixed-ram' feature. The core of the feature is to e
Peter Xu writes:
> On Thu, Mar 30, 2023 at 03:03:10PM -0300, Fabiano Rosas wrote:
>> Hi folks,
>
> Hi,
>
>>
>> I'm continuing the work done last year to add a new format of
>> migration stream that can be used to migrate large guests to a single
>> file in a performant way.
>>
>> This is an ear
The NetBSD support in the bsd-user fork can't even compile. It is being
removed there. Remove it here as well. If someone wants to revive it,
then I'm happy to help them do so. This hasn't built since the
conversion to meson.
Signed-off-by: Warner Losh
---
bsd-user/netbsd/host-os.h |
Remove OpenBSD system call inclusion and defines. We've not supported
building all the BSDs into one module for some time, and the OpenBSD
support hasn't even built since the meson conversion.
---
bsd-user/syscall_defs.h | 13 +
1 file changed, 1 insertion(+), 12 deletions(-)
diff --g
The OpenBSD support in the bsd-user fork can't even compile. It is being
removed there. Remove it here as well. If someone wants to revive it,
then I'm happy to help them do so. This hasn't built since the
conversion to meson.
Signed-off-by: Warner Losh
---
bsd-user/openbsd/host-os.h |
Remove OpenBSD system call tracing. We've not supported building all the
BSDs into one module for some time, and the OpenBSD support hasn't even
built since the meson conversion.
Signed-off-by: Warner Losh
---
bsd-user/qemu.h | 5 -
bsd-user/strace.c | 17 -
2 files change
Remove NetBSD system call inclusion and defines. We've not supported
building all the BSDs into one module for some time, and the NetBSD
support hasn't even built since the meson conversion.
Signed-off-by: Warner Losh
---
bsd-user/syscall_defs.h | 16
1 file changed, 16 deletion
Remove NetBSD system call tracing. We've not supported building all the
BSDs into one module for some time, and the NetBSD support hasn't even
built since the meson conversion.
Signed-off-by: Warner Losh
---
bsd-user/qemu.h | 5 -
bsd-user/strace.c | 17 -
2 files changed,
These prototypes have been obsolete since 304f944e5104.
Signed-off-by: Warner Losh
---
bsd-user/qemu.h | 6 --
1 file changed, 6 deletions(-)
diff --git a/bsd-user/qemu.h b/bsd-user/qemu.h
index 41d84e0b81..4062ee720f 100644
--- a/bsd-user/qemu.h
+++ b/bsd-user/qemu.h
@@ -169,12 +169,6 @@ a
The NetBSD and OpenBSD support in bsd-user hasn't built since before the meson
conversion. It's also out of sync with many of the recent changes in the
bsd-user fork and has just been removed there. Remove it from master for the
same reasons: it generates a number of false positives with grep and h
Please note: This did come from me, from a new machine that's slightly
misconfigured, so it didn't go through Google's email server and so you may
get a spoofing warning. I'll fix that in v2, if there is one, or in the
pull request if there's no changes.
Warner
On Fri, Mar 31, 2023 at 8:19 AM War
On Fri, Mar 31, 2023 at 12:07:56AM +, Titus Rwantare wrote:
> The ADM1266 can have string fields written by the driver, so
> it's worth specifically testing.
>
> Reviewed-by: Hao Wu
> Signed-off-by: Titus Rwantare
Acked-by: Corey Minyard
> ---
> tests/qtest/adm1266-test.c | 123 +
On Fri, Mar 31, 2023 at 12:07:55AM +, Titus Rwantare wrote:
> The ADM1266 is a cascadable super sequencer with margin control and
> fault recording.
This sounds like serious marketing-speak :). I looked up the chip and
yes, that's what they say about it.
> This commit adds basic suppor
On Fri, Mar 31, 2023 at 12:07:54AM +, Titus Rwantare wrote:
> VCAP is a register for devices with energy storage capacitors.
>
> Reviewed-by: Benjamin Streb
> Signed-off-by: Titus Rwantare
Acked-by: Corey Minyard
> ---
> hw/i2c/pmbus_device.c | 8
> include/hw/i2c/pmbus_
On Fri, Mar 31, 2023 at 12:07:53AM +, Titus Rwantare wrote:
> Devices models calling pmbus_send_string can't be relied upon to
> send a non-zero pointer. This logs an error and doesn't segfault.
>
> Reviewed-by: Patrick Venture
> Signed-off-by: Titus Rwantare
Acked-by: Corey Minyard
> ---
On Fri, Mar 31, 2023 at 12:07:52AM +, Titus Rwantare wrote:
> PMBus devices may integrate fans whose operation is configurable
> over PMBus. This commit allows the driver to read and write the
> fan control registers but does not model the operation of fans.
>
> Reviewed-by: Stephen Longfield
On Fri, Mar 31, 2023 at 12:07:51AM +, Titus Rwantare wrote:
> The VOUT_MODE command is described in the PMBus Specification,
> Part II, Ver 1.3 Section 8.3
>
> VOUT_MODE has a three bit mode and 4 bit parameter, the three bit
> mode determines whether voltages are formatted as uint16, uint16,
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