Re: [PATCH for-8.0] target/ppc: Fix temp usage in gen_op_arith_modw

On 4/7/23 20:36, Richard Henderson wrote: Fix a crash writing to 't3', which is now a constant. Instead, write the result of the remu to 'ret'. Fixes: 7058ff5231a ("target/ppc: Avoid tcg_const_* in translate.c") Reported-by: Nicholas Piggin Signed-off-by: Richard Henderson --- target/ppc/tra

[PATCH for-8.0] tcg/mips: Fix TCG_TARGET_CALL_RET_I128 for o32 abi

The return is by reference, not in 4 integer registers. This error resulted in qemu-system-i386: tcg/mips/tcg-target.c.inc:140: \ tcg_target_call_oarg_reg: Assertion `slot >= 0 && slot <= 1' failed. Fixes: 5427a9a7604 ("tcg: Add TCG_TARGET_CALL_{RET,ARG}_I128") Signed-off-by: Richard Hende

Re: [RFC PATCH 09/10] target/riscv: Restrict KVM-specific fields from ArchCPU

On 4/7/23 21:28, Richard Henderson wrote: On 4/5/23 09:04, Philippe Mathieu-Daudé wrote: These fields shouldn't be accessed when KVM is not available. Signed-off-by: Philippe Mathieu-Daudé --- RFC: The migration part is likely invalid... kvmtimer_needed() is defined in target/riscv/machine.c a

Re: [RFC PATCH 09/10] target/riscv: Restrict KVM-specific fields from ArchCPU

On 4/5/23 09:04, Philippe Mathieu-Daudé wrote: These fields shouldn't be accessed when KVM is not available. Signed-off-by: Philippe Mathieu-Daudé --- RFC: The migration part is likely invalid... kvmtimer_needed() is defined in target/riscv/machine.c as static bool kvmtimer_needed(void *opa

Re: [PATCH 07/10] target/arm: Restrict KVM-specific fields from ArchCPU

On 4/5/23 09:04, Philippe Mathieu-Daudé wrote: These fields shouldn't be accessed when KVM is not available. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/cpu.h | 2 ++ 1 file changed, 2 insertions(+) Reviewed-by: Richard Henderson r~

Re: [PATCH 06/10] target/arm: Reduce QMP header pressure by not including 'kvm_arm.h'

On 4/5/23 09:04, Philippe Mathieu-Daudé wrote: We only need "sysemu/kvm.h" for kvm_enabled() and "cpu.h" for the QOM type definitions (TYPE_ARM_CPU). Avoid including the heavy "kvm_arm.h" header. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/arm-qmp-cmds.c | 3 ++- 1 file changed, 2 in

Re: [PATCH 05/10] hw/arm/sbsa-ref: Include missing 'sysemu/kvm.h' header

On 4/5/23 09:04, Philippe Mathieu-Daudé wrote: "sysemu/kvm.h" is indirectly pulled in. Explicit its inclusion to avoid when refactoring include/: hw/arm/sbsa-ref.c:693:9: error: implicit declaration of function 'kvm_enabled' is invalid in C99 [-Werror,-Wimplicit-function-declaration] if

Re: [PATCH 04/10] hw/intc/arm_gic: Rename 'first_cpu' argument

On 4/7/23 21:23, Richard Henderson wrote: On 4/5/23 09:04, Philippe Mathieu-Daudé wrote: "hw/core/cpu.h" defines 'first_cpu' as QTAILQ_FIRST_RCU(&cpus). arm_gic_common_reset_irq_state() calls its second argument 'first_cpu', producing a build failure when "hw/core/cpu.h" is included:    hw/int

Re: [PATCH 04/10] hw/intc/arm_gic: Rename 'first_cpu' argument

On 4/5/23 09:04, Philippe Mathieu-Daudé wrote: "hw/core/cpu.h" defines 'first_cpu' as QTAILQ_FIRST_RCU(&cpus). arm_gic_common_reset_irq_state() calls its second argument 'first_cpu', producing a build failure when "hw/core/cpu.h" is included: hw/intc/arm_gic_common.c:238:68: warning: omittin

Re: [PATCH 03/10] hw/intc/arm_gic: Un-inline GIC*/ITS class_name() helpers

On 4/5/23 09:04, Philippe Mathieu-Daudé wrote: "kvm_arm.h" contains external and internal prototype declarations. Files under the hw/ directory should only access the KVM external API. In order to avoid machine / device models to include "kvm_arm.h" simply to get the QOM GIC/ITS class name, un-i

Re: [PATCH] target/arm: Fix debugging of ARMv8M Secure code

On 4/7/23 17:01, pbart...@amazon.com wrote: From: Paul Bartell Revert changes to arm_cpu_get_phys_page_attrs_debug made in commit 4a35855682cebb89f9630b07aa9fd37c4e8c733b. Commit 4a35855682 modifies the arm_cpu_get_phys_page_attrs_debug function so that it calls get_phys_addr_with_struct rathe

Re: [PATCH 1/2] accel/tcg/plugin: export host insn size

On 4/6/23 00:46, Alex Bennée wrote: If your aim is to examine JIT efficiency what is wrong with the current "info jit" that you can access via the HMP? Also I'm wondering if its time to remove the #ifdefs from CONFIG_PROFILER because I doubt the extra data it collects is that expensive. Richard,

[PATCH 11/12] tcg/mips: Use qemu_build_not_reached for LO/HI_OFF

The new(ish) macro produces a compile-time error instead of a link-time error. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 8 +++- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index e7930963fc..1df00b

[PATCH 06/12] tcg/mips: Split out tcg_out_movi_two

Emit all 32-bit signed constants, which can be loaded in two insns. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 35 --- 1 file changed, 24 insertions(+), 11 deletions(-) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index

[PATCH 08/12] tcg/mips: Aggressively use the constant pool for n64 calls

Repeated calls to a single helper are common -- especially the ones for softmmu memory access. Prefer the constant pool to longer sequences to increase sharing. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 16 +--- 1 file changed, 13 insertions(+), 3 deletions(-)

[PATCH 07/12] tcg/mips: Use the constant pool for 64-bit constants

During normal processing, the constant pool is accessible via TCG_REG_TB. During the prologue, it is accessible via TCG_REG_T9. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.h | 1 + tcg/mips/tcg-target.c.inc | 65 +-- 2 files changed, 49 inse

[PATCH 10/12] tcg/mips: Try three insns with shift and add in tcg_out_movi

These sequences are inexpensive to test. Maxing out at three insns results in the same space as a load plus the constant pool entry. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 44 +++ 1 file changed, 44 insertions(+) diff --git a/tcg/mi

[PATCH 09/12] tcg/mips: Try tb-relative addresses in tcg_out_movi

These addresses are often loaded by the qemu_ld/st slow path, for loading the retaddr value. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 13 + 1 file changed, 13 insertions(+) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index e37aca5986..8

[PATCH 12/12] tcg/mips: Replace MIPS_BE with HOST_BIG_ENDIAN

Since e03b56863d2b, which replaced HOST_WORDS_BIGENDIAN with HOST_BIG_ENDIAN, there is no need to define a second symbol which is [0,1]. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 88 ++- 1 file changed, 41 insertions(+), 47 deletions(-)

[PATCH 03/12] tcg/mips: Unify TCG_GUEST_BASE_REG tests

In tcg_out_qemu_ld/st, we already check for guest_base matching int16_t. Mirror that when setting up TCG_GUEST_BASE_REG in the prologue. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/mips/tcg-target.c.inc b/

[PATCH 01/12] tcg/mips: Move TCG_AREG0 to S8

No functional change; just moving the saved reserved regs to the end. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.h | 2 +- tcg/mips/tcg-target.c.inc | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/tcg/mips/tcg-target

[PATCH 05/12] tcg/mips: Split out tcg_out_movi_one

Emit all constants that can be loaded in exactly one insn. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 26 -- 1 file changed, 20 insertions(+), 6 deletions(-) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index c2f8d6550b..f0ae41

[PATCH 02/12] tcg/mips: Move TCG_GUEST_BASE_REG to S7

No functional change; just moving the saved reserved regs to the end. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc

[PATCH 04/12] tcg/mips: Create and use TCG_REG_TB

This vastly reduces the size of code generated for 64-bit addresses. The code for exit_tb, for instance, where we load a (tagged) pointer to the current TB, goes from 0x400aa9725c: li v0,64 0x400aa97260: dsll v0,v0,0x10 0x400aa97264: ori v0,v0,0xaa9 0x400aa97268: dsll v0,v0,

[PATCH for-8.1 00/12] tcg/mips: Backend improvements

I've posted some of these before, perhaps a year or more ago, but then failed to follow up and get them merged. I don't think there are any real dependencies, but it has been rebased upon today's load/store helpers patch set, so there might be minor conflicts, therefore: Based-on: 20230408024314.

[PATCH 33/42] tcg/mips: Reorg tcg_out_tlb_load

Compare the address vs the tlb entry with sign-extended values. This simplifies the page+alignment mask constant, and the generation of the last byte address for the misaligned test. Move the tlb addend load up, and the zero-extension down. This frees up a register, which allows us to drop the 'b

[PATCH 39/42] tcg/s390x: Use ALGFR in constructing host address for qemu_ld/st

Rather than zero-extend the guest address into a register, use an add instruction which zero-extends the second input. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 38 ++ 1 file changed, 22 insertions(+), 16 deletions(-) diff --git a/tcg/

[PATCH 16/42] tcg: Introduce tcg_out_movext

This is common code in most qemu_{ld,st} slow paths, extending the input value for the store helper data argument or extending the return value from the load helper. Signed-off-by: Richard Henderson --- tcg/tcg.c| 59 tcg/aarch64/tcg-targe

[PATCH 40/42] tcg/s390x: Simplify constraints on qemu_ld/st

Adjust the softmmu tlb to use R0+R1, not any of the normally available registers. Since we handle overlap betwen inputs and helper arguments, we can allow any allocatable reg. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-con-set.h | 2 -- tcg/s390x/tcg-target-con-str.h | 1 - tcg

[PATCH 31/42] tcg: Introduce tcg_out_st_helper_args

Centralize the logic to call the helper_stN_mmu functions. Signed-off-by: Richard Henderson --- tcg/tcg.c| 189 ++- tcg/aarch64/tcg-target.c.inc | 24 ++-- tcg/arm/tcg-target.c.inc | 106 ++--- tcg/i386/tcg-target.c.inc

[PATCH 09/42] tcg: Split out tcg_out_exts_i32_i64

We will need a backend interface for type extension with sign. Use it in tcg_reg_alloc_op in the meantime. Signed-off-by: Richard Henderson --- tcg/tcg.c| 4 tcg/aarch64/tcg-target.c.inc | 9 ++--- tcg/arm/tcg-target.c.inc | 5 + tcg/i386/tcg-targ

[PATCH 23/42] tcg/arm: Use TCGType not bool is_64 in tcg_out_qemu_{ld, st}

We need to set this in TCGLabelQemuLdst, so plumb this all the way through from tcg_out_op. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 28 +++- 1 file changed, 15 insertions(+), 13 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-targ

[PATCH 08/42] tcg: Split out tcg_out_ext32u

We will need a backend interface for performing 32-bit zero-extend. Use it in tcg_reg_alloc_op in the meantime. Signed-off-by: Richard Henderson --- tcg/tcg.c| 4 tcg/aarch64/tcg-target.c.inc | 9 +++-- tcg/arm/tcg-target.c.inc | 5 + tcg/i386/

[PATCH 18/42] tcg: Introduce tcg_out_movext2

This is common code in most qemu_{ld,st} slow paths, moving two registers when there may be overlap between sources and destinations. At present, this is only used by 32-bit hosts for 64-bit data, but will shortly be used for more than that. Signed-off-by: Richard Henderson --- tcg/tcg.c

[PATCH 14/42] tcg/i386: Conditionalize tcg_out_extu_i32_i64

Since TCG_TYPE_I32 values are kept zero-extended in registers, via omission of the REXW bit, we need not extend if the register matches. This is already relied upon by qemu_{ld,st}. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 4 +++- 1 file changed, 3 insertions(+), 1 deleti

[PATCH 22/42] tcg/aarch64: Pass TGType to tcg_out_qemu_st

This evens out the interface to match tcg_out_qemu_ld, and makes the argument to add_qemu_ldst_label less obscure. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarc

[PATCH 25/42] tcg/ppc: Use TCGType not bool is_64 in tcg_out_qemu_{ld, st}

We need to set this in TCGLabelQemuLdst, so plumb this all the way through from tcg_out_op. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 24 +--- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c

[PATCH 13/42] tcg: Split out tcg_out_extu_i32_i64

We will need a backend interface for type extension with zero. Use it in tcg_reg_alloc_op in the meantime. Signed-off-by: Richard Henderson --- tcg/tcg.c| 4 tcg/aarch64/tcg-target.c.inc | 10 ++ tcg/arm/tcg-target.c.inc | 5 + tcg/i386/tcg-

[PATCH 10/42] tcg/loongarch64: Conditionalize tcg_out_exts_i32_i64

Since TCG_TYPE_I32 values are kept sign-extended in registers, via ".w" instructions, we need not extend if the register matches. This is already relied upon by comparisons. Signed-off-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 4 +++- 1 file changed, 3 insertions(+), 1 deletio

[PATCH 32/42] tcg/loongarch64: Simplify constraints on qemu_ld/st

The softmmu tlb uses TCG_REG_TMP[0-2], not any of the normally available registers. Now that we handle overlap betwen inputs and helper arguments, we can allow any allocatable reg. Signed-off-by: Richard Henderson --- tcg/loongarch64/tcg-target-con-set.h | 2 -- tcg/loongarch64/tcg-target-con-

[PATCH 15/42] tcg: Split out tcg_out_extrl_i64_i32

We will need a backend interface for type truncation. For those backends that did not enable TCG_TARGET_HAS_extrl_i64_i32, use tcg_out_mov. Use it in tcg_reg_alloc_op in the meantime. Signed-off-by: Richard Henderson --- tcg/tcg.c| 4 tcg/aarch64/tcg-target.c.inc

[PATCH 12/42] tcg/riscv: Conditionalize tcg_out_exts_i32_i64

Since TCG_TYPE_I32 values are kept sign-extended in registers, via "w" instructions, we need not extend if the register matches. This is already relied upon by comparisons. Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) d

[PATCH 19/42] tcg: Clear TCGLabelQemuLdst on allocation

Signed-off-by: Richard Henderson --- tcg/tcg-ldst.c.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/tcg/tcg-ldst.c.inc b/tcg/tcg-ldst.c.inc index 6c6848d034..403cbb0f06 100644 --- a/tcg/tcg-ldst.c.inc +++ b/tcg/tcg-ldst.c.inc @@ -72,6 +72,7 @@ static inline TCGLabelQemuLdst *new_ldst_labe

[PATCH 42/42] tcg/sparc64: Pass TCGType to tcg_out_qemu_{ld,st}

We need to set this in TCGLabelQemuLdst, so plumb this all the way through from tcg_out_op. Signed-off-by: Richard Henderson --- tcg/sparc64/tcg-target.c.inc | 15 +++ 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.

[PATCH 38/42] tcg/riscv: Simplify constraints on qemu_ld/st

The softmmu tlb uses TCG_REG_TMP[0-2], not any of the normally available registers. Now that we handle overlap betwen inputs and helper arguments, we can allow any allocatable reg. Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target-con-set.h | 2 -- tcg/riscv/tcg-target-con-str.h | 1 -

[PATCH 24/42] tcg/i386: Use TCGType not bool is_64 in tcg_out_qemu_{ld, st}

There are several places where we already convert back from bool to type. Clean things up by using type throughout. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 56 +++ 1 file changed, 27 insertions(+), 29 deletions(-) diff --git a/tcg/mi

[PATCH 41/42] tcg/sparc64: Drop is_64 test from tcg_out_qemu_ld data return

In tcg_canonicalize_memop, we remove MO_SIGN from MO_32 operations with TCG_TYPE_I32. Thus this is never set. We already have an identical test just above which does not include is_64 Signed-off-by: Richard Henderson --- tcg/sparc64/tcg-target.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 de

[PATCH 21/42] tcg/aarch64: Rename ext to d_type in tcg_out_qemu_ld

The new name is slightly more descritive as "data type", where "extend", despite the c type, sounds like a bool. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aar

[PATCH for-8.1 00/42] tcg: Simplify calls to load/store helpers

There are several changes to the load/store helpers coming, and making sure that those changes are properly reflected across all of the backends was harrowing. I have gone back and restarted by hoisting the code out of the backends and into tcg.c. We already have all of the parameters for the hos

[PATCH 04/42] tcg: Split out tcg_out_ext8u

We will need a backend interface for performing 8-bit zero-extend. Use it in tcg_reg_alloc_op in the meantime. Signed-off-by: Richard Henderson --- tcg/tcg.c| 5 + tcg/aarch64/tcg-target.c.inc | 11 +++ tcg/arm/tcg-target.c.inc | 12 +---

[PATCH 36/42] tcg/ppc: Adjust constraints on qemu_ld/st

The softmmu tlb uses TCG_REG_{TMP1,TMP2,R0}, not any of the normally available registers. Now that we handle overlap betwen inputs and helper arguments, we can allow any allocatable reg. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target-con-set.h | 11 --- tcg/ppc/tcg-target-con-s

[PATCH 37/42] tcg/ppc: Remove unused constraints A, B, C, D

These constraints have not been used for quite some time. Fixes: 77b73de67632 ("Use rem/div[u]_i32 drop div[u]2_i32") Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target-con-str.h | 4 1 file changed, 4 deletions(-) diff --git a/tcg/ppc/tcg-target-con-str.h b/tcg/ppc/tcg-target-con-str

[PATCH 34/42] tcg/mips: Simplify constraints on qemu_ld/st

The softmmu tlb uses TCG_REG_TMP[0-3], not any of the normally available registers. Now that we handle overlap betwen inputs and helper arguments, we can allow any allocatable reg. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target-con-set.h | 13 + tcg/mips/tcg-target-con-str

[PATCH 27/42] tcg/riscv: Require TCG_TARGET_REG_BITS == 64

The port currently does not support "oversize" guests, which means riscv32 can only target 32-bit guests. We will soon be building TCG once for all guests. This implies that we can only support riscv64. Since all Linux distributions target riscv64 not riscv32, this is not much of a restriction a

[PATCH 35/42] tcg/ppc: Reorg tcg_out_tlb_read

Allocate TCG_REG_TMP2. Use R0, TMP1, TMP2 instead of any of the normally allocated registers for the tlb load. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 83 +++- 1 file changed, 48 insertions(+), 35 deletions(-) diff --git a/tcg/ppc/tcg

[PATCH 11/42] tcg/mips: Conditionalize tcg_out_exts_i32_i64

Since TCG_TYPE_I32 values are kept sign-extended in registers, we need not extend if the register matches. This is already relied upon by comparisons. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/tcg/mips/t

[PATCH 20/42] tcg/i386: Use TCGType not bool is_64 in tcg_out_qemu_{ld, st}

There are several places where we already convert back from bool to type. Clean things up by using type throughout. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 35 +-- 1 file changed, 17 insertions(+), 18 deletions(-) diff --git a/tcg/i386/t

[PATCH 17/42] tcg: Introduce tcg_out_xchg

We will want a backend interface for register swapping. This is only properly defined for x86; all others get a stub version that always indicates failure. Signed-off-by: Richard Henderson --- tcg/tcg.c| 2 ++ tcg/aarch64/tcg-target.c.inc | 5 + tcg/arm/tcg-target

[PATCH 28/42] tcg/riscv: Expand arguments to tcg_out_qemu_{ld,st}

Now that the host is always 64-bit, the address and data operands are always one operand each. In addition, change to using TCGType to describe the data operand. Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 47 +++--- 1 file changed, 18 inser

[PATCH 01/42] tcg: Replace if + tcg_abort with tcg_debug_assert

Signed-off-by: Richard Henderson --- tcg/tcg.c | 4 +--- tcg/i386/tcg-target.c.inc | 8 +++- 2 files changed, 4 insertions(+), 8 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index bb52bc060b..100f81edb2 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1174,9 +1174,7 @@ static TC

[PATCH 07/42] tcg: Split out tcg_out_ext32s

We will need a backend interface for performing 32-bit sign-extend. Use it in tcg_reg_alloc_op in the meantime. Signed-off-by: Richard Henderson --- tcg/tcg.c| 4 tcg/aarch64/tcg-target.c.inc | 9 +++-- tcg/arm/tcg-target.c.inc | 5 + tcg/i386/

[PATCH 06/42] tcg: Split out tcg_out_ext16u

We will need a backend interface for performing 16-bit zero-extend. Use it in tcg_reg_alloc_op in the meantime. Signed-off-by: Richard Henderson --- tcg/tcg.c| 5 + tcg/aarch64/tcg-target.c.inc | 13 - tcg/arm/tcg-target.c.inc | 17 ++-

[PATCH 29/42] tcg: Move TCGLabelQemuLdst to tcg.c

This will shortly be used by sparc64 without also using TCG_TARGET_NEED_LDST_LABELS. Signed-off-by: Richard Henderson --- tcg/tcg.c | 13 + tcg/tcg-ldst.c.inc | 14 -- 2 files changed, 13 insertions(+), 14 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 1c

[PATCH 05/42] tcg: Split out tcg_out_ext16s

We will need a backend interface for performing 16-bit sign-extend. Use it in tcg_reg_alloc_op in the meantime. Signed-off-by: Richard Henderson --- tcg/tcg.c| 7 +++ tcg/aarch64/tcg-target.c.inc | 13 - tcg/arm/tcg-target.c.inc | 10 -

[PATCH 02/42] tcg: Replace tcg_abort with g_assert_not_reached

Signed-off-by: Richard Henderson --- include/tcg/tcg.h| 6 -- target/i386/tcg/translate.c | 20 ++-- target/s390x/tcg/translate.c | 4 ++-- tcg/optimize.c | 10 -- tcg/tcg.c| 8 tcg/aarch64/tcg-target.c.inc |

[PATCH 30/42] tcg: Introduce tcg_out_ld_helper_args

Centralize the logic to call the helper_ldN_mmu functions. This loses out slightly on mips by not filling the delay slot, but the result is more maintainable. Signed-off-by: Richard Henderson --- tcg/tcg.c| 187 +++ tcg/aarch64/tcg-target.c.inc

[PATCH 26/42] tcg/s390x: Pass TCGType to tcg_out_qemu_{ld,st}

We need to set this in TCGLabelQemuLdst, so plumb this all the way through from tcg_out_op. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 22 ++ 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-targe

[PATCH for-8.0] tcg/i386: Adjust assert in tcg_out_addi_ptr

We can arrive here on _WIN64 because Int128 is passed by reference. Change the assert to check that the immediate is in range, instead of attempting to check the host ABI. Fixes: 6a6d772e30d ("tcg: Introduce tcg_out_addi_ptr") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1581 Signed-off

[PATCH 03/42] tcg: Split out tcg_out_ext8s

We will need a backend interface for performing 8-bit sign-extend. Use it in tcg_reg_alloc_op in the meantime. Signed-off-by: Richard Henderson --- tcg/tcg.c| 21 - tcg/aarch64/tcg-target.c.inc | 11 +++ tcg/arm/tcg-target.c.inc | 1

Re: [PATCH v12 02/10] target/riscv: add support for Zca extension

On 2023/4/8 03:25, Daniel Henrique Barboza wrote: On 4/7/23 00:34, liweiwei wrote: On 2023/4/7 09:14, liweiwei wrote: On 2023/4/7 04:22, Daniel Henrique Barboza wrote: Hi, This patch is going to break the sifive_u boot if I rebase "[PATCH v6 0/9] target/riscv: rework CPU extensions val

[PATCH V4] tracing: install trace events file only if necessary

From: Carlos Santos It is not useful when configuring with --enable-trace-backends=nop. Signed-off-by: Carlos Santos --- Changes v1->v2: Install based on chosen trace backend, not on chosen emulators. Changes v2->v3: Add missing comma Changes v3->v4: Fix array comparison: get_option('

[PATCH] block/vhdx: fix dynamic VHDX BAT corruption

The corruption occurs when a BAT entry aligned to 4096 bytes is changed. Specifically, the corruption occurs during the creation of the LOG Data Descriptor. The incorrect behavior involves copying 4088 bytes from the original 4096 bytes aligned offset to `tmp[8..4096]` and then copying the new val

[PATCH] target/arm: Fix debugging of ARMv8M Secure code

From: Paul Bartell Revert changes to arm_cpu_get_phys_page_attrs_debug made in commit 4a35855682cebb89f9630b07aa9fd37c4e8c733b. Commit 4a35855682 modifies the arm_cpu_get_phys_page_attrs_debug function so that it calls get_phys_addr_with_struct rather than get_phys_addr, which leads to a variety

Re: [PATCH 02/10] accel/kvm: Declare kvm_direct_msi_allowed in stubs

On 4/5/23 09:04, Philippe Mathieu-Daudé wrote: Avoid when calling kvm_direct_msi_enabled() from arm_gicv3_its_common.c the next commit: Undefined symbols for architecture arm64: "_kvm_direct_msi_allowed", referenced from: _its_class_name in hw_intc_arm_gicv3_its_common.c.o ld

Re: [PATCH 01/10] sysemu/kvm: Remove unused headers

On 4/5/23 09:04, Philippe Mathieu-Daudé wrote: All types used are forward-declared in "qemu/typedefs.h". Signed-off-by: Philippe Mathieu-Daudé --- include/sysemu/kvm.h | 3 --- 1 file changed, 3 deletions(-) Reviewed-by: Richard Henderson r~

Re: [PATCH 2/2] accel/stubs: Build HAX/KVM/XEN stubs once

On 4/5/23 09:13, Philippe Mathieu-Daudé wrote: +softmmu_ss.add_all(when: ['CONFIG_SOFTMMU'], if_true: sysemu_stubs_ss) This when is redundant. You can drop sysemu_stubs_ss and add each stub file directly to softmmu_ss. r~

Re: [PATCH 1/2] accel/stubs: Remove kvm_flush_coalesced_mmio_buffer() stub

On 4/5/23 09:13, Philippe Mathieu-Daudé wrote: kvm_flush_coalesced_mmio_buffer() is only called from qemu_flush_coalesced_mmio_buffer() where it is protected by a kvm_enabled() check. When KVM is not available, the call is elided, there is no need for a stub definition. Reviewed-by: Richard Hen

[PATCH V3] tracing: install trace events file only if necessary

From: Carlos Santos It is not useful when configuring with --enable-trace-backends=nop. Signed-off-by: Carlos Santos --- Changes v1->v2: Install based on chosen trace backend, not on chosen emulators. Changes v2->v3: Add missing comma --- trace/meson.build | 2 +- 1 file changed, 1 inserti

Re: [PATCH 14/14] accel: Rename HVF struct hvf_vcpu_state -> struct AccelvCPUState

On 4/5/23 03:18, Philippe Mathieu-Daudé wrote: We want all accelerators to share the same opaque pointer in CPUState. Rename the 'hvf_vcpu_state' structure as 'AccelvCPUState'. Use the generic 'accel' field of CPUState instead of 'hvf'. Replace g_malloc0() by g_new0() for readability. Signed-

Re: [PATCH 13/14] accel: Inline WHPX get_whpx_vcpu()

On 4/5/23 03:18, Philippe Mathieu-Daudé wrote: No need for this helper to access the CPUState::accel field. Signed-off-by: Philippe Mathieu-Daudé --- target/i386/whpx/whpx-all.c | 29 ++--- 1 file changed, 10 insertions(+), 19 deletions(-) Reviewed-by: Richard Hender

Re: [PATCH 12/14] accel: Rename WHPX struct whpx_vcpu -> struct AccelvCPUState

On 4/5/23 03:18, Philippe Mathieu-Daudé wrote: We want all accelerators to share the same opaque pointer in CPUState. Rename WHPX 'whpx_vcpu' as 'AccelvCPUState'. Signed-off-by: Philippe Mathieu-Daudé --- target/i386/whpx/whpx-all.c | 30 +++--- 1 file changed, 15 ins

Re: [PATCH 11/14] accel: Inline NVMM get_qemu_vcpu()

On 4/5/23 03:18, Philippe Mathieu-Daudé wrote: No need for this helper to access the CPUState::accel field. Signed-off-by: Philippe Mathieu-Daudé --- target/i386/nvmm/nvmm-all.c | 28 +++- 1 file changed, 11 insertions(+), 17 deletions(-) Reviewed-by: Richard Henders

Re: [PATCH 10/14] accel: Rename NVMM struct qemu_vcpu -> struct AccelvCPUState

On 4/5/23 03:18, Philippe Mathieu-Daudé wrote: -struct qemu_vcpu *qcpu = get_qemu_vcpu(cpu); +struct AccelvCPUState *qcpu = get_qemu_vcpu(cpu); With the typedef in hw/core/cpu.h, you can drop the 'struct' at the same time. Otherwise, Reviewed-by: Richard Henderson -qcpu = g_try_

Re: [PATCH 07/14] accel: Rename struct hax_vcpu_state -> struct AccelvCPUState

On 4/5/23 03:18, Philippe Mathieu-Daudé wrote: +struct AccelvCPUState; Missing typedef? r~

Re: [PATCH 08/14] accel: Move HAX hThread to accelerator context

On 4/5/23 03:18, Philippe Mathieu-Daudé wrote: hThread variable is only used by the HAX accelerator, so move it to the accelerator specific context. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/core/cpu.h | 1 - target/i386/hax/hax-i386.h | 3 +++ target/i386/hax/hax-a

Re: [PATCH 07/14] accel: Rename struct hax_vcpu_state -> struct AccelvCPUState

On 4/5/23 03:18, Philippe Mathieu-Daudé wrote: We want all accelerators to share the same opaque pointer in CPUState. Start with the HAX context, renaming its forward declarated structure 'hax_vcpu_state' as 'AccelvCPUState'. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/core/cpu.h

Re: [PATCH 05/14] accel: Rename 'hax_vcpu' as 'accel' in CPUState

On 4/5/23 03:18, Philippe Mathieu-Daudé wrote: All accelerators will share a single opaque context in CPUState. Start by renaming 'hax_vcpu' as 'accelCPUState'. Pasto in 'accel' here. Reviewed-by: Richard Henderson r~

Re: [PATCH 02/14] accel: Remove unused hThread variable on TCG/WHPX

On 4/5/23 03:17, Philippe Mathieu-Daudé wrote: On Windows hosts, cpu->hThread is assigned but never accessed: remove it. Signed-off-by: Philippe Mathieu-Daudé --- accel/tcg/tcg-accel-ops-mttcg.c | 4 accel/tcg/tcg-accel-ops-rr.c | 3 --- target/i386/whpx/whpx-accel-ops.c | 3 ---

Re: [PATCH 01/14] accel: Document generic accelerator headers

On 4/5/23 03:17, Philippe Mathieu-Daudé wrote: These headers are meant to be include by any file to check the availability of accelerators, thus are not accelerator specific. Signed-off-by: Philippe Mathieu-Daudé --- include/sysemu/hax.h | 2 ++ include/sysemu/kvm.h | 2 ++ include/sysemu/

Re: [PATCH 03/14] accel: Fix a leak on Windows HAX

On 4/5/23 03:18, Philippe Mathieu-Daudé wrote: hThread is only used on the error path in hax_kick_vcpu_thread(). Fixes: b0cb0a66d6 ("Plumb the HAXM-based hardware acceleration support") Signed-off-by: Philippe Mathieu-Daudé --- target/i386/hax/hax-all.c | 3 +++ 1 file changed, 3 insertions(+

Re: [PULL 5/6] edk2: replace build scripts

Mon, 20 Mar 2023 10:38:46 +0100 Gerd Hoffmann : > Remove Makefile.edk2 and the edk2*.sh scripts and replace them > with a python script (which already handles fedora rpm builds) > and a config file for it. This breaks 'make roms efirom' (in case this happens to be a valid make target). Olaf pg

[PATCH] Hexagon (target/hexagon) Additional instructions handled by idef-parser

Currently, idef-parser skips all floating point instructions. However, there are some floating point instructions that can be handled. The following instructions are now parsed F2_sfimm_p F2_sfimm_n F2_dfimm_p F2_dfimm_n F2_dfmpyll F2_dfmpylh To make these instructions wo

[PATCH] do not lockdown github PRs submitted to forks of official mirror

From: "Lauren N. Liberda" qemu forks on github are typically the way of work on changes to be upstreamed later, such as support for new devices. currently, the workflow prevents any external contributors from submitting code changes, and blindly points them to upstream instead. Signed-off-by: La

[PATCH] Hexagon (target/hexagon) Remove unused slot variable in helpers

The slot variable in helpers was only passed to log_reg_write function where the argument is unused. - Remove declaration from generated helper functions - Remove slot argument from log_reg_write Signed-off-by: Taylor Simpson --- target/hexagon/macros.h| 2 +- target/hexagon/op_helpe

Re: [PATCH 8/8] block, block-backend: write some hot coroutine wrappers by hand

Il ven 7 apr 2023, 22:04 Eric Blake ha scritto: > On Fri, Apr 07, 2023 at 05:33:03PM +0200, Paolo Bonzini wrote: > > The introduction of the graph lock is causing blk_get_geometry, a hot > function > > used in the I/O path, to create a coroutine. However, the only part > that really > > needs to

Re: [PATCH 8/8] block, block-backend: write some hot coroutine wrappers by hand

On Fri, Apr 07, 2023 at 05:33:03PM +0200, Paolo Bonzini wrote: > The introduction of the graph lock is causing blk_get_geometry, a hot function > used in the I/O path, to create a coroutine. However, the only part that > really > needs to run in coroutine context is the call to > bdrv_co_refresh

Re: [PATCH 7/8] block-backend: ignore inserted state in blk_co_nb_sectors

On Fri, Apr 07, 2023 at 05:33:02PM +0200, Paolo Bonzini wrote: > All callers of blk_co_nb_sectors (and blk_nb_sectors) are able to > handle a non-inserted CD-ROM as a zero-length file, they do not need > to raise an error. > > Not using blk_co_is_available() aligns the function with > blk_co_get_g

Re: [PATCH 6/8] block-backend: inline bdrv_co_get_geometry

On Fri, Apr 07, 2023 at 05:33:01PM +0200, Paolo Bonzini wrote: > bdrv_co_get_geometry is only used in blk_co_get_geometry. Inline it in > there, to reduce the number of wrappers for bs->total_sectors. > > Signed-off-by: Paolo Bonzini > --- > block.c | 10 -- > block/blo

Re: [PATCH 5/8] migration/block: replace uses of blk_nb_sectors that do not check result

On Fri, Apr 07, 2023 at 05:33:00PM +0200, Paolo Bonzini wrote: > Uses of blk_nb_sectors must check whether the result is negative. > Otherwise, underflow can happen. Fortunately, alloc_aio_bitmap() > and bmds_aio_inflight() both have an alternative way to retrieve the > number of sectors in the fi

Re: [PATCH 4/8] block: remove has_variable_length from BlockDriver

On Fri, Apr 07, 2023 at 05:32:59PM +0200, Paolo Bonzini wrote: > Fill in the field in BlockLimits directly for host devices, and > copy it from there for the raw format. > > Signed-off-by: Paolo Bonzini > --- > block/file-posix.c | 12 > block/file-win32.c

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