On Tue, Apr 11, 2023 at 2:29 PM Eugenio Perez Martin
wrote:
>
> On Tue, Apr 11, 2023 at 4:26 AM Jason Wang wrote:
> >
> > On Mon, Apr 10, 2023 at 5:05 PM Eugenio Perez Martin
> > wrote:
> > >
> > > On Mon, Apr 10, 2023 at 5:22 AM Jason Wang wrote:
> > > >
> > > > On Mon, Apr 10, 2023 at 11:17 A
在 2023/4/5 23:38, Steven Sistare 写道:
On 4/4/2023 6:00 PM, Philippe Mathieu-Daudé wrote:
On 4/4/23 18:00, Steve Sistare wrote:
When net_init_tap() succeeds for a multi-queue device, it returns a
non-zero ret=1 code to its caller, because of this code where ret becomes
Indeed g_unix_set_fd_non
On Tue, Apr 11, 2023 at 4:26 AM Jason Wang wrote:
>
> On Mon, Apr 10, 2023 at 5:05 PM Eugenio Perez Martin
> wrote:
> >
> > On Mon, Apr 10, 2023 at 5:22 AM Jason Wang wrote:
> > >
> > > On Mon, Apr 10, 2023 at 11:17 AM Longpeng (Mike, Cloud Infrastructure
> > > Service Product Dept.) wrote:
> >
On Sun, Apr 9, 2023 at 12:00 AM Weiwei Li wrote:
>
> Zdinx/Zhinx{min} require Zfinx. And require relationship is usually done
> by check currently.
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
Acked-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c | 5 +++--
> 1 file
On Sat, Mar 25, 2023 at 9:58 PM Richard Henderson
wrote:
>
> This builds on Fei and Zhiwei's SUM and TB_FLAGS changes.
>
> * Reclaim 5 TB_FLAGS bits, since we nearly ran out.
>
> * Using cpu_mmu_index(env, true) is insufficient to implement
> HLVX properly. While that chooses the correct
On Sat, Mar 25, 2023 at 10:56 PM Richard Henderson
wrote:
>
> Implement this by adjusting prot, which reduces the set of
> checks required. This prevents exec to be set for U pages
> in MMUIdx_S_SUM. While it had been technically incorrect,
> it did not manifest as a bug, because we will never a
On Fri, Apr 7, 2023 at 11:49 AM Weiwei Li wrote:
>
> This patchset tries to fix some problems in current implementation for
> mstatus.MPP
>
> The port is available here:
> https://github.com/plctlab/plct-qemu/tree/plct-mpp-fix-v3
>
> v3:
> * add patch 2 to remove PRV_H, and use PRV_RESERVED inste
On Sat, Mar 25, 2023 at 9:51 PM Richard Henderson
wrote:
>
> We were effectively computing the protection bits twice,
> once while performing access checks and once while returning
> the valid bits to the caller. Reorg so we do this once.
>
> Move the computation of mxr close to its single use.
>
On Sat, Mar 25, 2023 at 10:35 PM Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu_helper.c | 12 ++--
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/target/riscv/cpu_helper.c b/target/ris
On Sat, Mar 25, 2023 at 10:56 PM Richard Henderson
wrote:
>
> The debugger should not modify PTE_A or PTE_D.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu_helper.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/
On Sat, Mar 25, 2023 at 9:55 PM Richard Henderson
wrote:
>
> If we want to give the debugger a greater view of memory than
> the cpu, we should simply disable the access check entirely,
> not simply for this one corner case.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Al
On Sun, Mar 26, 2023 at 2:03 AM Richard Henderson
wrote:
>
> Move the code that never loops outside of the loop.
> Unchain the if-return-else statements.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu_helper.c | 234 +-
On Sat, Mar 25, 2023 at 9:56 PM Richard Henderson
wrote:
>
> These values are constant for every level of pte lookup.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu_helper.c | 16
> 1 file changed, 8 insertions(+), 8 dele
On Sat, Mar 25, 2023 at 10:29 PM Richard Henderson
wrote:
>
> Move the check from the top of get_physical_address to
> the two callers, where passing mmu_idx makes no sense.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu_helper.c | 10 ++-
On Sat, Mar 25, 2023 at 10:42 PM Richard Henderson
wrote:
>
> Table 9.5 "Effect of MPRV..." specifies that MPV=1 uses VS-level
> vsstatus.SUM instead of HS-level sstatus.SUM.
>
> For HLV/HSV instructions, the HS-level register does not apply, but
> the VS-level register presumably does, though thi
Hi Nick, Fabiano,
Any review comments, please?
regards,
Harsh
On 3/31/23 16:36, Daniel Henrique Barboza wrote:
On 3/31/23 07:39, Cédric Le Goater wrote:
On 3/31/23 08:53, Harsh Prateek Bora wrote:
This patchset introduces helper routines to enable (and does) cleaning
up of h_enter_nested()
Use linux specific PR_SET_VMA_ANON_NAME (introduced in v5.17) to set ram
block name in the kernel. This makes each ram block distinguishable and
can help debugging and inspection. The names of ram blocks are shown in
/proc/pid/maps like this:
7f00e940-7f00f140 rw-p 00:00 0
On Sat, Mar 25, 2023 at 9:58 PM Richard Henderson
wrote:
>
> Incorporate the virt_enabled and MPV checks into the cpu_mmu_index
> function, so we don't have to keep doing it within tlb_fill and
> subroutines. This also elides a flush on changes to MPV.
>
> Signed-off-by: Richard Henderson
Revie
On Sat, Mar 25, 2023 at 9:57 PM Richard Henderson
wrote:
>
> The current cpu_mmu_index value is really irrelevant to
> the HLV/HSV lookup. Provide the correct priv level directly.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu_helper.c |
On Sat, Mar 25, 2023 at 9:53 PM Richard Henderson
wrote:
>
> Move and rename riscv_cpu_two_stage_lookup, to match
> the other mmuidx_* functions.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.h| 1 -
> target/riscv/internals.h
On Sat, Mar 25, 2023 at 9:53 PM Richard Henderson
wrote:
>
> Use the priv level encoded into the mmu_idx, rather than
> starting from env->priv. We have already checked MPRV+MPP
> in riscv_cpu_mmu_index -- no need to repeat that.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Franci
On Wed, Apr 5, 2023 at 2:07 PM Alistair Francis wrote:
>
> On Mon, Apr 3, 2023 at 11:43 PM Wu, Fei wrote:
> >
> > Recent commit 0ee342256af92 switches to g_assert() for the predicate()
> > NULL check from returning RISCV_EXCP_ILLEGAL_INST. Qemu doesn't have
> > predicate() for un-allocated CSRs,
On Sat, Mar 25, 2023 at 9:55 PM Richard Henderson
wrote:
>
> In get_physical_address, we should use the setting passed
> via mmu_idx rather than checking env->mstatus directly.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/internals.h | 5 +
On Sat, Mar 25, 2023 at 9:57 PM Richard Henderson
wrote:
>
> We will enable more uses of this bit in the future.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/internals.h | 6 --
> target/riscv/cpu_helper.c | 2 +-
> target/riscv/op_hel
On Sat, Mar 25, 2023 at 9:53 PM Richard Henderson
wrote:
>
> Implement these instructions via helpers, in expectation
> of determining the mmu_idx to use at runtime. This allows
> the permission check to also be moved out of line, which
> allows HLSX to be removed from TB_FLAGS.
>
> Signed-off-by
On Sat, Mar 25, 2023 at 9:53 PM Richard Henderson
wrote:
>
> Use the new functions to properly check execute permission
> for the read rather than read permission.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/op_helper.c | 13 +++--
On Sat, Mar 25, 2023 at 9:52 PM Richard Henderson
wrote:
>
> At least RISC-V has the need to be able to perform a read
> using execute permissions, outside of translation.
> Add helpers to facilitate this.
>
> Signed-off-by: Richard Henderson
Acked-by: Alistair Francis
Alistair
> ---
> inclu
On Mon, Apr 10, 2023 at 7:37 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 4/10/23 11:20, Warner Losh wrote:
> > Update the system call list. We have one hokey thing in here for swapoff
> > that depends on the version number (so this is not completely generated
> > at the moment
> -Original Message-
> From: Richard Henderson
> Sent: Monday, April 10, 2023 8:30 PM
> To: Taylor Simpson ; qemu-devel@nongnu.org
> Cc: phi...@linaro.org; a...@rev.ng; a...@rev.ng; Brian Cain
> ; Matheus Bernardino (QUIC)
>
> Subject: Re: [PATCH] Hexagon (target/hexagon) Add overrides
On Mon, Apr 10, 2023 at 5:05 PM Eugenio Perez Martin
wrote:
>
> On Mon, Apr 10, 2023 at 5:22 AM Jason Wang wrote:
> >
> > On Mon, Apr 10, 2023 at 11:17 AM Longpeng (Mike, Cloud Infrastructure
> > Service Product Dept.) wrote:
> > >
> > >
> > >
> > > 在 2023/4/10 10:14, Jason Wang 写道:
> > > > On W
On Sat, Mar 25, 2023 at 9:57 PM Richard Henderson
wrote:
>
> From: Fei Wu
>
> Kernel needs to access user mode memory e.g. during syscalls, the window
> is usually opened up for a very limited time through MSTATUS.SUM, the
> overhead is too much if tlb_flush() gets called for every SUM change.
>
On Sat, Mar 25, 2023 at 10:01 PM Richard Henderson
wrote:
>
> From: Fei Wu
>
> Currently it's assumed the 2 low bits of mmu_idx map to privilege mode,
> this assumption won't last as we are about to add more mmu_idx. Here an
> individual priv field is added into TB_FLAGS.
>
> Reviewed-by: Richard
On Sat, Mar 25, 2023 at 9:52 PM Richard Henderson
wrote:
>
> From: LIU Zhiwei
>
> Once we mistook the vstart directly from the env->vstart. As env->vstart is
> not
> a constant, we should record it in the tb flags if we want to use
> it in translation.
>
> Reported-by: Richard Henderson
> Revie
On Sat, Mar 25, 2023 at 9:58 PM Richard Henderson
wrote:
>
> From: LIU Zhiwei
>
> The pointer masking is the only extension that directly use status.
> The vector or float extension uses the status in an indirect way.
>
> Replace the pointer masking extension special status fields with
> the gene
On 4/10/23 09:52, Daniel Henrique Barboza wrote:
This command is used by tooling like libvirt to retrieve a list of
supported CPUs. Each entry returns a CpuDefinitionInfo object that
contains more information about each CPU.
This initial support includes only the name of the CPU and its typename
On 4/10/23 09:52, Daniel Henrique Barboza wrote:
'static' is defined in the QMP doc as:
"whether a CPU definition is static and will not change depending on
QEMU version, machine type, machine options and accelerator options. A
static model is always migration-safe."
For RISC-V we'll consider a
On Sat, Mar 25, 2023 at 10:36 PM Richard Henderson
wrote:
>
> Merge with mstatus_{fs,vs}. We might perform a redundant
> assignment to one or the other field, but it's a trivial
> and saves 4 bits from TB_FLAGS.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> --
On Sat, Mar 25, 2023 at 10:01 PM Richard Henderson
wrote:
>
> From: LIU Zhiwei
>
> Reuse the MSTATUS_FS and MSTATUS_VS for the tb flags positions is not a
> normal way.
>
> It will make it hard to change the tb flags layout. And even worse, if we
> want to keep tb flags for a same extension togat
On 4/10/23 09:52, Daniel Henrique Barboza wrote:
QMP CPU commands are usually implemented by a separated file,
-qmp-cmds.c, to allow them to be build only for softmmu targets.
This file uses a CPU QOM header with basic QOM declarations for the
arch.
We'll introduce query-cpu-definitions for RISC
On 4/10/23 07:13, Mayuresh Chitale wrote:
+#ifndef CONFIG_USER_ONLY
+#define smstateen_fcsr_check(ctx) do { \
+if (!ctx->smstateen_fcsr_ok) { \
+if (ctx->virt_enabled) { \
+generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT); \
+} else { \
+gener
On Fri, Apr 7, 2023 at 11:49 AM Weiwei Li wrote:
>
> mstatus.MPP field is a WARL field since priv version 1.11, so we
> remain it unchanged if an invalid value is written into it. And
> after this, RVH shouldn't be passed to riscv_cpu_set_mode().
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junq
On Fri, Apr 7, 2023 at 11:49 AM Weiwei Li wrote:
>
> PRV_H has no real meaning, but just a reserved privilege mode currently.
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.h | 2 +-
> target/riscv/cpu_bits.h
On 4/10/23 07:13, Mayuresh Chitale wrote:
The state of smstateen0.FCSR bit impacts the execution of floating point
instructions when misa.F==0. Add a field in the tb->flags which stores
the current state of smstateen0.fcsr and will be used by floating point
translation routines.
Are you certain
On Fri, Apr 7, 2023 at 4:06 AM Daniel Henrique Barboza
wrote:
>
> Hi,
>
> This new version was rebased on top of Alistair's riscv-to-apply.next @
> 9c60ca583cb ("hw/riscv: Add signature dump function ...").
>
> No other changes made.
>
> Changes from v3:
> - rebased with riscv-to-apply.next @ 9c60
On 4/10/23 11:20, Warner Losh wrote:
Update the system call list. We have one hokey thing in here for swapoff
that depends on the version number (so this is not completely generated
at the moment). For this, we need to include sys/param.h. The method of
generation has changed, so this diff looks
On 4/10/23 11:20, Warner Losh wrote:
It's enabled on all platforms (even in the fork), so we can remove it
from here.
Signed-off-by: Warner Losh
---
bsd-user/arm/target_arch_elf.h| 1 -
bsd-user/elfcore.c| 3 ---
bsd-user/elfload.c| 5 -
bsd-user/i386
David Hildenbrand writes:
On 01.04.23 01:50, Ackerley Tng wrote:
For memfd_restricted() calls without a userspace mount, the backing
file should be the shmem mount in the kernel, and the size of backing
pages should be as defined by system-wide shmem configuration.
If a userspace mount is p
On 4/10/23 11:20, Warner Losh wrote:
It only defines the default system call scheme to use. However, that
feature was removed in a941a16f6f52.
Signed-off-by: Warner Losh
---
bsd-user/freebsd/host-os.h | 25 -
bsd-user/main.c| 1 -
bsd-user/netbsd/host-os.
On 4/10/23 11:20, Warner Losh wrote:
MAP_GUARD, MAP_EXCL, and MAP_NOCORE are FreeBSD only. Define them to be
0 if they aren't defined, and rely on the compiler to optimize away
sections not relevant. Added only to the top of mmap.c since that's the
only place we need this.
Signed-off-by: Warner
Hello,
This patchset builds upon the memfd_restricted() system call that was
discussed in the 'KVM: mm: fd-based approach for supporting KVM' patch
series, at
https://lore.kernel.org/lkml/20221202061347.1070246-1-chao.p.p...@linux.intel.com/T/
The tree can be found at:
https://github.com/googlepr
On 4/10/23 13:24, Taylor Simpson wrote:
Most of these are not modelled in QEMU, so save the overhead of
calling a helper.
The only exception is dczeroa. It assigns to hex_dczero_addr, which
is handled during packet commit.
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 24 +
For memfd_restricted() calls without a userspace mount, the backing
file should be the shmem mount in the kernel, and the size of backing
pages should be as defined by system-wide shmem configuration.
If a userspace mount is provided, the size of backing pages should be
as defined in the mount.
A
By default, the backing shmem file for a restrictedmem fd is created
on shmem's kernel space mount.
With this patch, an optional tmpfs mount can be specified via an fd,
which will be used as the mountpoint for backing the shmem file
associated with a restrictedmem fd.
This will help restrictedmem
On 3/31/23 11:28, Christoph Muellner wrote:
+/*
+ * Implement float64 to int32_t conversion without saturation;
+ * the result is supplied modulo 2^32.
+ * Rounding mode is RTZ.
+ * Flag behaviour identical to fcvt.w.d (see F specification).
+ *
+ * Similar conversion of this function can be foun
On 4/9/23 13:10, Stefan Weil wrote:
Resolves:https://gitlab.com/qemu-project/qemu/-/issues/1529
Signed-off-by: Stefan Weil
---
I suggest to apply the patch for 8.0 because it fixes documentation.
Reviewed-by: Richard Henderson
r~
Since TCG_TYPE_I32 values are kept sign-extended in registers, we need not
extend if the register matches. This is already relied upon by comparisons.
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target.c.inc | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/tcg/mips/t
On 4/9/23 13:18, Stefan Weil via wrote:
Signed-off-by: Stefan Weil
---
If my change is okay I suggest to apply the patch for 8.0
because it fixes documentation.
Regards,
Stefan W.
docs/system/devices/cxl.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/docs/system/de
Use tcg_out_ld_helper_args, tcg_out_ld_helper_ret,
and tcg_out_st_helper_args.
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 37 ++--
1 file changed, 11 insertions(+), 26 deletions(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loong
Signed-off-by: Richard Henderson
---
tcg/tcg-ldst.c.inc | 1 +
1 file changed, 1 insertion(+)
diff --git a/tcg/tcg-ldst.c.inc b/tcg/tcg-ldst.c.inc
index 6c6848d034..403cbb0f06 100644
--- a/tcg/tcg-ldst.c.inc
+++ b/tcg/tcg-ldst.c.inc
@@ -72,6 +72,7 @@ static inline TCGLabelQemuLdst *new_ldst_labe
This will shortly be used by sparc64 without also using
TCG_TARGET_NEED_LDST_LABELS.
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 13 +
tcg/tcg-ldst.c.inc | 14 --
2 files changed, 13 insertions(+), 14 deletions(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index cf
Since TCG_TYPE_I32 values are kept sign-extended in registers,
via ".w" instructions, we need not extend if the register matches.
This is already relied upon by comparisons.
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 4 +++-
1 file changed, 3 insertions(+), 1 deletio
The softmmu tlb uses TCG_REG_TMP[0-2], not any of the normally available
registers. Now that we handle overlap betwen inputs and helper arguments,
we can allow any allocatable reg.
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target-con-set.h | 2 --
tcg/loongarch64/tcg-target-con-
We will want a backend interface for register swapping.
This is only properly defined for x86; all others get a
stub version that always indicates failure.
Signed-off-by: Richard Henderson
---
tcg/tcg.c| 2 ++
tcg/aarch64/tcg-target.c.inc | 5 +
tcg/arm/tcg-target
While performing the load in the delay slot of the call to the common
bswap helper function is cute, it is not worth the added complexity.
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target.h | 4 +-
tcg/mips/tcg-target.c.inc | 284 ++
2 files chan
Unify all computation of argument stack offset in one function.
This requires that we adjust ref_slot to be in the same units,
by adding max_reg_slots during init_call_layout.
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 29 +
1 file changed, 17 insertions(+), 12
We will need a backend interface for performing 32-bit zero-extend.
Use it in tcg_reg_alloc_op in the meantime.
Signed-off-by: Richard Henderson
---
tcg/tcg.c| 4
tcg/aarch64/tcg-target.c.inc | 9 +++--
tcg/arm/tcg-target.c.inc | 5 +
tcg/i386/
Use tcg_out_ld_helper_args, tcg_out_ld_helper_ret,
and tcg_out_st_helper_args.
Signed-off-by: Richard Henderson
---
tcg/riscv/tcg-target.c.inc | 37 ++---
1 file changed, 10 insertions(+), 27 deletions(-)
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-ta
Use tcg_out_ld_helper_args, tcg_out_ld_helper_ret,
and tcg_out_st_helper_args.
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.c.inc | 88
1 file changed, 26 insertions(+), 62 deletions(-)
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-targe
Mark the argument registers const, because they must be passed to
add_qemu_ldst_label unmodified. Rename the 'ext' parameter 'data_type' to
make the use clearer; pass it to tcg_out_qemu_st as well to even out the
interfaces. Rename the 'otype' local 'addr_type' to make the use clearer.
Signed-of
These constraints have not been used for quite some time.
Fixes: 77b73de67632 ("Use rem/div[u]_i32 drop div[u]2_i32")
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target-con-str.h | 4
1 file changed, 4 deletions(-)
diff --git a/tcg/ppc/tcg-target-con-str.h b/tcg/ppc/tcg-target-con-str
Use tcg_out_st_helper_args. This eliminates the use of
a tail call to the store helper. This may or may not be
an improvement, depending on the call/return branch
prediction of the host microarchitecture.
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.c.inc | 55 +++--
Adjust the softmmu tlb to use R0+R1, not any of the normally available
registers. Since we handle overlap betwen inputs and helper arguments,
we can allow any allocatable reg.
Signed-off-by: Richard Henderson
---
tcg/s390x/tcg-target-con-set.h | 2 --
tcg/s390x/tcg-target-con-str.h | 1 -
tcg
The softmmu tlb uses TCG_REG_TMP[0-3], not any of the normally available
registers. Now that we handle overlap betwen inputs and helper arguments,
we can allow any allocatable reg.
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target-con-set.h | 13 +
tcg/mips/tcg-target-con-str
The softmmu tlb uses TCG_REG_TMP[0-2], not any of the normally available
registers. Now that we handle overlap betwen inputs and helper arguments,
we can allow any allocatable reg.
Signed-off-by: Richard Henderson
---
tcg/riscv/tcg-target-con-set.h | 2 --
tcg/riscv/tcg-target-con-str.h | 1 -
Allocate TCG_REG_TMP2. Use R0, TMP1, TMP2 instead of any of
the normally allocated registers for the tlb load.
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.c.inc | 84 +++-
1 file changed, 49 insertions(+), 35 deletions(-)
diff --git a/tcg/ppc/tcg
We will need a backend interface for type extension with zero.
Use it in tcg_reg_alloc_op in the meantime.
Signed-off-by: Richard Henderson
---
tcg/tcg.c| 4
tcg/aarch64/tcg-target.c.inc | 10 ++
tcg/arm/tcg-target.c.inc | 5 +
tcg/i386/tcg-
We need to set this in TCGLabelQemuLdst, so plumb this
all the way through from tcg_out_op.
Signed-off-by: Richard Henderson
---
tcg/s390x/tcg-target.c.inc | 22 ++
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-targe
Interpret the variable argument placement in the caller.
Mark the argument registers const, because they must be passed to
add_qemu_ldst_label unmodified. Shift some code around slightly
to share more between softmmu and user-only.
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target
The softmmu tlb uses TCG_REG_{TMP1,TMP2,R0}, not any of the normally
available registers. Now that we handle overlap betwen inputs and
helper arguments, we can allow any allocatable reg.
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target-con-set.h | 11 ---
tcg/ppc/tcg-target-con-s
Rather than zero-extend the guest address into a register,
use an add instruction which zero-extends the second input.
Signed-off-by: Richard Henderson
---
tcg/s390x/tcg-target.c.inc | 38 ++
1 file changed, 22 insertions(+), 16 deletions(-)
diff --git a/tcg/
Use tcg_out_ld_helper_args, tcg_out_ld_helper_ret,
and tcg_out_st_helper_args.
Signed-off-by: Richard Henderson
---
tcg/s390x/tcg-target.c.inc | 35 ++-
1 file changed, 10 insertions(+), 25 deletions(-)
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-targ
We will need a backend interface for type extension with sign.
Use it in tcg_reg_alloc_op in the meantime.
Signed-off-by: Richard Henderson
---
tcg/tcg.c| 4
tcg/aarch64/tcg-target.c.inc | 9 ++---
tcg/arm/tcg-target.c.inc | 5 +
tcg/i386/tcg-targ
Interpret the variable argument placement in the caller.
Mark the argument register const, because they must be passed to
add_qemu_ldst_label unmodified. This requires a bit of local
variable renaming, because addrlo was being modified.
Pass data_type instead of is64 -- there are several places w
We will need a backend interface for performing 8-bit sign-extend.
Use it in tcg_reg_alloc_op in the meantime.
Signed-off-by: Richard Henderson
---
tcg/tcg.c| 21 -
tcg/aarch64/tcg-target.c.inc | 11 +++
tcg/arm/tcg-target.c.inc | 1
Interpret the variable argument placement in the caller.
Mark the argument registers const, because they must be passed to
add_qemu_ldst_label unmodified. There are several places where we
already convert back from bool to type. Clean things up by using
type throughout.
Signed-off-by: Richard He
Compare the address vs the tlb entry with sign-extended values.
This simplifies the page+alignment mask constant, and the
generation of the last byte address for the misaligned test.
Move the tlb addend load up, and the zero-extension down.
This frees up a register, which allows us to drop the 'b
Use tcg_out_ld_helper_args and tcg_out_ld_helper_ret.
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.c.inc | 69 ---
1 file changed, 28 insertions(+), 41 deletions(-)
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 2b2759d69
An inline function is safer than a macro, and REG_P
was rather too generic.
Signed-off-by: Richard Henderson
---
tcg/tcg-internal.h | 4
tcg/tcg.c | 16 +---
2 files changed, 13 insertions(+), 7 deletions(-)
diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h
index e
Interpret the variable argument placement in the caller.
Mark the argument register const, because they must be passed to
add_qemu_ldst_label unmodified.
Pass data_type instead of is64 -- there are several places where
we already convert back from bool to type. Clean things up by
using type throu
Since TCG_TYPE_I32 values are kept zero-extended in registers, via
omission of the REXW bit, we need not extend if the register matches.
This is already relied upon by qemu_{ld,st}.
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.c.inc | 4 +++-
1 file changed, 3 insertions(+), 1 deleti
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 4 +---
tcg/i386/tcg-target.c.inc | 8 +++-
2 files changed, 4 insertions(+), 8 deletions(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index bb52bc060b..100f81edb2 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1174,9 +1174,7 @@ static TC
Interpret the variable argument placement in the caller.
Mark the argument registers const, because they must be passed to
add_qemu_ldst_label unmodified.
Pass data_type instead of is64 -- there are several places where
we already convert back from bool to type. Clean things up by
using type thro
We need to set this in TCGLabelQemuLdst, so plumb this
all the way through from tcg_out_op.
Signed-off-by: Richard Henderson
---
tcg/sparc64/tcg-target.c.inc | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.
Interpret the variable argument placement in the caller.
Mark the argument registers const, because they must be passed to
add_qemu_ldst_label unmodified.
Pass data_type instead of is_64. We need to set this in
TCGLabelQemuLdst, so plumb this all the way through from tcg_out_op.
Signed-off-by: R
Use tcg_out_ld_helper_args, tcg_out_ld_helper_ret,
and tcg_out_st_helper_args. This allows our local
tcg_out_arg_* infrastructure to be removed.
We are no longer filling the call or return branch
delay slots, nor are we tail-calling for the store,
but this seems a small price to pay.
Signed-off-
Since TCG_TYPE_I32 values are kept sign-extended in registers,
via "w" instructions, we need not extend if the register matches.
This is already relied upon by comparisons.
Signed-off-by: Richard Henderson
---
tcg/riscv/tcg-target.c.inc | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
d
Use tcg_out_ld_helper_args, tcg_out_ld_helper_ret,
and tcg_out_st_helper_args. This allows our local
tcg_out_arg_* infrastructure to be removed.
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.c.inc | 146 ++-
1 file changed, 21 insertions(+), 125 del
We will need a backend interface for type truncation. For those backends
that did not enable TCG_TARGET_HAS_extrl_i64_i32, use tcg_out_mov.
Use it in tcg_reg_alloc_op in the meantime.
Signed-off-by: Richard Henderson
---
tcg/tcg.c| 4
tcg/aarch64/tcg-target.c.inc
In tcg_canonicalize_memop, we remove MO_SIGN from MO_32 operations
with TCG_TYPE_I32. Thus this is never set. We already have an
identical test just above which does not include is_64
Signed-off-by: Richard Henderson
---
tcg/sparc64/tcg-target.c.inc | 2 +-
1 file changed, 1 insertion(+), 1 de
We will need a backend interface for performing 8-bit zero-extend.
Use it in tcg_reg_alloc_op in the meantime.
Signed-off-by: Richard Henderson
---
tcg/tcg.c| 5 +
tcg/aarch64/tcg-target.c.inc | 11 +++
tcg/arm/tcg-target.c.inc | 12 +---
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