Windows sends an extra left control key up/down input event for
every right alt key up/down input event for keyboards with
international layout. Since commit 830473455f ("ui/sdl2: fix
handling of AltGr key on Windows") QEMU uses a Windows low level
keyboard hook procedure to reliably filter out the
Based-on: <20230417192139.43263-1-shen...@gmail.com>
([PATCH v2 0/2] SDL2 usability fixes)
Windows sends an extra left control key up/down input event for
every right alt key up/down input event for keyboards with
international layout. Since commit 830473455f ("ui/sdl2: fix
handling of AltGr key
On Apr 18 09:26, Minwoo Im wrote:
> Fix status code overwritten issue in the COPY command and a trivial
> patch to check the Maximum Copy Length (MCL) for COPY command.
>
> Minwoo Im (2):
> hw/nvme: consider COPY command in nvme_aio_err
> hw/nvme: check maximum copy length (MCL) for COPY
>
>
On Apr 18 09:20, Minwoo Im wrote:
> From: Minwoo Im
>
> Add more comments of existing properties for nvme-ns device.
>
> Signed-off-by: Minwoo Im
> Reviewed-by: Klaus Jensen
> ---
> hw/nvme/ctrl.c | 9 -
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/hw/nvme/ctrl.c
On 17/04/2023 18.23, Vaibhav Jain wrote:
Since commit fd8171fe52b5e("target/hexagon: import lexer for idef-parser") the
hexagon target uses 'flex', 'bison' to generate idef-parser. However default
travis builder image for 'focal' may not have these pre-installed, consequently
following error is s
Windows sends an extra left control key up/down input event for
every right alt key up/down input event for keyboards with
international layout. Since commit 830473455f ("ui/sdl2: fix
handling of AltGr key on Windows") QEMU uses a Windows low level
keyboard hook procedure to reliably filter out the
Based-on: <20230417192139.43263-1-shen...@gmail.com>
("[PATCH v2 0/2] SDL2 usability fixes")
Windows sends an extra left control key up/down input event for every
right alt key up/down input event for keyboards with international
layout. Since commit 830473455f ("ui/sdl2: fix handling of AltGr
On Tue, Apr 18, 2023 at 05:13:11AM +, Raphael Norwitz wrote:
> Hey Andrey - apologies for the late reply here.
>
> It sounds like you are dealing with a buggy guest, rather than a QEMU issue.
>
> > On Apr 10, 2023, at 11:39 AM, Andrey Ryabinin wrote:
> >
> >
> >
> > On 4/10/23 10:35, Andr
SDL doesn't grab Alt+F4 under Windows by default. Pressing Alt+F4 thus closes
the VM immediately without confirmation, possibly leading to data loss. Fix
this by always grabbing Alt+F4 on Windows hosts, too.
Signed-off-by: Bernhard Beschow
---
ui/sdl2.c | 1 +
1 file changed, 1 insertion(+)
By default, SDL grabs Alt+Tab only in non-fullscreen mode. This causes Alt+Tab
to switch tasks on the host rather than in the VM in fullscreen mode while it
switches tasks in non-fullscreen mode in the VM. Fix this confusing behavior
by grabbing Alt+Tab in fullscreen mode, always causing tasks to
On 2023/4/18 12:47, LIU Zhiwei wrote:
On 2023/4/18 11:36, Weiwei Li wrote:
On 2023/4/18 11:07, LIU Zhiwei wrote:
On 2023/4/13 17:01, Weiwei Li wrote:
This patchset tries to fix the PMP bypass problem issue
https://gitlab.com/qemu-project/qemu/-/issues/1542
Please add your analysis of th
On 2023/4/18 13:18, LIU Zhiwei wrote:
On 2023/4/18 11:05, Weiwei Li wrote:
On 2023/4/18 10:53, Alistair Francis wrote:
On Thu, Apr 13, 2023 at 7:04 PM Weiwei Li wrote:
Not only the matched PMP entry, Any PMP entry that overlap with
partial of
the tlb page may make the regions in that page
Commit c0c8687ef0fd990db8db1655a8a6c5a5e35dd4bb disabled the
boot_linux.py test-case due to which the code coverage for ppc
decreased by around 2%. As per the discussion on
https://lore.kernel.org/qemu-devel/87sfdpqcy4@linaro.org/ it
was mentioned that the baseline test for ppc64 could be modif
On 2023/4/18 11:05, Weiwei Li wrote:
On 2023/4/18 10:53, Alistair Francis wrote:
On Thu, Apr 13, 2023 at 7:04 PM Weiwei Li wrote:
Not only the matched PMP entry, Any PMP entry that overlap with
partial of
the tlb page may make the regions in that page have different
permission
rights. So
Hey Andrey - apologies for the late reply here.
It sounds like you are dealing with a buggy guest, rather than a QEMU issue.
> On Apr 10, 2023, at 11:39 AM, Andrey Ryabinin wrote:
>
>
>
> On 4/10/23 10:35, Andrey Ryabinin wrote:
>> Some guests hang on boot when using the vhost-user-blk-pci de
On 2023/4/18 11:36, Weiwei Li wrote:
On 2023/4/18 11:07, LIU Zhiwei wrote:
On 2023/4/13 17:01, Weiwei Li wrote:
This patchset tries to fix the PMP bypass problem issue
https://gitlab.com/qemu-project/qemu/-/issues/1542
Please add your analysis of this issue here.
By the way, I think this
Since the driver doesn't support interrupts, we must return early when
index is set to VIRTIO_CONFIG_IRQ_IDX.
Fixes: 544f0278afca ("virtio: introduce macro VIRTIO_CONFIG_IRQ_IDX")
Signed-off-by: Viresh Kumar
---
V2: Simplify and fix comments.
hw/virtio/vhost-user-i2c.c | 16
1
On 2023/4/18 11:07, LIU Zhiwei wrote:
On 2023/4/13 17:01, Weiwei Li wrote:
This patchset tries to fix the PMP bypass problem issue
https://gitlab.com/qemu-project/qemu/-/issues/1542
Please add your analysis of this issue here.
By the way, I think this problem is introduced by
https://www.
On 2023/4/13 17:01, Weiwei Li wrote:
This patchset tries to fix the PMP bypass problem issue
https://gitlab.com/qemu-project/qemu/-/issues/1542
Please add your analysis of this issue here.
By the way, I think this problem is introduced by
https://www.mail-archive.com/qemu-devel@nongnu.org/
On 2023/4/18 10:53, Alistair Francis wrote:
On Thu, Apr 13, 2023 at 7:04 PM Weiwei Li wrote:
Not only the matched PMP entry, Any PMP entry that overlap with partial of
the tlb page may make the regions in that page have different permission
rights. So all of them should be taken into consider
On Thu, Apr 13, 2023 at 7:04 PM Weiwei Li wrote:
>
> pmp_get_tlb_size have no relationship with pmp-related permission check
> currently.
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu_helper.c | 16 ++-
On Thu, Apr 13, 2023 at 7:04 PM Weiwei Li wrote:
>
> Not only the matched PMP entry, Any PMP entry that overlap with partial of
> the tlb page may make the regions in that page have different permission
> rights. So all of them should be taken into consideration.
>
> Signed-off-by: Weiwei Li
> Si
Hi Phil, Meng,
Would you please kindly review and comments on below patch, this fixes an issue
when imx/s3c sdhci controller is used. We plan to have one new NXP platform
supported in QEMU following this. Thanks again.
Regards,
Hake
From: Hake Huang (OSS)
Sent: 2023年4月12日 16:42
To: phi...@lin
On Thu, Apr 13, 2023 at 7:04 PM Weiwei Li wrote:
>
> TLB needn't be flushed when pmpcfg/pmpaddr don't changes.
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/pmp.c | 24
> 1 file changed, 16 in
On Thu, Apr 13, 2023 at 7:03 PM Weiwei Li wrote:
>
> TLB should be flushed not only for pmpcfg csr changes, but also for
> pmpaddr csr changes.
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/pmp.c | 1 +
> 1 file chang
On Tue, Apr 18, 2023 at 12:01 AM Lawrence Hunter
wrote:
>
> From: Kiran Ostrolenk
>
> Factor the non SEW-specific stuff out of `GEN_OPIVV_TRANS` into
> function `opivv_trans` (similar to `opivi_trans`). `opivv_trans` will be
> used in proceeding vector-crypto commits.
>
> Signed-off-by: Kiran Ost
On Mon, Apr 17, 2023 at 8:47 PM Andrea Parri wrote:
>
> Hi Alistair,
>
> > > @@ -936,6 +936,11 @@ restart:
> > > return TRANSLATE_FAIL;
> > > }
> > >
> > > +/* PTE reserved bits must be cleared otherwise an exception is
> > > raised */
> > > +if (riscv_cpu_mx
On Mon, Apr 17, 2023 at 10:57 AM Drew Fustini wrote:
>
> From: Nicolas Pitre
>
> Implement a capacity controller according to the Capacity and Bandwidth
> QoS Register Interface (CBQRI) which supports these capabilities:
>
> - Number of access types: 2 (code and data)
> - Usage monitoring ope
On 23-03-30 14:44:27, Paolo Bonzini wrote:
> The last argument to -pci_nvme_err_startfail_virt_state is always "OFFLINE"
> due to the enclosing "if" condition requiring !sctrl->scs. Reported by
> Coverity.
>
> Signed-off-by: Paolo Bonzini
Reviewed-by: Minwoo Im
On 2023/4/18 00:25, Daniel Henrique Barboza wrote:
On 4/13/23 06:01, Weiwei Li wrote:
When PMP entry overlap part of the page, we'll set the tlb_size to 1,
and
this will make the address set with TLB_INVALID_MASK to make the page
un-cached. However, if we clear TLB_INVALID_MASK when TLB is
Fix status code overwritten issue in the COPY command and a trivial
patch to check the Maximum Copy Length (MCL) for COPY command.
Minwoo Im (2):
hw/nvme: consider COPY command in nvme_aio_err
hw/nvme: check maximum copy length (MCL) for COPY
hw/nvme/ctrl.c | 25 +
1
From: Minwoo Im
If we don't have NVME_CMD_COPY consideration in the switch statement in
nvme_aio_err(), it will go to have NVME_INTERNAL_DEV_ERROR and
`req->status` will be ovewritten to it. During the aio context, it
might set the NVMe status field like NVME_CMD_SIZE_LIMIT, but it's
overwritten
From: Minwoo Im
MCL(Maximum Copy Length) in the Identify Namespace data structure limits
the number of LBAs to be copied inside of the controller. We've not
checked it at all, so added the check with returning the proper error
status.
Signed-off-by: Minwoo Im
Reviewed-by: Klaus Jensen
---
hw
Fix status code overwritten issue in the COPY command and a trivial
patch to check the Maximum Copy Length (MCL) for COPY command.
Minwoo Im (2):
hw/nvme: consider COPY command in nvme_aio_err
hw/nvme: check maximum copy length (MCL) for COPY
hw/nvme/ctrl.c | 25 +
1
From: Minwoo Im
Add more comments of existing properties for nvme-ns device.
Signed-off-by: Minwoo Im
Reviewed-by: Klaus Jensen
---
hw/nvme/ctrl.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c
index 8b7be14209..87c07f5dbb 100644
--
In a multi-seat scenario where multiple keyboards and mice are connected
to the host but some are dedicated for the guests only (through pass
through mode) and some are only for the host, there is a strong use case
where a customer does not want a HID device connected to the host to be
able to cont
Am 14. April 2023 19:09:47 UTC schrieb "Volker Rümelin" :
>> Am 13.04.23 um 22:43 schrieb Bernhard Beschow:
>>>
>>> Am 13. April 2023 17:54:34 UTC schrieb "Volker Rümelin"
>>> :
> I'm trying to use QEMU on Windows hosts for fun and for profit. While the
> GTK
> GUI doesn't seem to
On Mon, 17 Apr 2023 at 15:12, Eugenio Perez Martin wrote:
>
> On Mon, Apr 17, 2023 at 9:08 PM Stefan Hajnoczi wrote:
> >
> > On Mon, 17 Apr 2023 at 14:56, Eugenio Perez Martin
> > wrote:
> > >
> > > On Mon, Apr 17, 2023 at 5:18 PM Stefan Hajnoczi
> > > wrote:
> > > >
> > > > On Fri, Apr 14, 2
On Mon, 17 Apr 2023 at 15:10, Eugenio Perez Martin wrote:
>
> On Mon, Apr 17, 2023 at 5:38 PM Stefan Hajnoczi wrote:
> >
> > On Thu, Apr 13, 2023 at 12:14:24PM +0200, Eugenio Perez Martin wrote:
> > > On Wed, Apr 12, 2023 at 11:06 PM Stefan Hajnoczi
> > > wrote:
> > > >
> > > > On Tue, Apr 11,
I'm trying to use QEMU on Windows hosts for fun and for profit. While the GTK
GUI doesn't seem to support OpenGL under Windows the SDL2 GUI does. Hence I
used the SDL2 GUI where I ran into several issues of which two are fixed in
this series, which are:
* Alt+Tab switches tasks on the host rather
SDL doesn't grab Alt+F4 under Windows by default. Pressing Alt+F4 thus closes
the VM immediately without confirmation, possibly leading to data loss. Fix
this by always grabbing Alt+F4 on Windows hosts, too.
Signed-off-by: Bernhard Beschow
---
ui/sdl2.c | 1 +
1 file changed, 1 insertion(+)
dif
By default, SDL grabs Alt+Tab only in non-fullscreen mode. This causes Alt+Tab
to switch tasks on the host rather than in the VM in fullscreen mode while it
switches tasks in non-fullscreen mode in the VM. Fix this confusing behavior
by grabbing Alt+Tab in fullscreen mode, always causing tasks to b
On Mon, 17 Apr 2023 at 15:08, Eugenio Perez Martin wrote:
>
> On Mon, Apr 17, 2023 at 7:14 PM Stefan Hajnoczi wrote:
> >
> > On Thu, Apr 13, 2023 at 12:14:24PM +0200, Eugenio Perez Martin wrote:
> > > On Wed, Apr 12, 2023 at 11:06 PM Stefan Hajnoczi
> > > wrote:
> > > >
> > > > On Tue, Apr 11,
On Mon, Apr 17, 2023 at 9:08 PM Stefan Hajnoczi wrote:
>
> On Mon, 17 Apr 2023 at 14:56, Eugenio Perez Martin
> wrote:
> >
> > On Mon, Apr 17, 2023 at 5:18 PM Stefan Hajnoczi wrote:
> > >
> > > On Fri, Apr 14, 2023 at 05:17:02PM +0200, Eugenio Perez Martin wrote:
> > > > On Thu, Apr 13, 2023 at
On Mon, Apr 17, 2023 at 5:38 PM Stefan Hajnoczi wrote:
>
> On Thu, Apr 13, 2023 at 12:14:24PM +0200, Eugenio Perez Martin wrote:
> > On Wed, Apr 12, 2023 at 11:06 PM Stefan Hajnoczi
> > wrote:
> > >
> > > On Tue, Apr 11, 2023 at 05:05:13PM +0200, Hanna Czenczek wrote:
> > > > So-called "internal
On Mon, 17 Apr 2023 at 14:56, Eugenio Perez Martin wrote:
>
> On Mon, Apr 17, 2023 at 5:18 PM Stefan Hajnoczi wrote:
> >
> > On Fri, Apr 14, 2023 at 05:17:02PM +0200, Eugenio Perez Martin wrote:
> > > On Thu, Apr 13, 2023 at 7:55 PM Hanna Czenczek wrote:
> > > >
> > > > On 13.04.23 13:38, Stefan
On Mon, Apr 17, 2023 at 7:14 PM Stefan Hajnoczi wrote:
>
> On Thu, Apr 13, 2023 at 12:14:24PM +0200, Eugenio Perez Martin wrote:
> > On Wed, Apr 12, 2023 at 11:06 PM Stefan Hajnoczi
> > wrote:
> > >
> > > On Tue, Apr 11, 2023 at 05:05:13PM +0200, Hanna Czenczek wrote:
> > > > So-called "internal
On Mon, Apr 17, 2023 at 5:18 PM Stefan Hajnoczi wrote:
>
> On Fri, Apr 14, 2023 at 05:17:02PM +0200, Eugenio Perez Martin wrote:
> > On Thu, Apr 13, 2023 at 7:55 PM Hanna Czenczek wrote:
> > >
> > > On 13.04.23 13:38, Stefan Hajnoczi wrote:
> > > > On Thu, 13 Apr 2023 at 05:24, Hanna Czenczek wr
On Thu, Apr 13, 2023 at 7:32 PM Hanna Czenczek wrote:
>
> On 13.04.23 12:14, Eugenio Perez Martin wrote:
> > On Wed, Apr 12, 2023 at 11:06 PM Stefan Hajnoczi
> > wrote:
> >> On Tue, Apr 11, 2023 at 05:05:13PM +0200, Hanna Czenczek wrote:
> >>> So-called "internal" virtio-fs migration refers to t
On Mon, Apr 17, 2023 at 9:43 AM Alex Bennée wrote:
>
> This is the current state of my testing tree. It contains a few
> patches that didn't make it into 8.0 and more testing fixes including
> a bump to the avocado release including Thomas' --max-parallel-tasks
> hack to avoid running the tests in
John Snow writes:
> On Mon, Apr 17, 2023 at 9:43 AM Alex Bennée wrote:
>>
>> From: Kautuk Consul
>>
>> Avocado version 101.0 has a fix to re-compute the checksum
>> of an asset file if the algorithm used in the *-CHECKSUM
>> file isn't the same as the one being passed to it by the
>> avocado
On 16.04.23 21:44, Zhang, Chen wrote:
-Original Message-
From: Vladimir Sementsov-Ogievskiy
Sent: Friday, April 14, 2023 5:51 PM
To: Zhang, Chen ; qemu-devel@nongnu.org
Cc: qemu-bl...@nongnu.org; pbonz...@redhat.com; arm...@redhat.com;
ebl...@redhat.com; jasow...@redhat.com; dgilb...@
On Thu, Apr 13, 2023 at 12:14:24PM +0200, Eugenio Perez Martin wrote:
> On Wed, Apr 12, 2023 at 11:06 PM Stefan Hajnoczi wrote:
> >
> > On Tue, Apr 11, 2023 at 05:05:13PM +0200, Hanna Czenczek wrote:
> > > So-called "internal" virtio-fs migration refers to transporting the
> > > back-end's (virtio
On Mon, Apr 17, 2023 at 9:43 AM Alex Bennée wrote:
>
> From: Kautuk Consul
>
> Avocado version 101.0 has a fix to re-compute the checksum
> of an asset file if the algorithm used in the *-CHECKSUM
> file isn't the same as the one being passed to it by the
> avocado user (i.e. the avocado_qemu pyt
The run-state.json file is missing a trailing newline; add it.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
Noticed this because my editor wanted to add the newline
when I touched the file for the following patch...
---
qapi/run-state.json | 2 +-
1 file changed, 1 insertion(
The 'singlestep' HMP command is confusing, because it doesn't
actually have anything to do with single-stepping the CPU. What it
does do is force TCG emulation to put one guest instruction in each
TB, which can be useful in some situations.
Create a new HMP command 'one-insn-per-tb', so we can d
Currently we report whether the TCG accelerator is in
'one-insn-per-tb' mode in the 'info status' output. This is a pretty
minor piece of TCG specific information, and we want to deprecate the
'singlestep' field of the associated QMP command. Move the
'one-insn-per-tb' reporting to 'info jit'.
W
Document that the -singlestep command line option is now
deprecated, as it is replaced by either the TCG accelerator
property 'one-insn-per-tb' for system emulation or the new
'-one-insn-per-tb' option for usermode emulation, and remove
the only use of the deprecated syntax from a README.
Signed-o
The '-singlestep' option is confusing, because it doesn't actually
have anything to do with single-stepping the CPU. What it does do
is force TCG emulation to put one guest instruction in each TB,
which can be useful in some situations.
Create a new command line argument -one-insn-per-tb, so we ca
The HMP 'singlestep' command, the QMP 'query-status' command and the
HMP 'info status' command (which is just wrapping the QMP command
implementation) look at the 'singlestep' global variable. Make them
access the new TCG accelerator 'one-insn-per-tb' property instead.
This leaves the HMP and QMP
The only place left that looks at the old 'singlestep' global
variable is the TCG curr_cflags() function. Replace the old global
with a new 'one_insn_per_tb' which is defined in tcg-all.c and
declared in accel/tcg/internal.h. This keeps it restricted to the
TCG code, unlike 'singlestep' which was
The command line option '-singlestep' and its HMP equivalent
the 'singlestep' command are very confusingly named, because
they have nothing to do with single-stepping the guest (either
via the gdb stub or by emulation of guest CPU architectural
debug facilities). What they actually do is put TCG in
The '-singlestep' option is confusing, because it doesn't actually
have anything to do with single-stepping the CPU. What it does do
is force TCG emulation to put one guest instruction in each TB,
which can be useful in some situations.
Create a new command line argument -one-insn-per-tb, so we ca
This commit adds 'one-insn-per-tb' as a property on the TCG
accelerator object, so you can enable it with
-accel tcg,one-insn-per-tb=on
It has the same behaviour as the existing '-singlestep' command line
option. We use a different name because 'singlestep' has always been
a confusing choice,
The 'singlestep' member of StatusInfo has never done what the QMP
documentation claims it does. What it actually reports is whether
TCG is working in "one guest instruction per translation block" mode.
We no longer need this field for the HMP 'info status' command, as
we've moved that information
On Sat, Apr 15, 2023 at 04:28:25PM +0800, Jisheng Zhang wrote:
> patch1 removes CBAR from A55 and A76
> patch2 adds A78 CPU
As in another email, for various reaons I want to recall these two patches.
>
> Jisheng Zhang (2):
> target/arm: Remove ARM_FEATURE_CBAR_RO from A55 and A76
> target/ar
On Sat, Apr 15, 2023 at 04:36:55PM +0800, Jisheng Zhang wrote:
> patch1 removes CBAR from A55 and A76
> patch2 adds A78 CPU
For various reasons, I'd like to recall these two patches.
>
> Jisheng Zhang (2):
> target/arm: Remove ARM_FEATURE_CBAR_RO from A55 and A76
> target/arm: Add Cortex-A78
On 4/13/23 06:01, Weiwei Li wrote:
When PMP entry overlap part of the page, we'll set the tlb_size to 1, and
this will make the address set with TLB_INVALID_MASK to make the page
un-cached. However, if we clear TLB_INVALID_MASK when TLB is re-filled, then
the TLB host address will be cached, a
Since commit fd8171fe52b5e("target/hexagon: import lexer for idef-parser") the
hexagon target uses 'flex', 'bison' to generate idef-parser. However default
travis builder image for 'focal' may not have these pre-installed, consequently
following error is seen with travis when trying to execute the
Stefan Hajnoczi writes:
> On Fri, 14 Apr 2023 at 12:06, Alex Bennée wrote:
>>
>> A lot of our vhost-user stubs are large chunks of boilerplate that do
>> (mostly) the same thing. This series attempts to fix that by defining
>> a new base class for vhost-user devices and then converting the rng
On Thu, Apr 13, 2023 at 12:14:24PM +0200, Eugenio Perez Martin wrote:
> On Wed, Apr 12, 2023 at 11:06 PM Stefan Hajnoczi wrote:
> >
> > On Tue, Apr 11, 2023 at 05:05:13PM +0200, Hanna Czenczek wrote:
> > > So-called "internal" virtio-fs migration refers to transporting the
> > > back-end's (virtio
On Fri, Apr 14, 2023 at 05:17:02PM +0200, Eugenio Perez Martin wrote:
> On Thu, Apr 13, 2023 at 7:55 PM Hanna Czenczek wrote:
> >
> > On 13.04.23 13:38, Stefan Hajnoczi wrote:
> > > On Thu, 13 Apr 2023 at 05:24, Hanna Czenczek wrote:
> > >> On 12.04.23 23:06, Stefan Hajnoczi wrote:
> > >>> On Tue
On Thu, Apr 13, 2023 at 07:31:57PM +0200, Hanna Czenczek wrote:
> On 13.04.23 12:14, Eugenio Perez Martin wrote:
> > On Wed, Apr 12, 2023 at 11:06 PM Stefan Hajnoczi
> > wrote:
> > > On Tue, Apr 11, 2023 at 05:05:13PM +0200, Hanna Czenczek wrote:
> > > > So-called "internal" virtio-fs migration r
On Mon, Apr 17, 2023, Chao Peng wrote:
> In case you started working on the code again, I have a branch [1]
> originally planned as v11 candidate which I believe I addressed all the
> discussions we had for v10 except the very latest one [2] and integrated
> all the newly added selftests from Acker
On Tue, Jan 24, 2023 at 01:27:50AM +, Sean Christopherson wrote:
> On Thu, Jan 19, 2023, Isaku Yamahata wrote:
> > On Thu, Jan 19, 2023 at 03:25:08PM +,
> > Sean Christopherson wrote:
> >
> > > On Thu, Jan 19, 2023, Isaku Yamahata wrote:
> > > > On Sat, Jan 14, 2023 at 12:37:59AM +,
>
On Mon, Apr 17, 2023 at 10:18:08AM +, Karol Nowak wrote:
> Hi Corey,
>
>
> thank you for your response.
>
>
> Could you give me some hints how to make IO operations non-blocking in QEMU?
> Is there a code reference in the source code of QEMU I could use?
>
You can look at hw/ipmi/ipmi_bm
Mon, 17 Apr 2023 14:46:54 +0200 Peter Krempa :
> Switch the dockerfile to 15.4.
Given that Leap 15.5 is essentially done, please skip this meanwhile stale
version of Leap.
Thanks,
Olaf
pgp08kRqcL5xn.pgp
Description: Digitale Signatur von OpenPGP
On 17/04/2023 16.11, Vaibhav Jain wrote:
Hi Thomas,
Thanks for reviewing this patch. My responses inline below:
...
Travis documentation at [1] mentions clang 7.0.0 to be the default
compiler for Ubuntu 20.04 (Focal and Jammy). That is what I see in my travis
environment also with Focal.
[1] -
Hi Thomas,
Thanks for looking into this patch. My responses inline below:
Thomas Huth writes:
> On 14/04/2023 23.06, Vaibhav Jain wrote:
>> Since commit fd8171fe52b5e("target/hexagon: import lexer for idef-parser")
>> the
>> hexagon target uses 'flex' to generate idef-parser. However 'focal' m
Hi Thomas,
Thanks for reviewing this patch. My responses inline below:
Thomas Huth writes:
> On 14/04/2023 23.06, Vaibhav Jain wrote:
>> Since commit 74a1b256d775("configure: Bump minimum Clang version to 10.0")
>> qemu
>> needs Clang version 10.0 as the minimum version to build qemu with
>> C
From: Nazar Kazakov
This commit adds support for the Zvkg vector-crypto extension, which
consists of the following instructions:
* vgmul.vv
* vghsh.vv
Translation functions are defined in
`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
`target/riscv/vcrypto_helper.c`.
Co-
From: Weiwei Li
Even though Zca/Zcf/Zcd can be included by C/F/D, however, their priv
version is higher than the priv version of C/F/D. So if we use check
for them instead of check for C/F/D totally, it will trigger new
problem when we try to disable the extensions based on the configured
priv ve
From: Nazar Kazakov
This commit adds support for the Zvkned vector-crypto extension, which
consists of the following instructions:
* vaesef.[vv,vs]
* vaesdf.[vv,vs]
* vaesdm.[vv,vs]
* vaesz.vs
* vaesem.[vv,vs]
* vaeskf1.vi
* vaeskf2.vi
Translation functions are defined in
`target/riscv/insn_tra
Static CPUs don't want their extensions changed by user interaction. We
can prevent it during init by not exposing user facing properties, but
write_misa() is also capable of disabling/enabling extension during
runtime.
We have a way of telling whether a CPU is static or not by checking for
TYPE_R
From: Kiran Ostrolenk
This commit adds support for the Zvknh vector-crypto extension, which
consists of the following instructions:
* vsha2ms.vv
* vsha2c[hl].vv
Translation functions are defined in
`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
`target/riscv/vcrypto_helpe
There is no need to init timers if we're not even sure that our
extensions are valid. Execute riscv_cpu_validate_set_extensions() before
riscv_timer_init().
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: LIU Zhiwei
Reviewed-by: Weiwei Li
---
target/riscv/cpu.c | 11 ---
1 file cha
This setter is doing nothing else but setting env->vext_ver. Assign the
value directly.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: LIU Zhiwei
Reviewed-by: Weiwei Li
---
target/riscv/cpu.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/target/riscv/cpu.c b/ta
Let's remove more code that is open coded in riscv_cpu_realize() and put
it into a helper. Let's also add an error message instead of just
asserting out if env->misa_mxl_max != env->misa_mlx.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: LIU Zhiwei
Reviewed-by: Weiwei Li
---
target/riscv
Hi,
In this v7 we have three extra patches:
- patch 4 [1] and 5 [2], both from Weiwei Li, addresses an issue that
we're going to have with Zca and RVC if we push the priv spec
disabling code to the end of validation. More details can be seen on
[3]. Patch 5 commit message also has some context o
The RVV verification will error out if fails and it's being done at the
end of riscv_cpu_validate_set_extensions(), after we've already set some
extensions that are dependent on RVV. Let's put it in its own function
and do it earlier.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: LIU Zhiwe
The setter is doing nothing special. Just set env->priv_ver directly.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: LIU Zhiwei
Reviewed-by: Weiwei Li
---
target/riscv/cpu.c | 29 -
1 file changed, 12 insertions(+), 17 deletions(-)
diff --git a/target/riscv/cp
From: Kiran Ostrolenk
This is for use in the RISC-V vclz and vctz instructions (implemented in
proceeding commit).
Signed-off-by: Kiran Ostrolenk
---
include/qemu/host-utils.h | 54 +++
1 file changed, 54 insertions(+)
diff --git a/include/qemu/host-utils.h
We have 4 config settings being done in riscv_cpu_init(): ext_ifencei,
ext_icsr, mmu and pmp. This is also the constructor of the "riscv-cpu"
device, which happens to be the parent device of every RISC-V cpu.
The result is that these 4 configs are being set every time, and every
other CPU should a
From: Nazar Kazakov
Move the checks out of `do_opiv{v,x,i}_gvec{,_shift}` functions
and into the corresponding macros. This enables the functions to be
reused in proceeding commits without check duplication.
Signed-off-by: Nazar Kazakov
---
target/riscv/insn_trans/trans_rvv.c.inc | 28
All these generic CPUs are using the latest priv available, at this
moment PRIV_VERSION_1_12_0:
- riscv_any_cpu_init()
- rv32_base_cpu_init()
- rv64_base_cpu_init()
- rv128_base_cpu_init()
Create a new PRIV_VERSION_LATEST enum and use it in those cases. I'll
make it easier to update everything at
From: Nazar Kazakov
Signed-off-by: Nazar Kazakov
---
target/riscv/cpu.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 3b754d7e13b..2f71d612725 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1485,6 +1485,16 @@ static P
This commit adds support for the Zvksh vector-crypto extension, which
consists of the following instructions:
* vsm3me.vv
* vsm3c.vi
Translation functions are defined in
`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
`target/riscv/vcrypto_helper.c`.
Co-authored-by: Kiran O
From: Max Chou
- Share sm4_subword between different targets.
Signed-off-by: Max Chou
Reviewed-by: Frank Chang
---
include/crypto/sm4.h | 8
target/arm/tcg/crypto_helper.c | 10 ++
2 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/include/crypto/s
From: Dickon Hood
This commit adds support for the Zvbc vector-crypto extension, which
consists of the following instructions:
* vrol.[vv,vx]
* vror.[vv,vx,vi]
* vbrev8.v
* vrev8.v
* vandn.[vv,vx]
* vbrev.v
* vclz.v
* vctz.v
* vcpop.v
* vswll.[vv,vx,vi]
Translation functions are defined in
`tar
This commit adds support for the Zvbc vector-crypto extension, which
consists of the following instructions:
* vclmulh.[vx,vv]
* vclmul.[vx,vv]
Translation functions are defined in
`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
`target/riscv/vcrypto_helper.c`.
Co-authored-
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