[PATCH RFC v3 1/9] linux-headers: Add KVM headers for loongarch

This patch is only a placeholder now, which is used to show some kvm structures and macros for reviewers. And it will be replaced by using update-linux-headers.sh when the linux loongarch kvm patches are accepted. Signed-off-by: Tianrui Zhao --- linux-headers/asm-loongarch/kvm.h | 99

[PATCH RFC v3 4/9] target/loongarch: Implement kvm get/set registers

Implement kvm_arch_get/set_registers interfaces, many regs can be get/set in the function, such as core regs, csr regs, fpu regs, mp state, etc. Signed-off-by: Tianrui Zhao Reviewed-by: Richard Henderson --- meson.build | 1 + target/loongarch/cpu.c| 3 +

[PATCH RFC v3 8/9] target/loongarch: Implement set vcpu intr for kvm

Implement loongarch kvm set vcpu interrupt interface, when a irq is set in vcpu, we use the KVM_INTERRUPT ioctl to set intr into kvm. Signed-off-by: Tianrui Zhao --- target/loongarch/cpu.c | 18 +- target/loongarch/kvm-stub.c | 11 +++

[PATCH RFC v3 9/9] target/loongarch: Add loongarch kvm into meson build

Add kvm.c and kvm-stub.c into meson.build to compile it when kvm is configed. Meanwhile in meson.build, we set the kvm_targets to loongarch64-softmmu when the cpu is loongarch. Signed-off-by: Tianrui Zhao Reviewed-by: Richard Henderson --- meson.build | 2 ++

Re: [PATCH] virtio-net: not enable vq reset feature unconditionally

On Thu, 4 May 2023 12:14:47 +0200, =?utf-8?q?Eugenio_P=C3=A9rez?= wrote: > The commit 93a97dc5200a ("virtio-net: enable vq reset feature") enables > unconditionally vq reset feature as long as the device is emulated. > This makes impossible to actually disable the feature, and it causes >

[PATCH RFC v3 7/9] target/loongarch: Implement kvm_arch_handle_exit

Implement kvm_arch_handle_exit for loongarch. In this function, the KVM_EXIT_LOONGARCH_IOCSR is handled, we read or write the iocsr address space by the addr, length and is_write argument in kvm_run. Signed-off-by: Tianrui Zhao Reviewed-by: Richard Henderson --- target/loongarch/kvm.c|

[PATCH RFC v3 0/9] Add loongarch kvm accel support

This series add loongarch kvm support, mainly implement some interfaces used by kvm such as kvm_arch_get/set_regs, kvm_arch_handle_exit, kvm_loongarch_set_interrupt, etc. Currently, we are able to boot LoongArch KVM Linux Guests. In loongarch VM, mmio devices and iocsr devices are emulated in

[PATCH RFC v3 3/9] target/loongarch: Supplement vcpu env initial when vcpu reset

Supplement vcpu env initial when vcpu reset, including init vcpu CSR_CPUID,CSR_TID to cpu->cpu_index. The two regs will be used in kvm_get/set_csr_ioctl. Signed-off-by: Tianrui Zhao --- target/loongarch/cpu.c | 2 ++ target/loongarch/cpu.h | 1 + 2 files changed, 3 insertions(+) diff --git

[PATCH RFC v3 5/9] target/loongarch: Implement kvm_arch_init function

Implement the kvm_arch_init of loongarch, in the function, the KVM_CAP_MP_STATE cap is checked by kvm ioctl. Signed-off-by: Tianrui Zhao Reviewed-by: Richard Henderson --- target/loongarch/kvm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/loongarch/kvm.c b/target/loongarch/kvm.c

[PATCH RFC v3 6/9] target/loongarch: Implement kvm_arch_init_vcpu

Implement kvm_arch_init_vcpu interface for loongarch, in this function, we register VM change state handler. And when VM state changes to running, the counter value should be put into kvm to keep consistent with kvm, and when state change to stop, counter value should be refreshed from kvm.

[PATCH RFC v3 2/9] target/loongarch: Define some kvm_arch interfaces

Define some functions in target/loongarch/kvm.c, such as kvm_arch_put_registers, kvm_arch_get_registers and kvm_arch_handle_exit, etc. which are needed by kvm/kvm-all.c. Now the most functions has no content and they will be implemented in the next patches. Signed-off-by: Tianrui Zhao

Re: [PATCH v4 36/57] tcg/loongarch64: Assert the host supports unaligned accesses

Hi, 在 2023/5/5 下午9:24, WANG Xuerui 写道: Hi, On 2023/5/3 15:06, Richard Henderson wrote: This should be true of all server class loongarch64. And desktop-class (i.e. all Loongson-3 series). Signed-off-by: Richard Henderson ---   tcg/loongarch64/tcg-target.c.inc | 6 ++   1 file changed,

Re: [PULL 00/45] loongarch-to-apply queue

in the Git repository at:    https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20230505 for you to fetch changes up to 9dd207d409cc2eb08fe52965b9d1fd4a12a82bd5:    hw/intc: don't use target_ulong for LoongArch ipi (2023-05-05 10:00:47 +0800

Re: [PATCH 0/1] Updated: Ensure PV ring is drained on disconenct

On Thu, 20 Apr 2023, Mark Syms wrote: > Updated patch to address intermittent SIGSEGV on domain disconnect/shutdown. > > Mark Syms (1): > Ensure the PV ring is drained on disconnect > > hw/block/dataplane/xen-block.c | 31 +-- > 1 file changed, 25 insertions(+), 6

Re: [PATCH] 9pfs/xen: Fix segfault on shutdown

On Tue, 2 May 2023, Jason Andryuk wrote: > xen_9pfs_free can't use gnttabdev since it is already closed and NULL-ed > out when free is called. Do the teardown in _disconnect(). This > matches the setup done in _connect(). > > trace-events are also added for the XenDevOps functions. > >

[PATCH v2] vfio/pci: Static Resizable BAR capability

The PCI Resizable BAR (ReBAR) capability is currently hidden from the VM because the protocol for interacting with the capability does not support a mechanism for the device to reject an advertised supported BAR size. However, when assigned to a VM, the act of resizing the BAR requires adjustment

Question: PCIe P2P Guidance

Hi, I have been struggling for a few months now with achieving full bandwidth PCIe P2P in a qemu virtual machine. I am working with a number of PCIe endpoints (NVIDIA A100 GPUs and Mellanox ConnectX 7 Infiniband NICs) behind a PCIe switch. In all configurations I have tried, P2P traffic gets

Re: [PATCH v3 0/3] ACPI: i386: bump MADT to revision 5

Thoughts? eric On 4/21/23 16:48, Eric DeVolder wrote: The following Linux kernel change broke CPU hotplug for MADT revision less than 5. e2869bd7af60 ("x86/acpi/boot: Do not register processors that cannot be onlined for x2APIC") Discussion on this topic can be located here:

[PULL 19/42] tcg/i386: Rationalize args to tcg_out_qemu_{ld,st}

Interpret the variable argument placement in the caller. Pass data_type instead of is64 -- there are several places where we already convert back from bool to type. Clean things up by using type throughout. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson ---

[PULL 30/42] tcg/mips: Rationalize args to tcg_out_qemu_{ld,st}

Interpret the variable argument placement in the caller. There are several places where we already convert back from bool to type. Clean things up by using type throughout. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 186

[PULL 41/42] tcg: Introduce arg_slot_stk_ofs

Unify all computation of argument stack offset in one function. This requires that we adjust ref_slot to be in the same units, by adding max_reg_slots during init_call_layout. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tcg.c | 29 +

[PULL 27/42] tcg/arm: Introduce HostAddress

Collect the parts of the host address, and condition, into a struct. Merge tcg_out_qemu_*_{index,direct} and use it. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 248 ++- 1 file changed, 115 insertions(+), 133 deletions(-) diff --git

[PULL 17/42] target/sparc: Use cpu_ld*_code_mmu

This passes on the memop as given as argument to helper_ld_asi to the ultimate load primitive. Reviewed-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/ldst_helper.c | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/sparc/ldst_helper.c

[PULL 11/42] target/alpha: Use MO_ALIGN for system UNALIGN()

Signed-off-by: Richard Henderson --- target/alpha/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 9d25e21164..ffbac1c114 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -72,7 +72,7

[PULL 40/42] tcg: Replace REG_P with arg_loc_reg_p

An inline function is safer than a macro, and REG_P was rather too generic. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tcg-internal.h | 4 tcg/tcg.c | 16 +--- 2 files changed, 13 insertions(+), 7 deletions(-) diff --git

[PULL 26/42] tcg/arm: Rationalize args to tcg_out_qemu_{ld,st}

Interpret the variable argument placement in the caller. Pass data_type instead of is_64. We need to set this in TCGLabelQemuLdst, so plumb this all the way through from tcg_out_op. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 113

[PULL 12/42] target/alpha: Use MO_ALIGN where required

Mark all memory operations that are not already marked with UNALIGN. Signed-off-by: Richard Henderson --- target/alpha/translate.c | 36 1 file changed, 20 insertions(+), 16 deletions(-) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index

[PULL 22/42] tcg/i386: Drop r0+r1 local variables from tcg_out_tlb_load

Use TCG_REG_L[01] constants directly. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 32 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc

[PULL 42/42] tcg: Widen helper_*_st[bw]_mmu val arguments

While the old type was correct in the ideal sense, some ABIs require the argument to be zero-extended. Using uint32_t for all such values is a decent compromise. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg-ldst.h | 10 +++--- accel/tcg/cputlb.c

[PULL 14/42] target/hppa: Use MO_ALIGN for system UNALIGN()

Signed-off-by: Richard Henderson --- target/hppa/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 6a3154ebc6..59e4688bfa 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -271,7 +271,7 @@

[PULL 34/42] tcg/riscv: Rationalize args to tcg_out_qemu_{ld,st}

Interpret the variable argument placement in the caller. Pass data_type instead of is64 -- there are several places where we already convert back from bool to type. Clean things up by using type throughout. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Daniel Henrique Barboza

[PULL 23/42] tcg/i386: Introduce tcg_out_testi

Split out a helper for choosing testb vs testl. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 30 ++ 1 file changed, 18 insertions(+), 12 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc

[PULL 02/42] target/avr: Finish conversion to tcg_gen_qemu_{ld,st}_*

Convert away from the old interface with the implicit MemOp argument. Signed-off-by: Richard Henderson Reviewed-by: Anton Johansson Message-Id: <20230502135741.1158035-2-richard.hender...@linaro.org> --- target/avr/translate.c | 16 1 file changed, 8 insertions(+), 8

[PULL 06/42] target/mips: Finish conversion to tcg_gen_qemu_{ld, st}_*

Convert away from the old interface with the implicit MemOp argument. Signed-off-by: Richard Henderson Reviewed-by: Anton Johansson Message-Id: <20230502135741.1158035-6-richard.hender...@linaro.org> --- target/mips/tcg/translate.c | 8

[PULL 28/42] tcg/loongarch64: Rationalize args to tcg_out_qemu_{ld, st}

Interpret the variable argument placement in the caller. Shift some code around slightly to share more between softmmu and user-only. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 100 +-- 1 file

[PULL 25/42] tcg/aarch64: Introduce HostAddress

Collect the 3 potential parts of the host address into a struct. Reorg tcg_out_qemu_{ld,st}_direct to use it. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 86 +--- 1 file changed, 59 insertions(+), 27

[PULL 32/42] tcg/ppc: Introduce HostAddress

Collect the parts of the host address into a struct. Reorg tcg_out_qemu_{ld,st} to use it. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 90 +--- 1 file changed, 47 insertions(+), 43 deletions(-) diff

[PULL 13/42] target/alpha: Remove TARGET_ALIGNED_ONLY

Signed-off-by: Richard Henderson --- configs/targets/alpha-linux-user.mak | 1 - configs/targets/alpha-softmmu.mak| 1 - 2 files changed, 2 deletions(-) diff --git a/configs/targets/alpha-linux-user.mak b/configs/targets/alpha-linux-user.mak index 7e62fd796a..f7d3fb4afa 100644 ---

[PULL 21/42] tcg/i386: Introduce HostAddress

Collect the 4 potential parts of the host address into a struct. Reorg tcg_out_qemu_{ld,st}_direct to use it. Reorg guest_base handling to use it. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 165 +- 1

[PULL 03/42] target/cris: Finish conversion to tcg_gen_qemu_{ld, st}_*

Convert away from the old interface with the implicit MemOp argument. In this case we can fold the calls using the size bits of MemOp. Signed-off-by: Richard Henderson Reviewed-by: Anton Johansson Message-Id: <20230502135741.1158035-3-richard.hender...@linaro.org> ---

[PULL 31/42] tcg/ppc: Rationalize args to tcg_out_qemu_{ld,st}

Interpret the variable argument placement in the caller. Pass data_type instead of is64 -- there are several places where we already convert back from bool to type. Clean things up by using type throughout. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Daniel Henrique Barboza

[PULL 01/42] softfloat: Fix the incorrect computation in float32_exp2

From: Shivaprasad G Bhat The float32_exp2 function is computing wrong exponent of 2. For example, with the following set of values {0.1, 2.0, 2.0, -1.0}, the expected output would be {1.071773, 4.00, 4.00, 0.50}. Instead, the function is computing {1.119102, 3.382044, 3.382044,

[PULL 39/42] tcg: Move TCGLabelQemuLdst to tcg.c

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tcg.c | 13 + tcg/tcg-ldst.c.inc | 14 -- 2 files changed, 13 insertions(+), 14 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index cfd3262a4a..6f5daaee5f 100644 --- a/tcg/tcg.c +++

[PULL 35/42] tcg/s390x: Pass TCGType to tcg_out_qemu_{ld,st}

We need to set this in TCGLabelQemuLdst, so plumb this all the way through from tcg_out_op. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 22 ++ 1 file changed, 14 insertions(+), 8 deletions(-) diff --git

[PULL 36/42] tcg/s390x: Introduce HostAddress

Collect the 3 potential parts of the host address into a struct. Reorg tcg_out_qemu_{ld,st}_direct to use it. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 109 - 1 file changed, 60 insertions(+), 49

[PULL 38/42] tcg/sparc64: Pass TCGType to tcg_out_qemu_{ld,st}

We need to set this in TCGLabelQemuLdst, so plumb this all the way through from tcg_out_op. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/sparc64/tcg-target.c.inc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git

[PULL 24/42] tcg/aarch64: Rationalize args to tcg_out_qemu_{ld,st}

Rename the 'ext' parameter 'data_type' to make the use clearer; pass it to tcg_out_qemu_st as well to even out the interfaces. Rename the 'otype' local 'addr_type' to make the use clearer. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc |

[PULL 29/42] tcg/loongarch64: Introduce HostAddress

Collect the 2 parts of the host address into a struct. Reorg tcg_out_qemu_{ld,st}_direct to use it. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 55 +--- 1 file changed, 30 insertions(+), 25 deletions(-)

[PULL 00/42] tcg patch queue

The following changes since commit a9fe9e191b4305b88c356a1ed9ac3baf89eb18aa: Merge tag 'pull-riscv-to-apply-20230505-1' of https://github.com/alistair23/qemu into staging (2023-05-05 09:25:13 +0100) are available in the Git repository at: https://gitlab.com/rth7680/qemu.git tags/pull-tcg

[PULL 04/42] target/Hexagon: Finish conversion to tcg_gen_qemu_{ld, st}_*

Convert away from the old interface with the implicit MemOp argument. Importantly, this removes some incorrect casts generated by idef-parser's gen_load(). Signed-off-by: Richard Henderson Tested-by: Taylor Simpson Reviewed-by: Taylor Simpson Reviewed-by: Anton Johansson Message-Id:

[PULL 20/42] tcg/i386: Generalize multi-part load overlap test

Test for both base and index; use datahi as a temporary, overwritten by the final load. Always perform the loads in ascending order, so that any (user-only) fault sees the correct address. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 31 +++ 1

[PULL 08/42] target/sparc: Finish conversion to tcg_gen_qemu_{ld, st}_*

Convert away from the old interface with the implicit MemOp argument. Signed-off-by: Richard Henderson Reviewed-by: Anton Johansson Message-Id: <20230502135741.1158035-8-richard.hender...@linaro.org> --- target/sparc/translate.c | 43 ++-- 1 file changed, 28

[PULL 18/42] target/sparc: Remove TARGET_ALIGNED_ONLY

Reviewed-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- configs/targets/sparc-linux-user.mak | 1 - configs/targets/sparc-softmmu.mak | 1 - configs/targets/sparc32plus-linux-user.mak | 1 - configs/targets/sparc64-linux-user.mak | 1 -

[PULL 09/42] target/xtensa: Finish conversion to tcg_gen_qemu_{ld, st}_*

Convert away from the old interface with the implicit MemOp argument. Signed-off-by: Richard Henderson Reviewed-by: Max Filippov Message-Id: <20230502135741.1158035-9-richard.hender...@linaro.org> --- target/xtensa/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff

[PULL 15/42] target/hppa: Remove TARGET_ALIGNED_ONLY

Signed-off-by: Richard Henderson --- configs/targets/hppa-linux-user.mak | 1 - configs/targets/hppa-softmmu.mak| 1 - 2 files changed, 2 deletions(-) diff --git a/configs/targets/hppa-linux-user.mak b/configs/targets/hppa-linux-user.mak index db873a8796..361ea39d71 100644 ---

[PULL 10/42] tcg: Remove compatability helpers for qemu ld/st

Remove the old interfaces with the implicit MemOp argument. Signed-off-by: Richard Henderson Acked-by: David Hildenbrand Message-Id: <20230502135741.1158035-10-richard.hender...@linaro.org> --- include/tcg/tcg-op.h | 55 1 file changed, 55

[PULL 33/42] tcg/riscv: Require TCG_TARGET_REG_BITS == 64

The port currently does not support "oversize" guests, which means riscv32 can only target 32-bit guests. We will soon be building TCG once for all guests. This implies that we can only support riscv64. Since all Linux distributions target riscv64 not riscv32, this is not much of a restriction

[PULL 37/42] tcg/sparc64: Drop is_64 test from tcg_out_qemu_ld data return

In tcg_canonicalize_memop, we remove MO_SIGN from MO_32 operations with TCG_TYPE_I32. Thus this is never set. We already have an identical test just above which does not include is_64 Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/sparc64/tcg-target.c.inc | 2 +-

[PULL 16/42] target/sparc: Use MO_ALIGN where required

Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/translate.c | 66 +--- 1 file changed, 34 insertions(+), 32 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index bc71e44e66..414e014b11 100644 ---

[PULL 05/42] target/m68k: Finish conversion to tcg_gen_qemu_{ld, st}_*

Convert away from the old interface with the implicit MemOp argument. Signed-off-by: Richard Henderson Reviewed-by: Anton Johansson Message-Id: <20230502135741.1158035-5-richard.hender...@linaro.org> --- target/m68k/translate.c | 76 ++--- 1 file changed, 25

[PULL 07/42] target/s390x: Finish conversion to tcg_gen_qemu_{ld, st}_*

Convert away from the old interface with the implicit MemOp argument. Signed-off-by: Richard Henderson Reviewed-by: David Hildenbrand Reviewed-by: Ilya Leoshkevich Message-Id: <20230502135741.1158035-7-richard.hender...@linaro.org> --- target/s390x/tcg/translate.c | 152

Re: [PULL 0/1] audio patch

On 5/5/23 12:39, marcandre.lur...@redhat.com wrote: From: Marc-André Lureau The following changes since commit f6b761bdbd8ba63cee7428d52fb6b46e4224ddab: Merge tag 'qga-pull-2023-05-04' ofhttps://github.com/kostyanf14/qemu into staging (2023-05-04 12:08:00 +0100) are available in the Git

Re: [PULL 00/16] Migration 20230505 patches

/juan.quintela/qemu.git tags/migration-20230505-pull-request for you to fetch changes up to fae4009fb51b12927165667a9c9d6af93d31b1df: qemu-file: Make ram_control_save_page() use accessors for rate_limit (2023-05-05 02:01:59 +0200

Re: [Qemu-devel] [PATCH v4 21/24] target-sparc: Use explicit writes to cpu_fsr

Re: [PATCH v2 3/5] hw/display/virtio-gpu-virgl: define callbacks in realize function

On Fri, May 5, 2023 at 10:48 AM Bernhard Beschow wrote: > Am 1. Mai 2023 16:53:03 UTC schrieb Gurchetan Singh < > gurchetansi...@chromium.org>: > >On Sun, Apr 30, 2023 at 2:48 PM Bernhard Beschow > wrote: > > > >> > >> > >> Am 28. April 2023 16:48:21 UTC schrieb Gurchetan Singh < > >>

[PATCH] accel/tcg: Fix atomic_mmu_lookup for reads

A copy-paste bug had us looking at the victim cache for writes. Reported-by: Peter Maydell Signed-off-by: Richard Henderson --- To be inserted before patch 3 in https://lore.kernel.org/qemu-devel/45cba357-ba20-399a-27e6-5e9974117...@linaro.org/T/#m5dc55cf04d564f4a8f97bc95e7f0e427c24a4f0b r~

Re: [PATCH v4 06/57] accel/tcg: Honor atomicity of loads

On 5/4/23 18:17, Peter Maydell wrote: +case MO_ATOM_SUBALIGN: +tmp = p & -p; +if (tmp != 0 && tmp < atmax) { +atmax = tmp; +} +break; I don't understand the bit manipulation going on here. AIUI what we're trying to do is say "if e.g. p is only

RE: [PATCH 0/2] Hexagon: improve output for arch version debugging

> -Original Message- > From: Matheus Tavares Bernardino > Sent: Thursday, May 4, 2023 1:53 PM > To: qemu-devel@nongnu.org > Cc: Brian Cain ; Taylor Simpson > > Subject: [PATCH 0/2] Hexagon: improve output for arch version debugging > > If we run qemu with an Hexagon binary compiled

RE: [PATCH 1/2] Hexagon: list available CPUs with `-cpu help`

> -Original Message- > From: Matheus Tavares Bernardino > Sent: Thursday, May 4, 2023 1:53 PM > To: qemu-devel@nongnu.org > Cc: Brian Cain ; Taylor Simpson > > Subject: [PATCH 1/2] Hexagon: list available CPUs with `-cpu help` > > Currently, qemu-hexagon only models the v67 cpu.

RE: [PATCH 2/2] Hexagon: append eflags to unknown cpu model string

> -Original Message- > From: Matheus Tavares Bernardino > Sent: Thursday, May 4, 2023 1:53 PM > To: qemu-devel@nongnu.org > Cc: Brian Cain ; Taylor Simpson > ; Laurent Vivier > Subject: [PATCH 2/2] Hexagon: append eflags to unknown cpu model string > > Running qemu-hexagon with a

Re: [PATCH v4 03/57] accel/tcg: Introduce tlb_read_idx

On 5/4/23 16:02, Peter Maydell wrote: On Wed, 3 May 2023 at 08:15, Richard Henderson wrote: Instead of playing with offsetof in various places, use MMUAccessType to index an array. This is easily defined instead of the previous dummy padding array in the union. Reviewed-by: Alex Bennée

Re: [PATCH v3 10/10] accel/tcg: include cs_base in our hash calculations

On 5/5/23 16:53, Alex Bennée wrote: + uint32_t flags, uint64_t flags2, uint32_t cf_mask) { -return qemu_xxhash6(phys_pc, pc, flags, cf_mask); +return qemu_xxhash8(phys_pc, pc, flags, +flags2 & 0x, flags2 >> 32, cf_mask); Well not that

Re: [PULL 00/45] loongarch-to-apply queue

/gaosong/qemu.git tags/pull-loongarch-20230505 for you to fetch changes up to 9dd207d409cc2eb08fe52965b9d1fd4a12a82bd5: hw/intc: don't use target_ulong for LoongArch ipi (2023-05-05 10:00:47 +0800) Add LoongArch LSX instructions

Re: [PATCH v2 3/5] hw/display/virtio-gpu-virgl: define callbacks in realize function

Am 1. Mai 2023 16:53:03 UTC schrieb Gurchetan Singh : >On Sun, Apr 30, 2023 at 2:48 PM Bernhard Beschow wrote: > >> >> >> Am 28. April 2023 16:48:21 UTC schrieb Gurchetan Singh < >> gurchetansi...@chromium.org>: >> >From: Gurchetan Singh >> > >> >This reduces the amount of renderer backend

RE: [PATCH] Hexagon (decode): look for pkts with multiple insns at the same slot

> -Original Message- > From: Matheus Tavares Bernardino > Sent: Thursday, May 4, 2023 1:57 PM > To: qemu-devel@nongnu.org > Cc: Taylor Simpson > Subject: [PATCH] Hexagon (decode): look for pkts with multiple insns at the > same slot > > Each slot in a packet can be assigned to at

Re: [PATCH v1 2/9] KVM: x86/mmu: Add support for prewrite page tracking

On Fri, May 05, 2023, Micka�l Sala�n wrote: > > On 05/05/2023 18:28, Sean Christopherson wrote: > > I have no doubt that we'll need to solve performance and scaling issues > > with the > > memory attributes implementation, e.g. to utilize xarray multi-range support > > instead of storing

Re: [PATCH v1 4/9] KVM: x86: Add new hypercall to set EPT permissions

On Fri, May 05, 2023, Micka�l Sala�n wrote: > > On 05/05/2023 18:44, Sean Christopherson wrote: > > On Fri, May 05, 2023, Micka�l Sala�n wrote: > > > Add a new KVM_HC_LOCK_MEM_PAGE_RANGES hypercall that enables a guest to > > > set EPT permissions on a set of page ranges. > > > > IMO,

RE: [PATCH v4 0/7] Add EPYC-Genoa model and update previous EPYC Models

[AMD Official Use Only - General] > -Original Message- > From: Paolo Bonzini > Sent: Friday, May 5, 2023 3:31 AM > To: Moger, Babu > Cc: pbonz...@redhat.com; richard.hender...@linaro.org; > weijiang.y...@intel.com; phi...@linaro.org; d...@amazon.co.uk; > p...@xen.org;

Re: [PATCH v1 4/9] KVM: x86: Add new hypercall to set EPT permissions

On 05/05/2023 18:44, Sean Christopherson wrote: On Fri, May 05, 2023, Micka�l Sala�n wrote: Add a new KVM_HC_LOCK_MEM_PAGE_RANGES hypercall that enables a guest to set EPT permissions on a set of page ranges. IMO, manipulation of protections, both for memory (this patch) and CPU state

RE: [PATCH] Hexagon (target/hexagon/*.py): raise exception on reg parsing error

> -Original Message- > From: Matheus Tavares Bernardino > Sent: Thursday, May 4, 2023 11:18 AM > To: qemu-devel@nongnu.org > Cc: a...@rev.ng; Taylor Simpson ; a...@rev.ng > Subject: [PATCH] Hexagon (target/hexagon/*.py): raise exception on reg > parsing error > > Currently, the python

Re: [PATCH v1 2/9] KVM: x86/mmu: Add support for prewrite page tracking

On 05/05/2023 18:28, Sean Christopherson wrote: On Fri, May 05, 2023, Micka�l Sala�n wrote: diff --git a/arch/x86/include/asm/kvm_page_track.h b/arch/x86/include/asm/kvm_page_track.h index eb186bc57f6a..a7fb4ff888e6 100644 --- a/arch/x86/include/asm/kvm_page_track.h +++

Re: [PATCH v1 4/9] KVM: x86: Add new hypercall to set EPT permissions

On Fri, May 05, 2023, Micka�l Sala�n wrote: > Add a new KVM_HC_LOCK_MEM_PAGE_RANGES hypercall that enables a guest to > set EPT permissions on a set of page ranges. IMO, manipulation of protections, both for memory (this patch) and CPU state (control registers in the next patch) should come

[PULL 3/6] MAINTAINERS: Adding myself in the list for ppc/spapr

From: Harsh Prateek Bora Would like to get notified of changes in this area and review them. Signed-off-by: Harsh Prateek Bora Reviewed-by: Daniel Henrique Barboza Message-Id: <20230503093619.2530487-3-hars...@linux.ibm.com> Signed-off-by: Daniel Henrique Barboza --- MAINTAINERS | 1 + 1

[PULL 0/6] ppc queue

The following changes since commit a9fe9e191b4305b88c356a1ed9ac3baf89eb18aa: Merge tag 'pull-riscv-to-apply-20230505-1' of https://github.com/alistair23/qemu into staging (2023-05-05 09:25:13 +0100) are available in the Git repository at: https://gitlab.com/danielhb/qemu.git tags/pull-ppc

[PULL 5/6] tests: tcg: ppc64: Add tests for Vector Extract Mask Instructions

From: Shivaprasad G Bhat Add test for vextractbm, vextractwm, vextractdm and vextractqm instructions. Test works for both qemu-ppc64 and qemu-ppc64le. Based on the test case written by John Platts posted at [1] References: [1] - https://gitlab.com/qemu-project/qemu/-/issues/1536

[PULL 2/6] ppc: spapr: cleanup cr get/set with helpers.

From: Harsh Prateek Bora The bits in cr reg are grouped into eight 4-bit fields represented by env->crf[8] and the related calculations should be abstracted to keep the calling routines simpler to read. This is a step towards cleaning up the related/calling code for better readability.

[PULL 4/6] tcg: ppc64: Fix mask generation for vextractdm

From: Shivaprasad G Bhat In function do_extractm() the mask is calculated as dup_const(1 << (element_width - 1)). '1' being signed int works fine for MO_8,16,32. For MO_64, on PPC64 host this ends up becoming 0 on compilation. The vextractdm uses MO_64, and it ends up having mask as 0.

[PULL 1/6] hw/display/sm501: Remove unneeded increment from loop

From: BALATON Zoltan As Coverity points out (CID 1508621) the calculation to increment i in the fill fallback loop is ineffective as it is overwritten in next statement. This was left there by mistake from a previous version but is not needed in the current approach so remove the superfluous

[PULL 6/6] hw/ppc/Kconfig: NVDIMM is a hard requirement for the pseries machine

From: Thomas Huth When building QEMU with "--without-default-devices", the pseries machine fails to start even when running with the --nodefaults option: $ ./qemu-system-ppc64 --nodefaults -M pseries Type 'spapr-nvdimm' is missing its parent 'nvdimm' Aborted (core dumped) Looks like NVDIMM

Re: [PATCH v1 2/9] KVM: x86/mmu: Add support for prewrite page tracking

On Fri, May 05, 2023, Micka�l Sala�n wrote: > diff --git a/arch/x86/include/asm/kvm_page_track.h > b/arch/x86/include/asm/kvm_page_track.h > index eb186bc57f6a..a7fb4ff888e6 100644 > --- a/arch/x86/include/asm/kvm_page_track.h > +++ b/arch/x86/include/asm/kvm_page_track.h > @@ -3,6 +3,7 @@ >

Re: [PTACH v2 1/6] update-linux-headers: sync-up header with Linux for KVM AIA support

On Fri, 5 May 2023 11:39:36 + Yong-Xuan Wang wrote: > Update the linux headers to get the latest KVM RISC-V headers with AIA support > by the scripts/update-linux-headers.sh. > The linux headers is comes from the riscv_aia_v1 branch available at > https://github.com/avpatel/linux.git. It

Re: [PATCH] target/ppc: Fix nested-hv HEAI delivery

On Fri, 5 May 2023, Nicholas Piggin wrote: ppc hypervisors turn HEAI interrupts into program interrupts injected into the guest that executed the illegal instruction, if the hypervisor doesn't handle it some other way. The nexted-hv implementation failed to account for this HEAI->program

Re: [PATCH 0/9] tcg: Remove compatability helpers for qemu ld/st

On 5/2/23 14:57, Richard Henderson wrote: Finishing this conversion has been a long time coming. This is a prerequisite to removing TARGET_ALIGNED_ONLY, which in turn is a prerequiste to building TCG once. r~ Richard Henderson (9): target/avr: Finish conversion to tcg_gen_qemu_{ld,st}_*

Re: [PATCH] vfio/pci: Static Resizable BAR capability

On Fri, 5 May 2023 10:29:36 +0200 Cédric Le Goater wrote: > On 5/4/23 22:42, Alex Williamson wrote: > > The PCI Resizable BAR (ReBAR) capability is currently hidden from the > > VM because the protocol for interacting with the capability does not > > support a mechanism for the device to reject

[PATCH v3 01/10] *-user: remove the guest_user_syscall tracepoints

This is pure duplication now. Both bsd-user and linux-user have builtin strace support and we can also track syscalls via the plugins system. Message-Id: <20230420150009.1675181-2-alex.ben...@linaro.org> Reviewed-by: Warner Losh Reviewed-by: Stefan Hajnoczi Reviewed-by: Richard Henderson

[PATCH v3 07/10] trace: remove control-vcpu.h

Now we no longer have vcpu controlled trace events we can excise the code that allows us to query its status. Message-Id: <20230420150009.1675181-8-alex.ben...@linaro.org> Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Stefan Hajnoczi Reviewed-by: Richard Henderson Signed-off-by: Alex Bennée

[PATCH v3 00/10] tracing: remove dynamic vcpu state

Hi Stefan, The references dynamic vcpu tracing support was removed when the original TCG trace points where removed. However there was still a legacy of dynamic trace state to track this in cpu.h and extra hash variables to track TBs. While the removed vcpu tracepoints are not in generated code

[PATCH v3 10/10] accel/tcg: include cs_base in our hash calculations

We weren't using cs_base in the hash calculations before. Since the arm front end moved a chunk of flags in a378206a20 (target/arm: Move mode specific TB flags to tb->cs_base) they comprise of an important part of the execution state. Widen the tb_hash_func to include cs_base and expand to

[PATCH v3 08/10] tcg: remove the final vestiges of dstate

Now we no longer have dynamic state affecting things we can remove the additional fields in cpu.h and simplify the TB hash calculation. For the benchmark: hyperfine -w 2 -m 20 \ "./arm-softmmu/qemu-system-arm -cpu cortex-a15 \ -machine type=virt,highmem=off \ -display

[PATCH v3 03/10] trace: remove vcpu_id from the TraceEvent structure

This does involve temporarily stubbing out some helper functions before we excise the rest of the code. Message-Id: <20230420150009.1675181-4-alex.ben...@linaro.org> Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Stefan Hajnoczi Reviewed-by: Richard Henderson Signed-off-by: Alex Bennée

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