On Mon, May 15, 2023 at 03:52:29PM +0300, Vladimir Sementsov-Ogievskiy wrote:
> On incoming migration we have the following sequence to load option
> ROM:
>
> 1. On device realize we do normal load ROM from the file
>
> 2. Than, on incoming migration we rewrite ROM from the incoming RAM
>
On Thu, May 18, 2023 at 11:23 PM Michael S. Tsirkin wrote:
>
> On Thu, May 18, 2023 at 08:36:22AM +0200, Eugenio Perez Martin wrote:
> > On Thu, May 18, 2023 at 7:50 AM Jason Wang wrote:
> > >
> > > On Wed, May 17, 2023 at 2:30 PM Eugenio Perez Martin
> > > wrote:
> > > >
> > > > On Wed, May
On 5/18/23 10:12, Juan Quintela wrote:
The following changes since commit 266ccbb27b3ec6661f22395ec2c41d854c94d761:
Merge tag 'pull-target-arm-20230518'
ofhttps://git.linaro.org/people/pmaydell/qemu-arm into staging (2023-05-18
06:08:30 -0700)
are available in the Git repository
On Friday, May 19, 2023 10:52 AM, Wang, Lei4 wrote:
> > We can change it to uint16_t or uint32_t, but need to see if listening
> > on a larger value is OK to everyone.
>
> Is there any use case to use >256 migration channels? If not, then I suppose
> it's no need to increase it.
People can
It's more convenient to jump among files with --extra=+fq.
Signed-off-by: Fei Wu
---
Makefile | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Makefile b/Makefile
index 3c7d67142f..ffb3bcd4f4 100644
--- a/Makefile
+++ b/Makefile
@@ -239,8 +239,8 @@ ctags:
Paolo, please help add below queued sgx fix into this PULL request, which was
missed from last time, thanks a lot!
https://lists.nongnu.org/archive/html/qemu-devel/2023-04/msg00841.html
https://lists.nongnu.org/archive/html/qemu-devel/2023-04/msg00896.html
Regards,
Yang
Hi,
After pulling in the QEMU latest commits, I can no longer run the
"configure" command. Below is the error message I am seeing. I believe this
is related to this change "configure: create a python venv
unconditionally".
I am running on Debian GNU/Linux 11 (bullseye) and 5.15 kernel version.
On 5/19/2023 10:44, Wang, Wei W wrote:
> On Friday, May 19, 2023 9:31 AM, Wang, Lei4 wrote:
>> On 5/18/2023 17:16, Juan Quintela wrote:
>>> Lei Wang wrote:
When destination VM is launched, the "backlog" parameter for listen()
is set to 1 as default in
On Friday, May 19, 2023 9:31 AM, Wang, Lei4 wrote:
> On 5/18/2023 17:16, Juan Quintela wrote:
> > Lei Wang wrote:
> >> When destination VM is launched, the "backlog" parameter for listen()
> >> is set to 1 as default in socket_start_incoming_migration_internal(),
> >> which will lead to socket
Command "qemu-system-riscv64 -machine virt
-m 2G -smp 1 -numa node,mem=1G -numa node,mem=1G"
would trigger this problem.Backtrace with:
#0 0x55b5b1a4 in riscv_numa_get_default_cpu_node_id at
../hw/riscv/numa.c:211
#1 0x558ce510 in machine_numa_finish_cpu_init at
On Friday, May 19, 2023 3:20 AM, Peter Xu wrote:
> On Fri, May 19, 2023 at 12:00:26AM +0800, Wei Wang wrote:
> > qemu_start_incoming_migration needs to check the number of multifd
> > channels or postcopy ram channels to configure the backlog parameter (i.e.
> > the maximum length to which the
Support disas for Z*inx instructions only when Zfinx extension is supported.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
disas/riscv.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 9e01810eef..a370bac6ef
Remove redundant parenthese and fix multi-line comments.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
disas/riscv.c | 219 +-
1 file changed, 110 insertions(+), 109 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index
Support disas for Zcmt* instructions only when related extensions
are supported.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
disas/riscv.c | 20
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index
Pass RISCVCPUConfig as disassemble_info.target_info to support disas
of conflict instructions related to specific extensions.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
disas/riscv.c | 10 ++-
target/riscv/cpu.c | 1 +
target/riscv/cpu.h | 114
Some extensions have conflict encodings, such as
* Z*inx reuse the same encodings as normal float point extensions.
* Zcm* reuse the some encodings of Zcd.
* Custom extensions from different vendors may share the same encodings.
To resolve this problem, this patchset tries to pass
Fix lines with over 80 characters.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
disas/riscv.c | 201 +++---
1 file changed, 140 insertions(+), 61 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index fcea5d7beb..ee50a4ab0c
Currently decomp_rv32 and decomp_rv64 value in opcode_data for vector
instructions are the same op index as their own. And they have no
functional decomp_data. So they have no functional difference from just
leaving them as zero.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
Use pointer to pass more information of target to disasembler,
such as pass cpu.cfg related information in following commits.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
include/disas/dis-asm.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On Fri, Mar 03, 2023 at 04:07:25PM +, Daniel P. Berrangé wrote:
> The current test runner is only safe against parallel execution within
> a single instance of the 'check' process, and only if -j is given a
> value greater than 2. This prevents running multiple copies of the
> 'check' process
On 5/18/2023 17:16, Juan Quintela wrote:
> Lei Wang wrote:
>> When destination VM is launched, the "backlog" parameter for listen() is set
>> to 1 as default in socket_start_incoming_migration_internal(), which will
>> lead to socket connection error (the queue of pending connections is full)
>>
On 4/22/2023 12:42 AM, Alex Bennée wrote:
>
> Fei Wu writes:
>
>> This patch series were done by Vanderson and Alex originally in 2019, I
>> (Fei Wu) rebased them on latest upstream from:
>> https://github.com/stsquad/qemu/tree/tcg/tbstats-and-perf-v10
>> and send out this review per Alex's
On Thu, May 18, 2023 at 12:26:33PM -0700, Richard Henderson wrote:
> So, here we are again, out of runner time with 13 days left in the month.
>
> Did we come to any resolution since last time? Holding development for that
> long just
> isn't right, so I'll continue processing the hard way --
> From: Jason Gunthorpe
> Sent: Friday, May 19, 2023 4:19 AM
>
> On Thu, May 18, 2023 at 03:45:24PM -0400, Peter Xu wrote:
>
> > I see that Intel is already copied here (at least Yi and Kevin) so I assume
> > there're already some kind of synchronizations on multi-vIOMMU vs recent
> > works on
On Wed, May 17, 2023 at 06:10:22PM -0400, Stefan Hajnoczi wrote:
> No block driver implements .bdrv_co_io_plug() anymore. Get rid of the
> function pointers.
>
> Signed-off-by: Stefan Hajnoczi
> ---
> include/block/block-io.h | 3 ---
> include/block/block_int-common.h | 11 --
On Wed, May 17, 2023 at 06:10:21PM -0400, Stefan Hajnoczi wrote:
> Stop using the .bdrv_co_io_plug() API because it is not multi-queue
> block layer friendly. Use the new blk_io_plug_call() API to batch I/O
> submission instead.
>
> Signed-off-by: Stefan Hajnoczi
> ---
> include/block/raw-aio.h
On Wed, May 17, 2023 at 06:10:20PM -0400, Stefan Hajnoczi wrote:
> Stop using the .bdrv_co_io_plug() API because it is not multi-queue
> block layer friendly. Use the new blk_io_plug_call() API to batch I/O
> submission instead.
>
> Signed-off-by: Stefan Hajnoczi
> ---
> include/block/raw-aio.h
On Wed, May 17, 2023 at 06:10:19PM -0400, Stefan Hajnoczi wrote:
> Stop using the .bdrv_co_io_plug() API because it is not multi-queue
> block layer friendly. Use the new blk_io_plug_call() API to batch I/O
> submission instead.
>
> Signed-off-by: Stefan Hajnoczi
> ---
> block/blkio.c | 40
On Wed, May 17, 2023 at 06:10:18PM -0400, Stefan Hajnoczi wrote:
> Stop using the .bdrv_co_io_plug() API because it is not multi-queue
> block layer friendly. Use the new blk_io_plug_call() API to batch I/O
> submission instead.
>
> Signed-off-by: Stefan Hajnoczi
> ---
> block/nvme.c | 44
On Wed, May 17, 2023 at 06:10:17PM -0400, Stefan Hajnoczi wrote:
> Introduce a new API for thread-local blk_io_plug() that does not
> traverse the block graph. The goal is to make blk_io_plug() multi-queue
> friendly.
>
> Instead of having block drivers track whether or not we're in a plugged
>
Test execution of DC CVAP and DC CVADP instructions under user mode
emulation.
Signed-off-by: Zhuojia Shen
---
tests/tcg/aarch64/Makefile.target | 11 ++
tests/tcg/aarch64/dcpodp.c| 58 +++
tests/tcg/aarch64/dcpop.c | 58
DC CVAP and DC CVADP instructions can be executed in EL0 on Linux,
either directly when SCTLR_EL1.UCI == 1 or emulated by the kernel (see
user_cache_maint_handler() in arch/arm64/kernel/traps.c).
This patch enables execution of the two instructions in user mode
emulation.
Signed-off-by: Zhuojia
This patch series enables executing DC CVAP and DC CVADP instructions in
AArch64 Linux user mode emulation and adds proper TCG tests.
Changes in v3:
- Fix typo of HWCAP2_DCPODP
- Split tests into a separate patch
- Remove unnecessary handling of SIGILL in tests
- Merge 4 tests into 2
Changes in
> From: Jason Gunthorpe
> Sent: Thursday, May 18, 2023 10:57 PM
>
> On Thu, May 18, 2023 at 10:16:24AM -0400, Peter Xu wrote:
>
> > What you mentioned above makes sense to me from the POV that 1
> vIOMMU may
> > not suffice, but that's at least totally new area to me because I never
> > used >1
On Thu, 18 May 2023 16:03:07 -0400
"Michael S. Tsirkin" wrote:
> On Fri, Apr 21, 2023 at 06:06:49PM +0200, Robin Voetter wrote:
> >
> >
> > On 4/21/23 10:22, Michael S. Tsirkin wrote:
> > > On Thu, Apr 20, 2023 at 05:38:39PM +0200, ro...@streamhpc.com wrote:
> > >> From: Robin Voetter
> >
* T.J. Alumbaugh (talum...@google.com) wrote:
> On Tue, May 16, 2023 at 5:03 AM Dr. David Alan Gilbert
> wrote:
> >
> > * T.J. Alumbaugh (talum...@google.com) wrote:
> > > Working Set Reporting supported in virtio-balloon.
> > > - adds working set reporting and notification vqueues
> > > -
On Tue, May 16, 2023 at 5:03 AM Dr. David Alan Gilbert wrote:
>
> * T.J. Alumbaugh (talum...@google.com) wrote:
> > Working Set Reporting supported in virtio-balloon.
> > - adds working set reporting and notification vqueues
> > - QMP API additions:
> >- guest-ws property on balloon
> >
Pls do not v2 as reply to v1.
Start a new thread if you really want to reply to v1
with link to lore copy of v2.
--
MST
On Mon, May 15, 2023 at 05:25:18PM +0400, marcandre.lur...@redhat.com wrote:
> From: Marc-André Lureau
>
> It looks like the virtio_gpu_load() does not compute and set the offset,
> the same way virtio_gpu_set_scanout() does. This probably results in
> incorrect display until the
On Sat, May 13, 2023 at 12:09:02PM +0200, Bernhard Beschow wrote:
> This series:
> * Removes dead code from omap_uart and i82378
> * Resolves redundant code in the i8254 timer devices
> * Replaces string literals by macro usage for TYPE_ISA_PARALLEL devices
>
> Bernhard Beschow (4):
>
On Wed, May 10, 2023 at 06:39:49PM +, Bernhard Beschow wrote:
>
>
> Am 21. April 2023 16:40:47 UTC schrieb Bernhard Beschow :
> >
> >
> >Am 21. April 2023 07:15:18 UTC schrieb "Michael S. Tsirkin"
> >:
> >>On Thu, Mar 02, 2023 at 10:21:38PM +0100, Bernhard Beschow wrote:
> >>> This series
On Thu, May 18, 2023 at 08:36:22AM +0200, Eugenio Perez Martin wrote:
> On Thu, May 18, 2023 at 7:50 AM Jason Wang wrote:
> >
> > On Wed, May 17, 2023 at 2:30 PM Eugenio Perez Martin
> > wrote:
> > >
> > > On Wed, May 17, 2023 at 5:59 AM Jason Wang wrote:
> > > >
> > > > On Tue, May 9, 2023 at
On Wed, May 17, 2023 at 05:28:34PM +0200, Kevin Wolf wrote:
> This tests exercises graph locking, draining, and graph modifications
> with AioContext switches a lot. Amongst others, it serves as a
> regression test for bdrv_graph_wrlock() deadlocking because it is called
> with a locked AioContext
From: Matheus Tavares Bernardino
This enables LLDB to work with hexagon linux-user mode through the GDB
remote protocol.
Helped-by: Richard Henderson
Signed-off-by: Matheus Tavares Bernardino
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
Message-Id:
---
From: Brian Cain
Signed-off-by: Brian Cain
Co-authored-by: Sid Manning
Signed-off-by: Sid Manning
Co-authored-by: Matheus Tavares Bernardino
Signed-off-by: Matheus Tavares Bernardino
Reviewed-by: Taylor Simpson
Signed-off-by: Taylor Simpson
Message-Id:
Signed-off-by: Taylor Simpson
Co-authored-by: Brian Cain
Signed-off-by: Brian Cain
Co-authored-by: Matheus Tavares Bernardino
Signed-off-by: Matheus Tavares Bernardino
Reviewed-by: Brian Cain
Message-Id:
<17cb32f34d469f705c3cc066a3583935352ee048.1683214375.git.quic_mathb...@quicinc.com>
---
From: Matheus Tavares Bernardino
Signed-off-by: Matheus Tavares Bernardino
Reviewed-by: Taylor Simpson
Signed-off-by: Taylor Simpson
Message-Id:
---
MAINTAINERS| 1 +
configs/targets/hexagon-linux-user.mak | 1 +
target/hexagon/cpu.c | 3 +-
From: Matheus Tavares Bernardino
In the previous commit, we modified gdbstub.c to only send stop-reply
packets as a response to GDB commands that accept it. Now, let's add a
test for this intended behavior. Running this test before the fix from
the previous commit fails as QEMU sends a
18.05.2023 23:22, Michael S. Tsirkin пишет:
On Thu, Apr 27, 2023 at 05:10:13PM -0400, Alexander Bulekov wrote:
As the code is designed for re-entrant calls to apic-msi, mark apic-msi
as reentrancy-safe.
Signed-off-by: Alexander Bulekov
Reviewed-by: Darren Kenny
Acked-by: Michael S. Tsirkin
On Thu, Apr 27, 2023 at 05:10:13PM -0400, Alexander Bulekov wrote:
> As the code is designed for re-entrant calls to apic-msi, mark apic-msi
> as reentrancy-safe.
>
> Signed-off-by: Alexander Bulekov
> Reviewed-by: Darren Kenny
Acked-by: Michael S. Tsirkin
feel free to merge with rest of
On Thu, May 18, 2023 at 03:45:24PM -0400, Peter Xu wrote:
> On Thu, May 18, 2023 at 11:56:46AM -0300, Jason Gunthorpe wrote:
> > On Thu, May 18, 2023 at 10:16:24AM -0400, Peter Xu wrote:
> >
> > > What you mentioned above makes sense to me from the POV that 1 vIOMMU may
> > > not suffice, but
Jonathan Cameron wrote:
> On Wed, 17 May 2023 19:45:54 -0700
> Ira Weiny wrote:
>
> > Magic numbers can be confusing.
> >
> > Use the range size define for CXL.cachemem rather than a magic number.
> > Update/add spec references.
> >
> > Signed-off-by: Ira Weiny
>
> I guess we should do a
On Thu, May 18, 2023 at 12:20 PM Alex Bennée wrote:
>
> Since the update to the latest version Avocado only automatically
> collects logging under the avocado name space. Tweak the QEMUMachine
> class to allow avocado to bring logging under its name space. This
> also allows useful tricks like:
>
In certain cases, we can avoid the overhead of writing to future_VRegs
and write directly to VRegs. We consider HVX reads/writes when computing
ctx->need_commit. Then, we can early-exit from gen_commit_hvx.
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id:
Changes in v3
Fix bugs exposed by dpmpyss_rnd_s0 instruction
Set correct size/signedness for constants
Test cases added to tests/tcg/hexagon/misc.c
Changes in v2
Fix bug in imm_print identified in clang build
Currently, idef-parser skips all floating point
From: Matheus Tavares Bernardino
Currently, the python scripts used for the hexagon building will not
abort the compilation when there is an error parsing a register. Let's
make the compilation properly fail in such cases by rasing an exception
instead of just printing a warning message, which
Have gen_analyze_funcs mark the registers that are read by the
instruction. We also mark the implicit reads using instruction
attributes.
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <20230427230012.3800327-11-tsimp...@quicinc.com>
---
target/hexagon/translate.h
Only endloop instructions will conditionally write to a predicate.
When there is an endloop instruction, we preload the values into
new_pred_value.
The only place pred_written is needed is when HEX_DEBUG is on.
We remove the last use of check_for_attrib. However, new uses will be
introduced
Enable conditional compilation depending on whether idef-parser
is configured
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <20230427230012.3800327-2-tsimp...@quicinc.com>
---
meson.build | 1 +
1 file changed, 1 insertion(+)
diff --git a/meson.build b/meson.build
From: Matheus Tavares Bernardino
Running qemu-hexagon with a binary that was compiled for an arch version
unknown by qemu can produce a somewhat confusing message:
qemu-hexagon: unable to find CPU model 'unknown'
Let's give a bit more info by appending the eflags so that the message
becomes:
These instructions have implicit reads from p0, so we don't want
them in helpers when idef-parser is off.
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <20230427230012.3800327-6-tsimp...@quicinc.com>
---
target/hexagon/gen_tcg.h | 16
The following instructions are added
J2_callrh
J2_junprh
Signed-off-by: Taylor Simpson
Reviewed-by: Anton Johansson
Message-Id: <20230427224057.3766963-9-tsimp...@quicinc.com>
---
target/hexagon/gen_tcg.h | 4
target/hexagon/attribs_def.h.inc | 1 +
Tests added for the following instructions
J2_callrh
J2_jumprh
Signed-off-by: Taylor Simpson
Reviewed-by: Anton Johansson
Message-Id: <20230427224057.3766963-10-tsimp...@quicinc.com>
---
tests/tcg/hexagon/v73_scalar.c| 96 +++
The following have overrides
S2_insert
S2_insert_rp
S2_asr_r_svw_trun
A2_swiz
These instructions have semantics that write to the destination
before all the operand reads have been completed. Therefore,
the idef-parser versions were disabled with the short-circuit patch.
Test
From: Matheus Tavares Bernardino
The Hexagon PRM says that "The assembler automatically encodes
instructions in the packet in the proper order. In the binary encoding
of a packet, the instructions must be ordered from Slot 3 down to
Slot 0."
Prior to the architecture version v73, the slot
On Fri, Apr 21, 2023 at 01:32:04PM +0300, Vladimir Sementsov-Ogievskiy wrote:
> DEVICE_DELETED and DEVICE_UNPLUG_GUEST_ERROR has equal data, let's
> refactor it to one structure. That also helps to add new events
> consistently.
>
> Signed-off-by: Vladimir Sementsov-Ogievskiy
Can QAPI
With the overrides added in prior commits, this function is not used
Remove references in macros.h
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <20230427230012.3800327-7-tsimp...@quicinc.com>
---
target/hexagon/macros.h| 14 --
These instructions have implicit writes to registers, so we don't
want them to be helpers when idef-parser is off.
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <20230427230012.3800327-5-tsimp...@quicinc.com>
---
target/hexagon/gen_tcg.h | 32
The pred_written variable in the CPUHexagonState is only used for
bookkeeping within the translation of a packet. With recent changes
that eliminate the need to free TCGv variables, these make more sense
to be transient and kept in DisasContext.
Suggested-by: Richard Henderson
Signed-off-by:
In certain cases, we can avoid the overhead of writing to hex_new_value
and write directly to hex_gpr. We add need_commit field to DisasContext
indicating if the end-of-packet commit is needed. If it is not needed,
get_result_gpr() and get_result_gpr_pair() can return hex_gpr.
We pass the
From: Matheus Tavares Bernardino
Currently, qemu-hexagon only models the v67 cpu. Nonetheless if we try
to get this information with `-cpu help`, qemu just exists with an error
code and no output. Let's correct that.
The code is basically a copy from target/alpha/cpu.h, but we strip the
These instructions have implicit writes to registers, so we don't
want them to be helpers when idef-parser is off.
Signed-off-by: Taylor Simpson
Acked-by: Richard Henderson
Message-Id: <20230427230012.3800327-4-tsimp...@quicinc.com>
---
target/hexagon/gen_tcg.h | 21 +++
Add support for the ELF flags
Move target/hexagon/cpu.[ch] to be v73
Change the compiler flag used by "make check-tcg"
The decbin instruction is removed in Hexagon v73, so check the
version before trying to compile the instruction.
Signed-off-by: Taylor Simpson
Reviewed-by: Anton Johansson
From: Matheus Tavares Bernardino
GDB's remote serial protocol allows stop-reply messages to be sent by
the stub either as a notification packet or as a reply to a GDB command
(provided that the cmd accepts such a response). QEMU currently does not
implement notification packets, so it should
From: Matheus Tavares Bernardino
Each slot in a packet can be assigned to at most one instruction.
Although the assembler generally ought to enforce this rule, we better
be safe than sorry and also do some check to properly throw an "invalid
packet" exception on wrong slot assignments.
This
The pkt_has_store_s1 field is only used for bookkeeping helpers with
a load. With recent changes that eliminate the need to free TCGv
variables, it makes more sense to make this transient.
These helpers already take the instruction slot as an argument. We
combine the slot and pkt_has_store_s1
The following instructions are tested
V6_vasrvuhubrndsat
V6_vasrvuhubsat
V6_vasrvwuhrndsat
V6_vasrvwuhsat
V6_vassign_tmp
V6_vcombine_tmp
V6_vmpyuhvs
Signed-off-by: Taylor Simpson
Reviewed-by: Anton Johansson
Message-Id: <20230427224057.3766963-8-tsimp...@quicinc.com>
When generating TCG, make sure we have read all the operand registers
before writing to the destination registers.
This is a prerequesite for short-circuiting where the source and dest
operands could be the same.
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id:
The new_value array in the CPUHexagonState is only used for bookkeeping
within the translation of a packet. With recent changes that eliminate
the need to free TCGv variables, these make more sense to be transient
and kept in DisasContext.
Suggested-by: Richard Henderson
Signed-off-by: Taylor
Signed-off-by: Taylor Simpson
Reviewed-by: Anton Johansson
Message-Id: <20230427224057.3766963-4-tsimp...@quicinc.com>
---
tests/tcg/hexagon/v68_scalar.c| 186 ++
tests/tcg/hexagon/Makefile.target | 2 +
2 files changed, 188 insertions(+)
create mode 100644
From: Marco Liebel
test_vshuff checks that the vshuff instruction works correctly when
both vector registers are the same. Using vshuff in this way is
undefined and will be rejected by the compiler in a future version of
the toolchain.
Signed-off-by: Marco Liebel
Reviewed-by: Brian Cain
These instructions have implicit writes to registers, so we don't
want them to be helpers when idef-parser is off.
The following instructions are overriden
S2_cabacdecbin
SA1_cmpeqi
Remove the log_pred_write function from op_helper.c
Remove references in macros.h
Signed-off-by: Taylor
The following instructions are added
V6_v6mpyvubs10_vxx
V6_v6mpyhubs10_vxx
V6_v6mpyvubs10
V6_v6mpyhubs10
Signed-off-by: Taylor Simpson
Reviewed-by: Anton Johansson
Message-Id: <20230427224057.3766963-5-tsimp...@quicinc.com>
---
target/hexagon/mmvec/macros.h| 9
In certain cases, we can avoid the overhead of writing to hex_new_pred_value
and write directly to hex_pred. We consider predicate reads/writes when
computing ctx->need_commit. The get_result_pred() function uses this
field to decide between hex_new_pred_value and hex_pred. Then, we can
The following items in the CPUHexagonState are only used for bookkeeping
within the translation of a packet. With recent changes that eliminate
the need to free TCGv variables, these make more sense to be transient
and kept in DisasContext.
The following items are moved
dczero_addr
The generated helpers for HVX use pass-by-reference, so they can't
short-circuit when the reads/writes overlap. The instructions with
overrides are OK because they use tcg_gen_gvec_*.
We add a flag has_hvx_helper to DisasContext and extend gen_analyze_funcs
to set the flag when the instruction
The following instructions are added
L2_loadw_aq
L4_loadd_aq
R6_release_at_vi
R6_release_st_vi
S2_storew_rl_at_vi
S4_stored_rl_at_vi
S2_storew_rl_st_vi
S4_stored_rl_st_vi
The release instructions are nop's in qemu. The others behave as
loads/stores.
The
Precursor to moving new_value from the global state to DisasContext
USR will need to stay in the global state because some helpers will
set it's value
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <20230427230012.3800327-17-tsimp...@quicinc.com>
---
The following instructions are added
V6_vasrvuhubrndsat
V6_vasrvuhubsat
V6_vasrvwuhrndsat
V6_vasrvwuhsat
V6_vassign_tmp
V6_vcombine_tmp
V6_vmpyuhvs
Signed-off-by: Taylor Simpson
Reviewed-by: Anton Johansson
Message-Id: <20230427224057.3766963-7-tsimp...@quicinc.com>
The following changes since commit 278238505d28d292927bff7683f39fb4fbca7fd1:
Merge tag 'pull-tcg-20230511-2' of https://gitlab.com/rth7680/qemu into
staging (2023-05-11 11:44:23 +0100)
are available in the Git repository at:
https://github.com/quic/qemu tags/pull-hex-20230518-1
for you
The new_pred_value array in the CPUHexagonState is only used for
bookkeeping within the translation of a packet. With recent changes
that eliminate the need to free TCGv variables, these make more sense
to be transient and kept in DisasContext.
Suggested-by: Richard Henderson
Signed-off-by:
From: Paolo Bonzini
Changes in v2
Fix yyassert's for sign and zero extends
Coverity reports a parameter that is "set but never used". This is caused
by an assignment operator being used instead of equality.
Co-authored-by: Taylor Simpson
Signed-off-by: Paolo Bonzini
Signed-off-by:
Add DisasContext arg to gen_log_reg_write_pair also
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <20230427230012.3800327-3-tsimp...@quicinc.com>
---
target/hexagon/gen_tcg.h| 2 +-
target/hexagon/genptr.h | 2 +-
Signed-off-by: Taylor Simpson
Reviewed-by: Anton Johansson
Message-Id: <20230427224057.3766963-6-tsimp...@quicinc.com>
---
tests/tcg/hexagon/v68_hvx.c | 90 +
tests/tcg/hexagon/v6mpy_ref.c.inc | 161 ++
tests/tcg/hexagon/Makefile.target | 3 +
On Fri, Apr 21, 2023 at 06:06:49PM +0200, Robin Voetter wrote:
>
>
> On 4/21/23 10:22, Michael S. Tsirkin wrote:
> > On Thu, Apr 20, 2023 at 05:38:39PM +0200, ro...@streamhpc.com wrote:
> >> From: Robin Voetter
> >>
> >> The ROCm driver for Linux uses PCIe atomics to schedule work and
> >>
On Tue, Apr 11, 2023 at 09:24:39PM +0700, Bui Quang Minh wrote:
> As userspace APIC now supports x2APIC, intel interrupt remapping
> hardware can be set to EIM mode when userspace local APIC is used.
>
> Signed-off-by: Bui Quang Minh
> ---
> hw/i386/intel_iommu.c | 11 ---
> 1 file
On Wed, May 17, 2023 at 12:26:18PM -0400, Stefan Hajnoczi wrote:
> On Wed, 17 May 2023 at 11:54, Alex Bennée wrote:
> Hi Alex,
> There were two unresolved issues:
>
> 1. How to inject SIGBUS when the guest accesses a page that's beyond
> the end-of-file.
> 2. Implementing the vhost-user messages
On Thu, May 18, 2023 at 11:56:46AM -0300, Jason Gunthorpe wrote:
> On Thu, May 18, 2023 at 10:16:24AM -0400, Peter Xu wrote:
>
> > What you mentioned above makes sense to me from the POV that 1 vIOMMU may
> > not suffice, but that's at least totally new area to me because I never
> > used >1
On 05/17/2023 12:51 PM -0700, Richard Henderson wrote:
> On 5/17/23 10:31, Zhuojia Shen wrote:
> > DC CVAP and DC CVADP instructions can be executed in EL0 on Linux,
> > either directly when SCTLR_EL1.UCI == 1 or emulated by the kernel (see
> > user_cache_maint_handler() in
So, here we are again, out of runner time with 13 days left in the month.
Did we come to any resolution since last time? Holding development for that long just
isn't right, so I'll continue processing the hard way -- testing on private runners and
local build machines.
r~
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