On 5/23/23 22:46, Richard Henderson wrote:
The beginning of the structure, with pretaddr, should be just below
16-byte alignment. Disconnect fpstate from sigframe, just like the
kernel does.
Signed-off-by: Richard Henderson
---
linux-user/i386/signal.c | 104
The beginning of the structure, with pretaddr, should be just below
16-byte alignment. Disconnect fpstate from sigframe, just like the
kernel does.
Signed-off-by: Richard Henderson
---
linux-user/i386/signal.c | 104 +--
tests/tcg/x86_64/sigstack.c |
Hi Weiwei Li,
You're right, it seems that we need to add a check in riscv_imsic.c
Thanks for the advice!
Best Regards,
Tommy
On Wed, May 24, 2023 at 10:35 AM Weiwei Li wrote:
>
> On 2023/5/24 09:51, Tommy Wu wrote:
> > Hi Weiwei Li,
> > Yes, you're right, `riscv_refresh_dynamic_csr_xml()`
Hi WeiWei Li,
When the CPU is realizing, it will call `riscv_gen_dynamic_csr_xml` for the
first time with the correct `base_reg` value.
code flow :
riscv_cpu_realize
→ riscv_cpu_register_gdb_regs_for_features
→ riscv_gen_dynamic_csr_xml
The functionality of `cpu->dyn_csr_base_reg` is
The commit title/message are duplicated to previous one, Here should
use "query-named-block-nodes" instead.
Lin
From: Fabiano Rosas
Sent: Wednesday, May 24, 2023 5:39 AM
To: qemu-devel@nongnu.org
Cc: qemu-bl...@nongnu.org; Kevin Wolf; Hanna Reitz; Markus
On 2023/05/24 13:06, Jason Wang wrote:
On Wed, May 24, 2023 at 3:54 AM Michael Tokarev wrote:
23.05.2023 10:31, Jason Wang wrote:
https://github.com/jasowang/qemu.git tags/net-pull-request
I might be wrong but it looks like besides the rtl8139 fix which went
to -stable already, and
On Wed, May 24, 2023 at 3:54 AM Michael Tokarev wrote:
>
> 23.05.2023 10:31, Jason Wang wrote:
>
> >https://github.com/jasowang/qemu.git tags/net-pull-request
>
> I might be wrong but it looks like besides the rtl8139 fix which went
> to -stable already, and "e1000e: Fix tx/rx counters"
/davidhildenbrand/qemu into
staging (2023-05-23 10:57:25 -0700)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230523-2
for you to fetch changes up to a57663c5a38c26516bde24ecb3992adff4861a31:
tcg: Remove USE_TCG_OPTIMIZATIONS (2023-05-24 01:10:44 +
On 2023/5/24 09:51, Tommy Wu wrote:
Hi Weiwei Li,
Yes, you're right, `riscv_refresh_dynamic_csr_xml()` can only be
called when
cpu->dyn_csr_xml isn't a NULL pointer here.
The cpu->dyn_csr_xml will be set when the cpu is realized.
Yeah, It will be set only when Zicsr is supported. And
On 2023/5/24 09:59, Tommy Wu wrote:
Hi Weiwei Li,
`dyn_csr_base_reg` will be used in `riscv_refresh_dynamic_csr_xml`
We can initialize this variable when the cpu is realized.
I didn't find this initialization in following code.
And used this variable in `riscv_refresh_dynamic_csr_xml`.
write_mstatus() can only change current xl when in debug mode.
And we need update cur_pmmask/base in this case.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: LIU Zhiwei
---
target/riscv/csr.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git
actual_address = (requested_address & ~mpmmask) | mpmbase.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: LIU Zhiwei
---
target/riscv/vector_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
This patchset tries to fix some problem in current implementation for pointer
mask, and add support for pointer mask of instruction fetch.
The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-pm-fix-v7
v2:
* drop some error patchs
* Add patch 2 and 3 to fix the new
Hi Weiwei Li,
`dyn_csr_base_reg` will be used in `riscv_refresh_dynamic_csr_xml`
We can initialize this variable when the cpu is realized. And used this
variable in `riscv_refresh_dynamic_csr_xml`.
Best regards,
Tommy
On Tue, May 23, 2023 at 10:38 PM Weiwei Li wrote:
>
> On 2023/5/23 19:44,
Hi Weiwei Li,
Yes, you're right, `riscv_refresh_dynamic_csr_xml()` can only be called
when
cpu->dyn_csr_xml isn't a NULL pointer here.
The cpu->dyn_csr_xml will be set when the cpu is realized.
Best Regards,
Tommy
On Tue, May 23, 2023 at 10:44 PM Weiwei Li wrote:
>
> On 2023/5/23 19:44,
On Tuesday, May 23, 2023 10:50 PM, Peter Xu wrote:
> On Tue, May 23, 2023 at 02:30:25PM +, Wang, Wei W wrote:
> > > It's about whether we want to protect e.g. below steps:
> > >
> > > 1. start dest qemu with -incoming defer 2.
> > > "migrate-set-capabilities" to enable multifd 3.
-0700)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230523-2
for you to fetch changes up to a57663c5a38c26516bde24ecb3992adff4861a31:
tcg: Remove USE_TCG_OPTIMIZATIONS (2023-05-24 01:10:44 +
With FEAT_LSE2, load and store of int128 is directly supported.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
host/include/aarch64/host/atomic128-ldst.h | 53 --
1 file changed, 40 insertions(+), 13 deletions(-)
diff --git
On 5/23/23 09:45, Philippe Mathieu-Daudé wrote:
On 23/5/23 15:53, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
tcg/region.c | 2 ++
tcg/tcg-common.c | 2 ++
tcg/tcg-op-gvec.c | 2 ++
tcg/tcg-op-ldst.c | 2 ++
tcg/tcg-op-vec.c | 2 ++
tcg/tcg-op.c | 2 ++
Remove the locally defined load_atomic16 and store_atomic16,
along with HAVE_al16 and HAVE_al16_fast in favor of the
routines defined in atomic128.h.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 2 +-
accel/tcg/ldst_atomicity.c.inc | 118
Create both atomic16_read_ro and atomic16_read_rw.
Previously we pretended that we had atomic16_read in system mode,
because we "know" that all ram is always writable to the host.
Now, expose read-only and read-write versions all of the time.
For aarch64, do not fall back to __atomic_read_16 even
No need to roll our own, as this is now provided by tcg.
This was the last use of retxl, so remove that too.
Reviewed-by: Alex Bennée
Reviewed-by: David Hildenbrand
Signed-off-by: Richard Henderson
---
target/s390x/cpu.h | 3 --
target/s390x/helper.h| 4 ---
Now that load/store are gone, we're always passing
PAGE_READ | PAGE_WRITE for RMW atomic operations.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
accel/tcg/atomic_template.h | 32 ++
accel/tcg/cputlb.c | 85 ++---
Add a bit to indicate when VMOVDQU is also atomic if aligned.
Reviewed-by: Alex Bennée
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
host/include/i386/host/cpuinfo.h | 1 +
util/cpuinfo-i386.c | 4 +++-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git
Use cpuinfo_init() during init_accel(), and the variable cpuinfo
during test_buffer_is_zero_next_accel(). Adjust the logic that
cycles through the set of accelerators for testing.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
util/bufferiszero.c | 127
Eliminate the CONFIG_USER_ONLY specialization.
Reviewed-by: Alex Bennée
Reviewed-by: David Hildenbrand
Signed-off-by: Richard Henderson
---
target/s390x/tcg/mem_helper.c | 8 +---
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/target/s390x/tcg/mem_helper.c
Separates the aarch64-specific portion into its own file.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
host/include/aarch64/host/atomic128-ldst.h | 49 ++
host/include/generic/host/atomic128-ldst.h | 57 +
include/qemu/atomic128.h
This is always defined, and the optimization pass is
essential to producing reasonable code.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index bfe3d80fc2..ac30d484f5 100644
---
These symbols will shortly become dynamic runtime tests and
therefore not appropriate for the preprocessor. Use the
matching CONFIG_* symbols for that purpose.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
host/include/aarch64/host/atomic128-cas.h | 2 ++
Place the CONFIG_AVX512BW_OPT block at the top,
which will aid function selection in the next patch.
Reviewed-by: Alex Bennée
Reviewed-by: Juan Quintela
Signed-off-by: Richard Henderson
---
migration/xbzrle.c | 244 ++---
1 file changed, 122
With the current structure of cputlb.c, there is no difference
between the little-endian and big-endian entry points, aside
from the assert. Unify the pairs of functions.
The only use of the functions with explicit endianness was in
target/sparc64, and that was only to satisfy the assert: the
Silly typo: sizeof(16) != 16.
Fixes: e61f1efeb730 ("meson: Detect atomic128 support with optimization")
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/meson.build
Not only the routines in ldst_atomicity.c.inc need markup,
but also the ones in the headers.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
host/include/generic/host/atomic128-cas.h | 12
host/include/generic/host/atomic128-ldst.h | 18 --
With FEAT_LSE2, load and store of int128 is directly supported.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
host/include/aarch64/host/atomic128-ldst.h | 53 --
1 file changed, 40 insertions(+), 13 deletions(-)
diff --git
No need to roll our own, as this is now provided by tcg.
This was the last use of retxl, so remove that too.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/ppc/cpu.h | 1 -
target/ppc/helper.h| 9
Use cpu_ld16_mmu and cpu_st16_mmu to eliminate the special case,
and change all of the *_data_ra functions to match.
Note that we check the alignment of both compare and store
pointers at the top of the function, so MO_ALIGN* may be
safely removed from the individual memory operations.
Move the code from tcg/. The only use of these bits so far
is with respect to the atomicity of tcg operations.
Reviewed-by: Alex Bennée
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
host/include/aarch64/host/cpuinfo.h | 22 ++
tcg/aarch64/tcg-target.h|
Separates the aarch64-specific portion into its own file.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
host/include/aarch64/host/atomic128-cas.h | 43 ++
host/include/generic/host/atomic128-cas.h | 43 ++
include/qemu/atomic128.h
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/tcg/debug-assert.h | 17 +
include/tcg/tcg.h | 9 +
MAINTAINERS| 1 +
3 files changed, 19 insertions(+), 8 deletions(-)
create mode
Use __sync_bool_compare_and_swap_16 to control the loop,
rather than a separate comparison.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
host/include/generic/host/atomic128-ldst.h | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git
Atomic load/store of 128-byte quantities is now handled
by cpu_{ld,st}16_mmu.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
accel/tcg/atomic_template.h | 61 +++
include/exec/cpu_ldst.h | 9 --
accel/tcg/atomic_common.c.inc | 14
The following changes since commit aa33508196f4e2da04625bee36e1f7be5b9267e7:
Merge tag 'mem-2023-05-23' of https://github.com/davidhildenbrand/qemu into
staging (2023-05-23 10:57:25 -0700)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230523
The entire contents of the header is host-specific, but the
existence of such a header is not, which could prevent some
host specific ifdefs at the top of the file for the include.
Add host/include/{arch,generic} to the project arguments.
Reviewed-by: Alex Bennée
Reviewed-by: Philippe
Perform the function selection once, and only if CONFIG_AVX512_OPT
is enabled. Centralize the selection to xbzrle.c, instead of
spreading the init across 3 files.
Remove xbzrle-bench.c. The benefit of being able to benchmark
the different implementations is less important than not peeking
into
Use the CPUINFO_* bits instead of the individual boolean
variables that we had been using. Remove all of the init
code that was moved over to cpuinfo-i386.c.
Note that have_avx512* check both AVX512{F,VL}, as we had
previously done during tcg_target_init.
Reviewed-by: Alex Bennée
Reviewed-by:
This had been set since the beginning, is never undefined,
and it would seem to be harmful to debugging to do so.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/exec/exec-all.h | 3 ---
accel/tcg/cpu-exec.c | 2 --
accel/tcg/translate-all.c | 2 --
The items in migration_files are built for libmigration and included
info softmmu_ss from there; no need to also include them directly.
Reviewed-by: Alex Bennée
Reviewed-by: Juan Quintela
Signed-off-by: Richard Henderson
---
migration/meson.build | 1 -
1 file changed, 1 deletion(-)
diff
Add cpuinfo.h for i386 and x86_64, and the initialization
for that in util/. Populate that with a slightly altered
copy of the tcg host probing code. Other uses of cpuid.h
will be adjusted one patch at a time.
Reviewed-by: Alex Bennée
Reviewed-by: Juan Quintela
Signed-off-by: Richard
On 5/23/23 09:36, Philippe Mathieu-Daudé wrote:
@@ -321,13 +321,13 @@ static void vhost_vdpa_listener_region_add(MemoryListener
*listener,
return;
}
-if (unlikely((section->offset_within_address_space & ~TARGET_PAGE_MASK) !=
-
On 5/23/23 09:35, Philippe Mathieu-Daudé wrote:
The previous commit remove the unnecessary "virtio-access.h"
header. These files no longer have target-specific dependency.
Move them to the generic 'softmmu_ss' source set.
Signed-off-by: Philippe Mathieu-Daudé
---
On 5/23/23 09:35, Philippe Mathieu-Daudé wrote:
None of these files use the VirtIO Load/Store API declared
by "hw/virtio/virtio-access.h". This header probably crept
in via copy/pasting, remove it.
Note, "virtio-access.h" is target-specific, so any file
including it also become tainted as
On 5/23/23 09:35, Philippe Mathieu-Daudé wrote:
In order to have virtio-iommu.c become target-agnostic,
we need to avoid using TARGET_PAGE_MASK. Get it with the
qemu_target_page_mask() helper.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/virtio/virtio-iommu.c | 3 ++-
1 file changed, 2
On 5/23/23 09:35, Philippe Mathieu-Daudé wrote:
Instead of having "virtio/virtio-bus.h" implicitly included,
explicit it, to avoid when rearranging headers:
hw/virtio/vhost-vsock-common.c: In function ‘vhost_vsock_common_start’:
hw/virtio/vhost-vsock-common.c:51:5: error: unknown type
On 5/23/23 09:35, Philippe Mathieu-Daudé wrote:
Avoid accessing RAMBlock internals, use the provided
qemu_ram_get_fd() getter to get the file descriptor.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/virtio/virtio-mem.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by:
On 5/23/23 09:35, Philippe Mathieu-Daudé wrote:
Instead of adding 'vhost-vsock-common.c' twice (for VHOST_VSOCK
and VHOST_USER_VSOCK), have it depend on VHOST_VSOCK_COMMON,
selected by both symbols.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/virtio/Kconfig | 6 ++
On 5/23/23 09:35, Philippe Mathieu-Daudé wrote:
Following the SCSI variable named '[specific_]scsi_ss', rename the
target-specific VirtIO/SCSI set prefixed with 'specific_'. This will
help when adding target-agnostic VirtIO/SCSI set in few commits.
No logical change.
Signed-off-by: Philippe
On 5/23/23 09:35, Philippe Mathieu-Daudé wrote:
We will modify this file shortly. Re-arrange it slightly first,
declaring source sets first.
No logical change.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/scsi/meson.build | 12 +---
1 file changed, 5 insertions(+), 7 deletions(-)
On 5/23/23 09:35, Philippe Mathieu-Daudé wrote:
Instead of adding 'vhost-scsi-common.c' twice (for VHOST_SCSI and
VHOST_USER_SCSI), have it depend on VHOST_SCSI_COMMON, selected by
both symbols.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/scsi/Kconfig | 6 ++
hw/scsi/meson.build | 6
On 5/23/23 09:35, Philippe Mathieu-Daudé wrote:
+unsigned qemu_target_page_mask(void);
Should be signed int, so that it sign-extends to whatever needed width.
r~
On 5/23/23 16:02, BALATON Zoltan wrote:
On Tue, 23 May 2023, Richard Henderson wrote:
Instead of computing an artifical "class" bitmask then
converting that to the fprf value, compute the final
value from the start.
Reorder the tests to check the most likely cases first.
Signed-off-by:
On 5/23/23 05:50, Alex Bennée wrote:
static inline uint32_t qemu_xxhash5(uint64_t ab, uint64_t cd, uint32_t e)
{
-return qemu_xxhash7(ab, cd, e, 0, 0);
+return qemu_xxhash8(ab, cd, e, 0, 0);
}
static inline uint32_t qemu_xxhash6(uint64_t ab, uint64_t cd, uint32_t e,
On Tue, 23 May 2023, Richard Henderson wrote:
Instead of computing an artifical "class" bitmask then
converting that to the fprf value, compute the final
value from the start.
Reorder the tests to check the most likely cases first.
Signed-off-by: Richard Henderson
---
target/ppc/fpu_helper.c
On Tue, 23 May 2023, Richard Henderson wrote:
Instead of computing an artifical "class" bitmask then
converting that to the fprf value, compute the final
value from the start.
Reorder the tests to check the most likely cases first.
This seems to work in that it makes the function go down in
Remove the signed * signed check, leaving the signed * unsigned check.
This link test runs foul of -fsanitize=undefined, where clang-11 has
an undefined reference to __muloti4 to check for signed overflow.
This failure prevents us properly detecting atomic128 support.
Signed-off-by: Richard
The 05/22/2023 16:09, Jonathan Cameron wrote:
> Defined in CXL r3.0 8.2.9.2.1.2 DRAM Event Record, this event
> provides information related to DRAM devices.
>
> Example injection command in QMP:
>
> { "execute": "cxl-inject-dram-event",
> "arguments": {
> "path":
The 05/22/2023 16:09, Jonathan Cameron wrote:
> These events include a copy of the device health information at the
> time of the event. Actually using the emulated device health would
> require a lot of controls to manipulate that state. Given the aim
> of this injection code is to just test the
Hello Philippe,
On 5/23/23 3:52 AM, Philippe Mathieu-Daudé wrote:
Hi Ninad,
On 22/5/23 17:36, Ninad Palsule wrote:
The VPD data is added for system and BMC FRU. This data is fabricated.
Per
https://www.qemu.org/docs/master/devel/submitting-a-patch.html#write-a-meaningful-commit-message:
Please review the change.
- This drops adds VPD data for rainier machine.
- The VPD data is added for system VPD and BMC FRU.
Ninad Palsule (1):
hw/arm/aspeed:Add vpd data for Rainier machine
hw/arm/aspeed.c| 6 --
hw/arm/aspeed_eeprom.c | 45
The current modeling of Rainier machine creates zero filled VPDs(EEPROMs).
This makes some services and applications unhappy and causing them to fail.
Hence this drop adds some fabricated data for system and BMC FRU so that
vpd services are happy and active.
Tested:
- The system-vpd.service is
Some callers of this function are about to be converted to use
coroutines, so allow it to be executed both inside and outside a
coroutine.
Signed-off-by: Fabiano Rosas
---
include/block/block-io.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/block/block-io.h
The last call site of this function has been removed by commit
c04d0ab026 ("qemu-img: Let info print block graph").
Signed-off-by: Fabiano Rosas
---
block/qapi.c | 27 ---
include/block/qapi.h | 3 ---
2 files changed, 30 deletions(-)
diff --git a/block/qapi.c
From: João Silva
The fstat call can take a long time to finish when running over
NFS. Add a version of it that runs in the thread pool.
Adapt one of its users, raw_co_get_allocated_file size to use the new
version. That function is called via QMP under the qemu_global_mutex
so it has a large
From: Lin Ma
Sometimes the query-block performs time-consuming I/O(say waiting for
the fstat of NFS complete), So let's make this QMP handler runs in a
coroutine.
The following patch moves the fstat() into a thread pool.
Signed-off-by: Lin Ma
Signed-off-by: Fabiano Rosas
---
blockdev.c
As discussed in another thread [1], here's an RFC addressing a VCPU
softlockup encountered when issuing QMP commands that target a disk
placed on NFS.
Since QMP commands happen with the qemu_global_mutex locked, any
command that takes too long to finish will block other threads waiting
to take
From: Lin Ma
Sometimes the query-block performs time-consuming I/O(say waiting for
the fstat of NFS complete), So let's make this QMP handler runs in a
coroutine.
The following patch moves the fstat() into a thread pool.
Signed-off-by: Lin Ma
Signed-off-by: Fabiano Rosas
---
We're about to move calls to 'fstat' into the thread-pool to avoid
blocking VCPU threads should the system call take too long.
To achieve that we first need to make sure none of its callers is
holding the aio_context lock, otherwise yielding before scheduling the
aiocb handler would result in a
Hello Cedric,
On 5/23/23 12:53 AM, Cédric Le Goater wrote:
On 5/22/23 17:36, Ninad Palsule wrote:
The VPD data is added for system and BMC FRU. This data is fabricated.
Tested:
- The system-vpd.service is active.
- VPD service related to bmc is active.
Signed-off-by: Ninad Palsule
> -Original Message-
> From: Matheus Tavares Bernardino
> Sent: Tuesday, May 23, 2023 3:36 PM
> To: qemu-devel@nongnu.org
> Cc: Taylor Simpson ; Brian Cain
> ; Marco Liebel (QUIC)
> Subject: [PATCH 2/2] Hexagon: fix outdated `hex_new_*` references in
> comments
>
> Some code comments
> -Original Message-
> From: Matheus Tavares Bernardino
> Sent: Tuesday, May 23, 2023 3:36 PM
> To: qemu-devel@nongnu.org
> Cc: Taylor Simpson ; Brian Cain
> ; Marco Liebel (QUIC)
> Subject: [PATCH 1/2] target/hexagon/*.py: remove undef vars from
> bad_register()
>
> Some calls to
On Tue, Apr 18, 2023 at 05:21:33PM +0100, Alex Bennée wrote:
> Lets document some more of the core VirtIODevice structure.
>
> Signed-off-by: Alex Bennée
> ---
> include/hw/virtio/virtio.h | 8
> 1 file changed, 8 insertions(+)
>
> diff --git a/include/hw/virtio/virtio.h
On 5/23/23 06:59, Weiwei Li wrote:
pc_succ_insn is no longer useful after the introduce of cur_insn_len
and all pc related value use diff value instead of absolute value.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/translate.c | 7 +--
1 file changed, 1
On 5/23/23 06:59, Weiwei Li wrote:
Add a base pc_save for PC-relative translation(CF_PCREL).
Diable the directly sync pc from tb by riscv_cpu_synchronize_from_tb.
Use gen_pc_plus_diff to get the pc-relative address.
Enable CF_PCREL in System mode.
Signed-off-by: Weiwei Li
Signed-off-by:
On Tue, Apr 18, 2023 at 05:21:32PM +0100, Alex Bennée wrote:
> Signed-off-by: Alex Bennée
> ---
> include/hw/virtio/virtio.h | 6 ++
> 1 file changed, 6 insertions(+)
Reviewed-by: Stefan Hajnoczi
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On Tue, Apr 18, 2023 at 05:21:31PM +0100, Alex Bennée wrote:
> Signed-off-by: Alex Bennée
> ---
> include/hw/virtio/virtio.h | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git a/include/hw/virtio/virtio.h b/include/hw/virtio/virtio.h
> index f236e94ca6..22ec098462 100644
> ---
Some calls to `hex_common.bad_register()` in Hexagon python files are
passing undefined variables. Let's remove those.
Signed-off-by: Matheus Tavares Bernardino
---
target/hexagon/gen_helper_funcs.py | 8
target/hexagon/gen_tcg_funcs.py| 6 +++---
2 files changed, 7 insertions(+),
Some code comments refer to hex_new_value and hex_new_pred_value, which
have been transferred to DisasContext and, in the case of hex_new_value,
should now be accessed through get_result_gpr(). Let's update these
comments to reflect the new state of the codebase. Since they are only
meant to
These are two minor follow ups to the last Hexagon pull, updating some
stale code comments and removing undefined variables from error messages
at python scripts.
Matheus Tavares Bernardino (2):
target/hexagon/*.py: remove undef vars from bad_register()
Hexagon: fix outdated `hex_new_*`
On Tue, Apr 18, 2023 at 05:21:30PM +0100, Alex Bennée wrote:
> Fixes: 544f0278af (virtio: introduce macro VIRTIO_CONFIG_IRQ_IDX)
> Signed-off-by: Alex Bennée
> ---
> hw/display/vhost-user-gpu.c| 4 ++--
> hw/net/virtio-net.c| 4 ++--
> hw/virtio/vhost-user-fs.c | 4 ++--
>
On 5/23/23 06:59, Weiwei Li wrote:
Reduce reliance on absolute values by using true pc difference for
gen_pc_plus_diff() to prepare for PC-relative translation.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/insn_trans/trans_rvi.c.inc | 6 ++
On 5/23/23 06:59, Weiwei Li wrote:
Reduce reliance on absolute values(by passing pc difference) to
prepare for PC-relative translation.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/insn_trans/trans_privileged.c.inc | 2 +-
target/riscv/insn_trans/trans_rvi.c.inc
On Tue, Apr 18, 2023 at 05:21:28PM +0100, Alex Bennée wrote:
> I'm still not sure how I achieve by use case of the parent class
> defining the following properties:
>
> static Property vud_properties[] = {
> DEFINE_PROP_CHR("chardev", VHostUserDevice, chardev),
>
On 5/23/23 06:59, Weiwei Li wrote:
Reduce reliance on absolute value to prepare for PC-relative translation.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/insn_trans/trans_rvi.c.inc | 4 ++--
target/riscv/translate.c| 8 +---
2 files changed, 7
On 5/23/23 06:59, Weiwei Li wrote:
Use cur_insn_len to store the length of the current instruction to
prepare for PC-relative translation.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/translate.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
Instead of computing an artifical "class" bitmask then
converting that to the fprf value, compute the final
value from the start.
Reorder the tests to check the most likely cases first.
Signed-off-by: Richard Henderson
---
target/ppc/fpu_helper.c | 78 -
On 5/23/23 08:02, David Hildenbrand wrote:
The following changes since commit 886c0453cbf10eebd42a9ccf89c3e46eb389c357:
Merge tag 'pull-qapi-2023-05-17-v2' ofhttps://repo.or.cz/qemu/armbru into
staging (2023-05-22 15:54:21 -0700)
are available in the Git repository at:
The function is unused since commit
bdad3654d3c55f478e538037d9eccd204e5fc8ee ('hw/arm/nseries: Remove
invalid/unnecessary n8x0_uart_setup()').
Signed-off-by: Bernhard Beschow
Acked-by: Michael S. Tsirkin
Reviewed-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
---
The attribute isn't used since commit 5c9736789b79ea49cd236ac326f0a414f63b1015
"i82378: Cleanup implementation".
Signed-off-by: Bernhard Beschow
Acked-by: Michael S. Tsirkin
Reviewed-by: Mark Cave-Ayland
---
hw/isa/i82378.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/isa/i82378.c
Both TYPE_KVM_I8254 and TYPE_I8254 have their own but same implementation of
the "iobase" property. The storage for the property already resides in
PITCommonState, so also move the property definition there.
Signed-off-by: Bernhard Beschow
Acked-by: Michael S. Tsirkin
Reviewed-by: Mark
This series:
* Removes dead code from omap_uart and i82378
* Resolves redundant code in the i8254 timer devices
v3:
* Drop TYPE_ISA_PARALLEL since they became obsolete by
https://lore.kernel.org/qemu-devel/20230522115014.1110840-9-th...@redhat.com/
v2:
* Export ParallelState and
23.05.2023 10:31, Jason Wang wrote:
https://github.com/jasowang/qemu.git tags/net-pull-request
I might be wrong but it looks like besides the rtl8139 fix which went
to -stable already, and "e1000e: Fix tx/rx counters" change which has
been agreed upon before, there are a few other changes
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