On 26/06/2023 17.25, Richard Henderson wrote:
On 6/26/23 16:54, Christian Borntraeger wrote:
Am 26.06.23 um 15:21 schrieb Thomas Huth:
diff --git a/pc-bios/s390-ccw/start.S b/pc-bios/s390-ccw/start.S
index 29b0a9ece0..47ef6e8aa8 100644
--- a/pc-bios/s390-ccw/start.S
+++ b/pc-bios/s390-ccw/sta
On 6/26/23 23:59, Alex Bennée wrote:
We can return XKB_MOD_INVALID which rightly gets flagged by sanitisers
as an overly wide shift attempt.
Signed-off-by: Alex Bennée
---
qemu-keymap.c | 24
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git a/qemu-keymap.
On 26/06/2023 23.59, Alex Bennée wrote:
We can return XKB_MOD_INVALID which rightly gets flagged by sanitisers
as an overly wide shift attempt.
Signed-off-by: Alex Bennée
---
qemu-keymap.c | 24
1 file changed, 16 insertions(+), 8 deletions(-)
Reviewed-by: Thomas H
It seems it broke the "mac99" and powernv10 machines, using the
qemu-ppc-boot images which are mostly buildroot. See below for logs.
Adding Mark for further testing on Mac OS.
Mac OS 9.2 fails to boot with a popup saying :
Sorry, a system error occured.
"Soun
On 15/05/2023 16:11, Markus Armbruster wrote:
This reverts commit 1881f336a33a8a99cb17ab1c57ed953682e8e107.
This commit breaks "-drive if=pflash,readonly=on,file=image.iso". It
claims to merely replace an open-coded version of blk_name() by a
call, but that's not the case. Sorry for the incon
On 22/06/2023 13:26, Mark Cave-Ayland wrote:
On 21/06/2023 19:05, Richard Henderson wrote:
Changes from v1:
* Split into teeny weeny pieces.
* It turns out the sparc_tr_tb_stop hunk of v1 was buggy,
in that things that are not simple branches use DYNAMIC_PC,
e.g. the RETT (ret
On 6/9/2023 7:32 AM, Eugenio Perez Martin wrote:
On Fri, Jun 9, 2023 at 12:39 AM Si-Wei Liu wrote:
On 6/7/23 01:08, Eugenio Perez Martin wrote:
On Wed, Jun 7, 2023 at 12:43 AM Si-Wei Liu wrote:
Sorry for reviving this old thread, I lost the best timing to follow up
on this while I was on
On 23/06/2023 19:30, Henrik Carlqvist wrote:
SUN Type 4, 5 and 5c keyboards have dip switches to choose the language layout
of the keyboard. Solaris makes an ioctl to query the value of the dipswitches
and uses that value to select keyboard layout. Also the SUN bios like the one
in the file ss5
On 6/26/23 18:54, Peter Maydell wrote:
At the moment:
* aarch64_a64fx_initfn() calls aarch64_add_sve_properties()
* aarch64_max_tcg_initfn() calls all of
aarch64_add_pauth_properties(), aarch64_add_sve_properties(),
aarch64_add_sme_properties()
and it happens that (ignoring 'max') we
The icount-based QEMU_CLOCK_VIRTUAL runs ahead of the RT clock at times.
When warping, it is possible it is still ahead at the end of the warp,
which causes icount adaptive mode to adjust it backward. This can result
in the machine observing time going backwards.
Prevent this by clamping adaptive
On 6/26/2023 9:15 PM, Igor Mammedov wrote:
On Fri, 16 Jun 2023 11:23:09 +0800
Tao Su wrote:
From: Lei Wang
Latest stepping (8) of SapphireRapids has bit 13, 14 and 15 of
MSR_IA32_ARCH_CAPABILITIES enabled, which are related to some security
fixes.
Add version 2 of SapphireRapids CPU model w
On 6/26/2023 8:56 PM, Igor Mammedov wrote:
On Fri, 16 Jun 2023 11:23:10 +0800
Tao Su wrote:
From: Qian Wen
Emerald Rapids (EMR) is the next generation of Xeon server processor
after Sapphire Rapids (SPR).
Currently, regarding the feature set that can be exposed to guest, there
isn't any one
On 6/27/23 05:38, Alberto Garcia wrote:
On Sun 25 Jun 2023 04:56:29 PM +08, zhenwei pi wrote:
void throttle_timers_attach_aio_context(ThrottleTimers *tt,
AioContext *new_context)
{
-tt->timers[THROTTLE_TIMER_READ] =
-aio_timer_new(new_
On 6/27/23 05:24, Alberto Garcia wrote:
On Sun 25 Jun 2023 04:56:27 PM +08, zhenwei pi wrote:
Use enum ThrottleTimerType instead of number index.
+typedef enum {
+THROTTLE_TIMER_READ = 0,
+THROTTLE_TIMER_WRITE,
+THROTTLE_TIMER_MAX
+} ThrottleTimerType;
If you're doing this I
> On 26-Jun-2023, at 9:23 PM, Michael Tokarev wrote:
>
> 26.06.2023 15:30, Michael S. Tsirkin wrote:
>> From: Ani Sinha
>> When a peer nic is still attached to the vdpa backend, it is too early to
>> free
>> up the vhost-net and vdpa structures. If these structures are freed here,
>> then
>
On Mon, Jun 26, 2023 at 03:03:12PM +0200, Igor Mammedov wrote:
> On Fri, 16 Jun 2023 11:23:07 +0800
> Tao Su wrote:
>
> > MCDT_NO bit indicates HW contains the security fix and doesn't need to
> > be mitigated to avoid data-dependent behaviour for certain instructions.
> > It needs no hypervisor
On Mon, Jun 26, 2023 at 02:39:15PM +0200, Igor Mammedov wrote:
> On Fri, 16 Jun 2023 11:23:05 +0800
> Tao Su wrote:
>
> > Considering the case of FEAT_7_1_EAX being 0 and FEAT_7_1_EDX being
> > non-zero,
> Can you clarify when/why that happens?
When start a VM on GraniteRapids using '-cpu host',
>-Original Message-
>From: Joao Martins
>Sent: Monday, June 26, 2023 6:19 PM
>To: Avihai Horon ; Duan, Zhenzhong
>
>Cc: alex.william...@redhat.com; c...@redhat.com; Peng, Chao P
>; qemu-devel@nongnu.org
>Subject: Re: [PATCH v3 3/3] vfio/migration: vfio/migration: Refactor and fix
>print
On Mon, Jun 26, 2023 at 9:17 PM Ilya Maximets wrote:
>
> On 6/26/23 08:32, Jason Wang wrote:
> > On Sun, Jun 25, 2023 at 3:06 PM Jason Wang wrote:
> >>
> >> On Fri, Jun 23, 2023 at 5:58 AM Ilya Maximets wrote:
> >>>
> >>> AF_XDP is a network socket family that allows communication directly
> >>>
>-Original Message-
>From: Avihai Horon
>Sent: Monday, June 26, 2023 5:35 PM
>To: Duan, Zhenzhong ; qemu-
>de...@nongnu.org
>Cc: alex.william...@redhat.com; c...@redhat.com; Martins, Joao
>; Peng, Chao P
>Subject: Re: [PATCH v3 3/3] vfio/migration: vfio/migration: Refactor and fix
>prin
>-Original Message-
>From: Joao Martins
>Sent: Monday, June 26, 2023 6:08 PM
>To: Duan, Zhenzhong
>Cc: alex.william...@redhat.com; c...@redhat.com; qemu-devel@nongnu.org;
>avih...@nvidia.com; Peng, Chao P
>Subject: Re: [PATCH v3 1/3] vfio/pci: Fix resource leak in vfio_realize
>
>On 26/0
Hi Salil,
On 6/26/23 21:42, Salil Mehta wrote:
From: Shaoqin Huang
Sent: Monday, June 26, 2023 7:49 AM
To: qemu-devel@nongnu.org; qemu-...@nongnu.org
Cc: oliver.up...@linux.dev; Salil Mehta ;
james.mo...@arm.com; gs...@redhat.com; Shaoqin Huang ;
Cornelia Huck ; k...@vger.kernel.org; Michael S.
Set vc->gfx.guest_fb.dmabuf to NULL to prevent any further access
to it after the dmabuf is released.
v2: move declaration of vc inside ifdef
Cc: Gerd Hoffmann
Cc: Marc-André Lureau
Cc: Vivek Kasireddy
Signed-off-by: Dongwon Kim
---
ui/gtk.c | 5 +
1 file changed, 5 insertions(+)
diff -
On 2023/6/26 21:16, chenyuhui (A) wrote:
>
> On 2023/6/21 22:22, Fabiano Rosas wrote:
>> Jianguo Zhang via writes:
>>
>>> From: Yuhui Chen
>>>
>>> There is a coredump while trying to destroy mutex when
>>> p->running is false but p->mutex is not unlock.
>>> Make sure all mutexes has been rele
Respond with VIRTIO_GPU_RESP_ERR_OUT_OF_MEMORY if it fails to create
an udmabuf for the blob resource.
v2: consolidated return statments and removed an unnecessary style change
Cc: Gerd Hoffmann
Cc: Marc-André Lureau
Cc: Vivek Kasireddy
Signed-off-by: Dongwon Kim
---
hw/display/virtio-gpu.c
On Mon Jun 26, 2023 at 9:09 PM AEST, Paolo Bonzini wrote:
> On Mon, Jun 26, 2023 at 1:08 PM Paolo Bonzini wrote:
> > Queued, thanks.
>
> Hmm, almost, can you provide the Signed-off-by?
Sure, give me a bit and I'll make up a better changelog and patch.
Thanks,
Nick
On Mon Jun 26, 2023 at 11:35 PM AEST, Cédric Le Goater wrote:
> On 6/23/23 14:37, Cédric Le Goater wrote:
> > On 6/23/23 11:10, Peter Maydell wrote:
> >> On Fri, 23 Jun 2023 at 09:21, Nicholas Piggin wrote:
> >>>
> >>> ppc has always silently ignored access to real (physical) addresses
> >>> with
Hi,
this series reorder TCG specific code in order to easily
build a KVM-only binary. sysemu specific code is also
moved around, to help noticing invalid uses from user
emulation. Last patch adds a new job to our CI to avoid
this to bitrot.
Please review,
Phil.
Philippe Mathieu-Daudé (16):
ta
Signed-off-by: Philippe Mathieu-Daudé
---
target/riscv/cpu.h| 2 +-
target/riscv/{ => sysemu}/debug.h | 0
target/riscv/cpu_helper.c | 2 +-
target/riscv/{ => sysemu}/debug.c | 0
target/riscv/meson.build | 4
target/riscv/sysemu/meson.build | 1 +
6 files
Signed-off-by: Philippe Mathieu-Daudé
---
target/riscv/translate.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 8a33da811e..bd33bc3f51 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -30,7 +30,6 @@
#include "
Move TCG/sysemu-specific code and restrict the corresponding
prototypes to TCG, adapting meson rules.
Signed-off-by: Philippe Mathieu-Daudé
---
RFC due to riscv_cpu_get_phys_page_debug()
target/riscv/cpu.h | 15 +-
target/riscv/cpu_helper.c| 745 --
Move sysemu-specific files to the a new 'sysemu' sub-directory,
adapt meson rules.
Signed-off-by: Philippe Mathieu-Daudé
---
target/riscv/cpu.h | 2 +-
target/riscv/{ => sysemu}/instmap.h| 0
target/riscv/{ => sysemu}/kvm_riscv.h | 0
target/riscv/{ => sys
Add a new job to cross-build the riscv64 target without
the TCG accelerator (IOW: only KVM accelerator enabled).
Signed-off-by: Philippe Mathieu-Daudé
---
.gitlab-ci.d/crossbuilds.yml | 8
1 file changed, 8 insertions(+)
diff --git a/.gitlab-ci.d/crossbuilds.yml b/.gitlab-ci.d/crossbui
These fields shouldn't be accessed when KVM is not available.
Restrict the KVM timer migration state. Rename the KVM timer
post_load() handler accordingly, because cpu_post_load() is
too generic.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Daniel Henrique Barboza
---
target/riscv/cpu.h
Signed-off-by: Philippe Mathieu-Daudé
---
target/riscv/cpu.h | 3 +++
target/riscv/cpu.c | 11 +++
2 files changed, 14 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 5945e13fe0..8f16655041 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -474,7 +474,
Signed-off-by: Philippe Mathieu-Daudé
---
target/riscv/cpu_helper.c| 859 +-
target/riscv/sysemu/cpu_helper.c | 863 +++
target/riscv/sysemu/meson.build | 1 +
3 files changed, 865 insertions(+), 858 deletions(-)
create mode 1006
We want to extract TCG-specific code from debug.c, but some
functions call get_trigger_type() / do_trigger_action().
Expose these prototypes in "debug.h".
Signed-off-by: Philippe Mathieu-Daudé
---
target/riscv/debug.h | 4
target/riscv/debug.c | 5 ++---
2 files changed, 6 insertions(+), 3
Move TCG-specific files to the a new 'tcg' sub-directory. Add
stubs for riscv_cpu_[get/set]_fflags and riscv_raise_exception().
Adapt meson rules.
Signed-off-by: Philippe Mathieu-Daudé
---
target/riscv/{ => tcg}/XVentanaCondOps.decode | 0
target/riscv/{ => tcg}/insn16.decode | 0
tar
Signed-off-by: Philippe Mathieu-Daudé
---
target/riscv/cpu_helper.c| 83 --
target/riscv/tcg/cpu.c | 97
target/riscv/tcg/meson.build | 1 +
3 files changed, 98 insertions(+), 83 deletions(-)
create mode 100644 target/ri
We want to extract TCG/sysemu-specific code from cpu_helper.c,
but some functions call riscv_cpu_pending_to_irq(). Expose the
prototype in "internals.h".
Signed-off-by: Philippe Mathieu-Daudé
---
target/riscv/internals.h | 4
target/riscv/cpu_helper.c | 6 +++---
2 files changed, 7 inserti
Extract TCG-specific code from debug.c to tcg/sysemu/debug.c,
restrict the prototypes to TCG, adapt meson rules.
Signed-off-by: Philippe Mathieu-Daudé
---
target/riscv/debug.h| 2 +
target/riscv/debug.c| 148 -
target/riscv/tcg/sysemu/deb
riscv_cpu_do_interrupt() is not reachable on user emulation.
Signed-off-by: Philippe Mathieu-Daudé
---
target/riscv/cpu.h| 5 +++--
target/riscv/cpu_helper.c | 7 ++-
2 files changed, 5 insertions(+), 7 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 83a9a965
Signed-off-by: Philippe Mathieu-Daudé
---
target/riscv/cpu.c| 8 +---
target/riscv/cpu_helper.c | 2 ++
target/riscv/csr.c| 2 ++
3 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 4035fe0e62..175dbc9826 100644
--- a/ta
We only build for 32/64-bit hosts, so TCG is required for
128-bit targets.
Signed-off-by: Philippe Mathieu-Daudé
---
target/riscv/cpu.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 175dbc9826..7f281cdcf6 100644
---
On Tue Jun 27, 2023 at 7:45 AM AEST, Cédric Le Goater wrote:
> On 6/26/23 14:26, Michael Tokarev wrote:
> > 26.06.2023 08:56, Cédric Le Goater wrote:
> >> From: Nicholas Piggin
> >>
> >> Fix missing env->ca restore when going from L2 back to the host.
> >>
> >> Fixes: 120f738a467 ("spapr: implemen
The lack of SVE memory instrumentation has been an omission in plugin
handling since it was introduced. Fortunately we can utilise the
probe_* functions to force all all memory access to follow the slow
path. We do this by checking the access type and presence of plugin
memory callbacks and if set
As it is today it's not possible to use '-cpu host' if the RISC-V host
has RVH enabled. This is the resulting error:
$ sudo ./qemu/build/qemu-system-riscv64 \
-machine virt,accel=kvm -m 2G -smp 1 \
-nographic -snapshot -kernel ./guest_imgs/Image \
-initrd ./guest_imgs/rootfs_kvm_riscv
From: Richard Henderson
This is a perfectly natural occurrence for x86 "rep movb",
where the "rep" prefix forms a counted loop of the one insn.
During the tests/tcg/multiarch/memory test, this logging is
triggered over 35 times. Within the context of cross-i386-tci
build, which is already s
The absence of a satp mode in riscv_host_cpu_init() is causing the
following error:
$ sudo ./qemu/build/qemu-system-riscv64 -machine virt,accel=kvm \
-m 2G -smp 1 -nographic -snapshot \
-kernel ./guest_imgs/Image \
-initrd ./guest_imgs/rootfs_kvm_riscv64.img \
-append "earlycon=s
Using QOM correctly is increasingly important to maintaining a modern
code base. However the current documentation skips some important
concepts before launching into a simple example. Lets:
- at least mention properties
- mention TYPE_OBJECT and TYPE_DEVICE
- talk about why we have realize/
KVM-specific properties are being created inside target/riscv/kvm.c. But
at this moment we're gathering all the remaining properties from TCG and
adding them as is when running KVM. This creates a situation where
non-KVM properties are setting flags to 'true' due to its default
settings (e.g. Zawr
It was hard to track down this leak as it was an internal allocation
by glib and the backtraces did not give much away. The autofree was
freeing the allocation with g_free() but not taking care of the
individual strings. They should have been freed with g_strfreev()
instead.
Searching the glib sou
After changing user validation for mvendorid/marchid/mimpid to guarantee
that the value is validated on user input time, coupled with the work in
fetching KVM default values for them by using a scratch CPU, we're
certain that the values in cpu->cfg.(mvendorid|marchid|mimpid) are
already good to be
Certain validations, such as the validations done for the machine IDs
(mvendorid/marchid/mimpid), are done before starting the CPU.
Non-dynamic (named) CPUs tries to match user input with a preset
default. As it is today we can't prefetch a KVM default for these cases
because we're only able to rea
Update to commit ac9a78681b92 ("Linux 6.4-rc1").
Signed-off-by: Daniel Henrique Barboza
Acked-by: Alistair Francis
---
include/standard-headers/linux/const.h| 2 +-
include/standard-headers/linux/virtio_blk.h | 18 +++
.../standard-headers/linux/virtio_config.h| 6 +++
inclu
From: Philippe Mathieu-Daudé
Per commit 067109a11c ("docs/devel: mention the spacing requirement
for QOM"):
For a storage structure the first declaration should always be
called “parent_obj” and for a class structure the first member
should always be called “parent_class”
Adapt the QOM rS
Next patch will add KVM specific user properties for both MISA and
multi-letter extensions. For MISA extensions we want to make use of what
is already available in misa_ext_cfgs[] to avoid code repetition.
misa_ext_info_arr[] array will hold name and description for each MISA
extension that misa_e
At this moment we're retrieving env->misa_ext during
kvm_arch_init_cpu(), leaving env->misa_ext_mask behind.
We want to set env->misa_ext_mask, and we want to set it as early as
possible. The reason is that we're going to use it in the validation
process of the KVM MISA properties we're going to a
Fix up the kerneldoc markup and start documenting the various fields
in QDEV related structures. This involved:
- moving overall description to a DOC: comment at top
- fixing various markup issues for types and structures
- adding missing Return: statements
- adding some typedefs to hide QLIST
Give an overview of the most useful bits of the devel documentation to
read depending on what the developer wants to do.
Reviewed-by: Peter Maydell
Reviewed-by: Richard Henderson
Signed-off-by: Alex Bennée
Message-Id: <20230619171437.357374-2-alex.ben...@linaro.org>
---
v2
- removed excessiv
There are 2 places in which we need to get a pointer to a certain
property of the cpu->cfg struct based on property offset. Next patch
will add a couple more.
Create a helper to avoid repeating this code over and over.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
---
target
Allow 'marchid' and 'mimpid' to also be initialized in
kvm_riscv_init_machine_ids().
After this change, the handling of mvendorid/marchid/mimpid for the
'host' CPU type will be equal to what we already have for TCG named
CPUs, i.e. the user is not able to set these values to a different val
than t
If we don't set a proper cbom_blocksize|cboz_blocksize in the FDT the
Linux Kernel will fail to detect the availability of the CBOM/CBOZ
extensions, regardless of the contents of the 'riscv,isa' DT prop.
The FDT is being written using the cpu->cfg.cbom|z_blocksize attributes,
so let's expose them
riscv_isa_string_ext() is being used by riscv_isa_string(), which is
then used by boards to retrieve the 'riscv,isa' string to be written in
the FDT. All this happens after riscv_cpu_realize(), meaning that we're
already past riscv_cpu_validate_set_extensions() and, more important,
riscv_cpu_disabl
Mention that QOM-ified devices already have support for registering
the description.
Reviewed-by: Juan Quintela
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Acked-by: Peter Xu
Signed-off-by: Alex Bennée
Message-Id: <20230619171437.357374-3-alex.ben...@linaro.org>
---
in
The old g_memdup is deprecated, use the replacement.
Message-Id: <20230623122100.1640995-21-alex.ben...@linaro.org>
Reviewed-by: Richard Henderson
Signed-off-by: Alex Bennée
---
contrib/plugins/lockstep.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/contrib/plugins/lockst
Lets try and keep the overview of the sub-system digestible by
splitting the core API stuff into a separate file. As QOM and QDEV
work together we should also try and enumerate the qdev_ functions.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Alex Bennée
Message-Id: <20230619171437.357374-
Our design philosophy with KVM properties can be resumed in two main
decisions based on KVM interface availability and what the user wants to
do:
- if the user disables an extension that the host KVM module doesn't
know about (i.e. it doesn't implement the kvm_get_one_reg() interface),
keep bootin
'marchid' shouldn't be set to a different value as previously set for
named CPUs.
For all other CPUs it shouldn't be freely set either - the spec requires
that 'marchid' can't have the MSB (most significant bit) set and every
other bit set to zero, i.e. 0x8000 is an invalid 'marchid' value for
We're going to change the handling of mvendorid/marchid/mimpid by the
KVM driver. Since these are always present in all CPUs let's put the
same validation for everyone.
It doesn't make sense to allow 'mvendorid' to be different than it
is already set in named (vendor) CPUs. Generic (dynamic) CPUs
Hi,
This version has a change requested by Andrew in patch 16.
All patches aside from patch 16 are acked/reviewed.
Changes from v3:
- patch 16:
- error out with a "extension is not available with KVM"
- v3 link: https://lists.gnu.org/archive/html/qemu-devel/2023-06/msg04575.html
Daniel Henri
Using all TCG user properties in KVM is tricky. First because KVM
supports only a small subset of what TCG provides, so most of the
cpu->cfg flags do nothing for KVM.
Second, and more important, we don't have a way of telling if any given
value is an user input or not. For TCG this has a small imp
Following the same logic used with 'mvendorid' let's also restrict
'mimpid' for named CPUs. Generic CPUs keep setting the value freely.
Note that we're getting rid of the default RISCV_CPU_MARCHID value. The
reason is that this is not a good default since it's dynamic, changing
with with every QEM
An update to the clang tooling detects more issues with the code
including a memory leak from the g_string_new() allocation. Clean up
the code with g_autoptr and use ARRAY_SIZE while we are at it.
Signed-off-by: Alex Bennée
---
tests/qtest/fuzz/generic_fuzz.c | 11 ---
1 file changed, 4
This is a very bare bones set of dependencies for a minimal build of
QEMU. This will be useful for minimal cross-compile sanity check based
on things like Debian Sid where stuff isn't always in sync.
Message-Id: <20230623122100.1640995-16-alex.ben...@linaro.org>
Signed-off-by: Alex Bennée
---
v2
Let's add KVM user properties for the multi-letter extensions that KVM
currently supports: zicbom, zicboz, zihintpause, zbb, ssaia, sstc,
svinval and svpbmt.
As with MISA extensions, we're using the KVMCPUConfig type to hold
information about the state of each extension. However, multi-letter
exte
We're now ready to update the multi-letter extensions status for KVM.
kvm_riscv_update_cpu_cfg_isa_ext() is called called during vcpu creation
time to verify which user options changes host defaults (via the 'user_set'
flag) and tries to write them back to KVM.
Failure to commit a change to KVM i
We need this for the riscv64 and gcc-native mappings. As the older
alpine release has been dropped from the mappings we also need to bump
the version of alpine we use.
Message-Id: <20230623122100.1640995-13-alex.ben...@linaro.org>
Acked-by: Richard Henderson
Signed-off-by: Alex Bennée
---
tests
We can return XKB_MOD_INVALID which rightly gets flagged by sanitisers
as an overly wide shift attempt.
Signed-off-by: Alex Bennée
---
qemu-keymap.c | 24
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git a/qemu-keymap.c b/qemu-keymap.c
index 229866e004..8c80f
This keeps timing out on gitlab due to some qtests taking a long time.
As this is just ensuring the gcov machinery is working and not
attempting to be comprehensive lets skip qtest in this run.
Message-Id: <20230623122100.1640995-4-alex.ben...@linaro.org>
Reviewed-by: Richard Henderson
Signed-off
We still need to base this on Debian Sid until riscv64 is promoted to
a release architecture (or another distro provides a full cross
compile target). We use the new qemu-minimal project description to
avoid bringing in all the extra dependencies because every extra
package is another chance for si
When updating to the latest fedora the santizer found more leaks
inside xkbmap:
FAILED: pc-bios/keymaps/ar
/builds/stsquad/qemu/build-oss-fuzz/qemu-keymap -f pc-bios/keymaps/ar -l ara
=
==3604==ERROR: LeakSanitizer: detected m
From: Ani Sinha
When new dependencies and packages are added to containers, its important to
run CI container generation pipelines on gitlab to make sure that there are no
obvious conflicts between packages that are being added and those that are
already present. Running CI container pipelines wi
From: Marcin Juszkiewicz
Update prebuilt firmware images to have TF-A with FEAT_FGT support
enabled. This allowed us to enable test for "max" cpu in sbsa-ref
machine.
Signed-off-by: Marcin Juszkiewicz
Message-Id: <20230530152240.79160-1-marcin.juszkiew...@linaro.org>
Signed-off-by: Alex Bennée
From: Erik Skultety
Fedora 37 -> 38
Signed-off-by: Erik Skultety
Acked-by: Richard Henderson
Message-Id: <20230623122100.1640995-14-alex.ben...@linaro.org>
Message-Id:
[AJB: Dropped alpine (in prev commit), reflow commit msg]
Signed-off-by: Alex Bennée
---
tests/docker/dockerfiles/fedora-w
We recently missed a regression that should have been picked up by
check-tcg. This was because the libmem plugin is effectively a NOP if
the user doesn't specify the type to use.
Rather than changing the default behaviour add an additional expansion
so we can take this into account in future.
Mes
This is yet another make target you usually run in the top level of
the source directory.
Message-Id: <20230623122100.1640995-12-alex.ben...@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Alex Bennée
---
Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Running the fuzzer requires some hoop jumping and some problems only
show up in containers. This basically replicates the build-oss-fuzz
job from our CI so we can run in the same containers we use in CI.
Signed-off-by: Alex Bennée
---
tests/docker/test-fuzz | 28
1 f
We need a native compiler to build the hexagon codegen tools. In our
current images we already have a gcc as a side effect of a broken
dependency between gcovr and lcov but this will be fixed when we move
to bookworm. See
https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=987818 for details.
Update
As softfreeze is fast approaching I thought it would be work combining
my various trees into an omnibus series to ease the review and
merging.
The testing updates exposed a number of latent leaks that confused the
oss-fuzz jobs (hence the test-fuzz addition to help debug that). This
also includes
From: Daniel P. Berrangé
The coverage job wants to publish a coverage report on success, but the
tests might fail and in that case we need the meson logs for debugging.
Signed-off-by: Daniel P. Berrangé
Reviewed-by: Richard Henderson
Message-Id: <20230623122100.1640995-3-alex.ben...@linaro.org
From: Daniel P. Berrangé
If not set explicitly, gitlab assumes 'when: on_success" as the
publishing criteria for artifacts. This is reasonable if the
artifact is an output deliverable of the job. This is useless
if the artifact is a log file to be used for debugging job
failures.
This change mak
On 6/26/23 14:26, Michael Tokarev wrote:
26.06.2023 08:56, Cédric Le Goater wrote:
From: Nicholas Piggin
Fix missing env->ca restore when going from L2 back to the host.
Fixes: 120f738a467 ("spapr: implement nested-hv capability for the virtual
hypervisor")
Reviewed-by: Harsh Prateek Bora
S
On Sun 25 Jun 2023 04:56:29 PM +08, zhenwei pi wrote:
> void throttle_timers_attach_aio_context(ThrottleTimers *tt,
> AioContext *new_context)
> {
> -tt->timers[THROTTLE_TIMER_READ] =
> -aio_timer_new(new_context, tt->clock_type, SCALE_NS,
> -
On Sun 25 Jun 2023 04:56:30 PM +08, zhenwei pi wrote:
> Signed-off-by: zhenwei pi
Reviewed-by: Alberto Garcia
Berto
On Sun 25 Jun 2023 04:56:31 PM +08, zhenwei pi wrote:
> Operations on a crytpodev are considered as *write* only, the callback
> of read direction is never invoked. Use NULL instead of an unreachable
> path(cryptodev_backend_throttle_timer_cb on read direction).
>
> Signed-off-by: zhenwei pi
Revi
On Sun 25 Jun 2023 04:56:28 PM +08, zhenwei pi wrote:
> Use enum ThrottleTimerType instead in the throttle test codes.
>
> Signed-off-by: zhenwei pi
Reviewed-by: Alberto Garcia
Berto
On Sun 25 Jun 2023 04:56:27 PM +08, zhenwei pi wrote:
> Use enum ThrottleTimerType instead of number index.
> +typedef enum {
> +THROTTLE_TIMER_READ = 0,
> +THROTTLE_TIMER_WRITE,
> +THROTTLE_TIMER_MAX
> +} ThrottleTimerType;
If you're doing this I suppose you could also change 'bool i
I need advice on how to debug this.
One thing that stands out is uhci_irq().
It reads a u16 from the USBSTS register.
On the qemu side, this read is served from bmdma_read. Since the read
size is 2, the result is ~0, and uhci_irq() turns the controller off.
In other words, memory_region_ops_read
As softfreeze is fast approaching I thought it would be work combining
my various trees into an omnibus series to ease the review and
merging.
The testing updates exposed a number of latent leaks that confused the
oss-fuzz jobs (hence the test-fuzz addition to help debug that). This
also includes
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