Re: [PATCH 0/4] target/ppc: Fixes for instruction-related

On 6/20/23 18:40, Nicholas Piggin wrote: Because they got more complexities than I first thought, these patches are broken out from the bigger series here: https://lists.gnu.org/archive/html/qemu-ppc/2023-05/msg00425.html Since then I fixed the --disable-tcg compile bug reported by Anushree

Re: [PATCH v2] vdpa: Return -EINVAL if device ack is VIRTIO_NET_ERR

On Tue, Jun 27, 2023 at 10:36 PM Hawkins Jiawei wrote: > > According to VirtIO standard, "The class, command and > command-specific-data are set by the driver, > and the device sets the ack byte. > There is little it can do except issue a diagnostic > if ack is not VIRTIO_NET_OK." > > Therefore,

Re: [PATCH] net: add initial support for AF_XDP network backend

On Wed, Jun 28, 2023 at 6:45 AM Ilya Maximets wrote: > > On 6/27/23 04:54, Jason Wang wrote: > > On Mon, Jun 26, 2023 at 9:17 PM Ilya Maximets wrote: > >> > >> On 6/26/23 08:32, Jason Wang wrote: > >>> On Sun, Jun 25, 2023 at 3:06 PM Jason Wang wrote: > > On Fri, Jun 23, 2023 at 5:58 

RE: [PATCH 3/3] vfio/migration: Make VFIO migration non-experimental

> -Original Message- > From: Jason Gunthorpe [mailto:j...@nvidia.com] > Sent: 27 June 2023 13:30 > To: Cédric Le Goater > Cc: Avihai Horon ; Alex Williamson > ; Joao Martins ; > Juan Quintela ; Peter Xu ; > Leonardo Bras ; Zhenzhong Duan > ; Yishai Hadas ; Maor > Gottlieb ; Kirti

Re: [PATCH v3 0/4] hw/smbios: Cleanup topology related variables

On Mon, Jun 26, 2023 at 03:48:17PM +0200, Igor Mammedov wrote: > Date: Mon, 26 Jun 2023 15:48:17 +0200 > From: Igor Mammedov > Subject: Re: [PATCH v3 0/4] hw/smbios: Cleanup topology related variables > X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; x86_64-redhat-linux-gnu) > > On Tue, 20 Jun 2023

RE: [PATCH v3 3/3] vfio/migration: vfio/migration: Refactor and fix print of "Migration disabled"

>-Original Message- >From: Joao Martins >Sent: Tuesday, June 27, 2023 6:57 PM >To: Duan, Zhenzhong ; Avihai Horon > >Cc: alex.william...@redhat.com; c...@redhat.com; Peng, Chao P >; qemu-devel@nongnu.org >Subject: Re: [PATCH v3 3/3] vfio/migration: vfio/migration: Refactor and fix >print

Re: [PATCH v3 1/4] machine: Add helpers to get cores/threads per socket

On Mon, Jun 26, 2023 at 03:43:25PM +0200, Igor Mammedov wrote: > Date: Mon, 26 Jun 2023 15:43:25 +0200 > From: Igor Mammedov > Subject: Re: [PATCH v3 1/4] machine: Add helpers to get cores/threads per > socket > X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; x86_64-redhat-linux-gnu) > > On Tue, 20

Re: [PATCH v3 3/4] hw/smbios: Fix thread count in type4

On Mon, Jun 26, 2023 at 03:44:49PM +0200, Igor Mammedov wrote: > Date: Mon, 26 Jun 2023 15:44:49 +0200 > From: Igor Mammedov > Subject: Re: [PATCH v3 3/4] hw/smbios: Fix thread count in type4 > X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; x86_64-redhat-linux-gnu) > > On Tue, 20 Jun 2023 18:39:57

Re: [PATCH v2 3/4] target/ppc: Make checkstop actually stop the system

On Wed, 28 Jun 2023, Nicholas Piggin wrote: On Wed Jun 28, 2023 at 3:38 AM AEST, BALATON Zoltan wrote: On Tue, 27 Jun 2023, Nicholas Piggin wrote: checkstop state does not halt the system, interrupts continue to be serviced, and other CPUs run. Stop the machine with vm_stop(), and print a

Re: [PATCH] i386/WHPX: Fix error message when fail to set ProcessorCount

Hi Paolo Could I add you for this patch's review? Let me add more background of this cleanup: This patch is one of my cleanups of smp.cores. I am trying to introduce hybrid topology. in hybrid topology, different clusters will have different number of cores, so calling smp.cores directly in

Re: [PATCH v2 4/4] target/ppc: Implement attn instruction on BookS 64-bit processors

On Wed Jun 28, 2023 at 1:25 AM AEST, Fabiano Rosas wrote: > Nicholas Piggin writes: > > > attn is an implementation-specific instruction that on POWER (and G5/ > > 970) can be enabled with a HID bit (disabled = illegal), and executing > > it causes the host processor to stop and the service

Re: [PATCH v2 00/17] Support smp.clusters for x86

On Thu, Jun 22, 2023 at 04:14:44PM -0400, Michael S. Tsirkin wrote: > Date: Thu, 22 Jun 2023 16:14:44 -0400 > From: "Michael S. Tsirkin" > Subject: Re: [PATCH v2 00/17] Support smp.clusters for x86 > > On Mon, May 29, 2023 at 08:30:44PM +0800, Zhao Liu wrote: > > From: Zhao Liu > > > > Hi

Re: [PATCH v3 09/14] target/ppc: Move patching nip from exception handler to helper_scv

On Wed Jun 28, 2023 at 3:40 AM AEST, BALATON Zoltan wrote: > On Mon, 26 Jun 2023, Nicholas Piggin wrote: > > On Tue Jun 20, 2023 at 8:47 PM AEST, BALATON Zoltan wrote: > >> On Tue, 20 Jun 2023, Nicholas Piggin wrote: > >>> On Fri Jun 16, 2023 at 9:03 AM AEST, BALATON Zoltan wrote: > From:

Re: [PATCH v2 3/4] target/ppc: Make checkstop actually stop the system

On Wed Jun 28, 2023 at 3:38 AM AEST, BALATON Zoltan wrote: > On Tue, 27 Jun 2023, Nicholas Piggin wrote: > > checkstop state does not halt the system, interrupts continue to be > > serviced, and other CPUs run. > > > > Stop the machine with vm_stop(), and print a register dump too. > > > >

Re: [PATCH v5 11/19] target/riscv/cpu: add misa_ext_info_arr[]

On 6/27/23 18:29, Philippe Mathieu-Daudé wrote: On 27/6/23 18:31, Daniel Henrique Barboza wrote: Next patch will add KVM specific user properties for both MISA and multi-letter extensions. For MISA extensions we want to make use of what is already available in misa_ext_cfgs[] to avoid code

Re: [PATCH v5 01/19] target/riscv: skip features setup for KVM CPUs

On 6/27/23 18:19, Philippe Mathieu-Daudé wrote: Hi Daniel, On 27/6/23 18:31, Daniel Henrique Barboza wrote: As it is today it's not possible to use '-cpu host' if the RISC-V host has RVH enabled. This is the resulting error: $ sudo ./qemu/build/qemu-system-riscv64 \ -machine

Re: [PATCH] net: add initial support for AF_XDP network backend

On 6/27/23 10:56, Stefan Hajnoczi wrote: > Can multiple VMs share a host netdev by filtering incoming traffic > based on each VM's MAC address and directing it to the appropriate > XSK? If yes, then I think AF_XDP is interesting when SR-IOV or similar > hardware features are not available. Good

[PATCH] virtio-gpu: replace the surface with null surface when resetting

The primary guest scanout shows the booting screen right after reboot but additional guest displays (i.e. max_ouptuts > 1) will keep displaying the old frames until the guest virtio gpu driver gets initialized, which could cause some confusion. A better way is to to replace the surface with a

Re: [PATCH] net: add initial support for AF_XDP network backend

On 6/27/23 04:54, Jason Wang wrote: > On Mon, Jun 26, 2023 at 9:17 PM Ilya Maximets wrote: >> >> On 6/26/23 08:32, Jason Wang wrote: >>> On Sun, Jun 25, 2023 at 3:06 PM Jason Wang wrote: On Fri, Jun 23, 2023 at 5:58 AM Ilya Maximets wrote: > > AF_XDP is a network socket family

Re: [PATCH 00/16] target/riscv: Allow building without TCG (KVM-only so far)

On 27/6/23 20:54, Daniel Henrique Barboza wrote: Phil, Can you rebase this on top of Alistair's riscv-to-apply.next? https://github.com/alistair23/qemu/tree/riscv-to-apply.next There's a trivial conflict in patch 8 and a not so trivial conflict in patch 14 that I'd rather let you deal with

[PATCH] virtio-gpu: do not replace surface when scanout is disabled

Surface is replaced with a place holder whenever the surface res is unreferenced by the guest message. With this logic, there is very frequent switching between guest display and the place holder image, which is looking like a flickering display if the guest driver is designed to unref the current

Re: [PATCH v5 11/19] target/riscv/cpu: add misa_ext_info_arr[]

On 27/6/23 18:31, Daniel Henrique Barboza wrote: Next patch will add KVM specific user properties for both MISA and multi-letter extensions. For MISA extensions we want to make use of what is already available in misa_ext_cfgs[] to avoid code repetition. misa_ext_info_arr[] array will hold name

Re: [PATCH v5 02/19] hw/riscv/virt.c: skip 'mmu-type' FDT if satp mode not set

On 27/6/23 18:31, Daniel Henrique Barboza wrote: The absence of a satp mode in riscv_host_cpu_init() is causing the following error: $ sudo ./qemu/build/qemu-system-riscv64 -machine virt,accel=kvm \ -m 2G -smp 1 -nographic -snapshot \ -kernel ./guest_imgs/Image \ -initrd

Re: [PATCH v5 01/19] target/riscv: skip features setup for KVM CPUs

Hi Daniel, On 27/6/23 18:31, Daniel Henrique Barboza wrote: As it is today it's not possible to use '-cpu host' if the RISC-V host has RVH enabled. This is the resulting error: $ sudo ./qemu/build/qemu-system-riscv64 \ -machine virt,accel=kvm -m 2G -smp 1 \ -nographic -snapshot

Re: [RFC 2/7] hw/cxl/cxl-mailbox-utils: Add dynamic capacity region representative and mailbox command support

The 05/15/2023 14:58, Jonathan Cameron wrote: > On Thu, 11 May 2023 16:53:23 -0500 > Nathan Fontenot wrote: > > > On 5/11/23 12:56, Fan Ni wrote: > > > From: Fan Ni > > > > > > Per cxl spec 3.0, add dynamic capacity region representative based on > > > Table 8-126 and extend the cxl type3

Re: [PATCH v3 03/36] gitlab: reduce testing scope of check-gcov

On 27/6/23 18:09, Alex Bennée wrote: This keeps timing out on gitlab due to some qtests taking a long time. As this is just ensuring the gcov machinery is working and not attempting to be comprehensive lets skip qtest in this run. Message-Id: <20230623122100.1640995-4-alex.ben...@linaro.org>

Re: [PATCH v3 08/36] tests/qtests: clean-up and fix leak in generic_fuzz

On 27/6/23 18:09, Alex Bennée wrote: An update to the clang tooling detects more issues with the code including a memory leak from the g_string_new() allocation. Clean up the code to avoid the allocation and use ARRAY_SIZE while we are at it. Signed-off-by: Alex Bennée ---

Re: [PATCH v3 12/36] tests/lcitool: Bump fedora container versions

On 27/6/23 18:09, Alex Bennée wrote: From: Erik Skultety Fedora 37 -> 38 Signed-off-by: Erik Skultety Acked-by: Richard Henderson Message-Id: <20230623122100.1640995-14-alex.ben...@linaro.org> Message-Id: [AJB: Dropped alpine (in prev commit), reflow commit msg] Signed-off-by: Alex Bennée

Re: [PATCH v3 16/36] tests/avocado: update firmware to enable sbsa-ref/max

On 27/6/23 18:09, Alex Bennée wrote: From: Marcin Juszkiewicz Update prebuilt firmware images to have TF-A with FEAT_FGT support enabled. This allowed us to enable test for "max" cpu in sbsa-ref machine. Signed-off-by: Marcin Juszkiewicz Message-Id:

Re: [PATCH v3 19/36] plugins: update lockstep to use g_memdup2

On 27/6/23 18:09, Alex Bennée wrote: The old g_memdup is deprecated, use the replacement. Message-Id: <20230623122100.1640995-21-alex.ben...@linaro.org> Reviewed-by: Richard Henderson Signed-off-by: Alex Bennée --- contrib/plugins/lockstep.c | 2 +- 1 file changed, 1 insertion(+), 1

Re: [PATCH v3 35/36] docs: Document security implications of debugging

On 27/6/23 18:09, Alex Bennée wrote: From: Ilya Leoshkevich Now that the GDB stub explicitly implements reading host files (note that it was already possible by changing the emulated code to open and read those files), concerns may arise that it undermines security. Document the status quo,

Re: [PATCH v3 32/36] gdbstub: Expose gdb_get_process() and gdb_get_first_cpu_in_process()

On 27/6/23 18:09, Alex Bennée wrote: From: Ilya Leoshkevich These functions will be needed by user-target.c in order to retrieve the name of the executable. Reviewed-by: Alex Bennée Signed-off-by: Ilya Leoshkevich Message-Id: <20230621203627.1808446-5-...@linux.ibm.com> Signed-off-by: Alex

Re: [Qemu RFC 0/7] Early enabling of DCD emulation in Qemu

The 05/15/2023 14:00, Jonathan Cameron wrote: > On Thu, 11 May 2023 17:56:40 + > Fan Ni wrote: > > > Since the early draft of DCD support in kernel is out > > (https://lore.kernel.org/linux-cxl/20230417164126.GA1904906@bgt-140510-bm03/T/#t), > > this patch series provide dcd emulation in

Re: [PATCH 0/4] target/ppc: Catch invalid real address accesses

On 27/06/2023 13:41, Cédric Le Goater wrote: On 6/27/23 14:05, Howard Spoelstra wrote: On Tue, Jun 27, 2023 at 1:24 PM Mark Cave-Ayland > wrote:     On 27/06/2023 11:28, Howard Spoelstra wrote: > On Tue, Jun 27, 2023 at 10:15 AM Mark Cave-Ayland

Re: [PATCH 0/4] target/ppc: Catch invalid real address accesses

On 27/06/2023 13:03, Cédric Le Goater wrote: Mac OS 9.2 fails to boot with a popup saying : Sorry, a system error occured. "Sound Manager"    address error To temporarily turn off extensions, restart and hold down the shift key Darwin and Mac OSX

[PATCH] docs/migration: Update postcopy bits

We have postcopy recovery but not reflected in the document, do an update for that. Add a very small section on postcopy preempt. Touch up the pagemap section, dropping the unsent map because it's already been dropped in the source code in commit 1e7cf8c323 ("migration/postcopy: unsentmap is not

Re: [PATCH v4 24/24] nbd/server: Add FLAG_PAYLOAD support to CMD_BLOCK_STATUS

On 08.06.23 16:56, Eric Blake wrote: Allow a client to request a subset of negotiated meta contexts. For example, a client may ask to use a single connection to learn about both block status and dirty bitmaps, but where the dirty bitmap queries only need to be performed on a subset of the disk;

Re: [PATCH 00/16] target/riscv: Allow building without TCG (KVM-only so far)

Phil, Can you rebase this on top of Alistair's riscv-to-apply.next? https://github.com/alistair23/qemu/tree/riscv-to-apply.next There's a trivial conflict in patch 8 and a not so trivial conflict in patch 14 that I'd rather let you deal with it. Also, can you take a look at these KVM patches

Re: [RFC PATCH 6/9] ui/gtk: Add a new parameter to assign connectors/monitors to GFX VCs

Hi Markus, So I've worked on the description of this param. Can you check if this new version looks ok? # @connectors:  List of physical monitor/connector names where the GTK #           windows containing the respective graphics virtual consoles (VCs) #   are to be placed. Index of

[PATCH v6 09/15] target/riscv: Add Zvkned ISA extension support

From: Nazar Kazakov This commit adds support for the Zvkned vector-crypto extension, which consists of the following instructions: * vaesef.[vv,vs] * vaesdf.[vv,vs] * vaesdm.[vv,vs] * vaesz.vs * vaesem.[vv,vs] * vaeskf1.vi * vaeskf2.vi Translation functions are defined in

[PATCH v6 11/15] target/riscv: Add Zvksh ISA extension support

From: Lawrence Hunter This commit adds support for the Zvksh vector-crypto extension, which consists of the following instructions: * vsm3me.vv * vsm3c.vi Translation functions are defined in `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in `target/riscv/vcrypto_helper.c`.

[PATCH v6 15/15] target/riscv: Add Zvksed ISA extension support

This commit adds support for the Zvksed vector-crypto extension, which consists of the following instructions: * vsm4k.vi * vsm4r.[vv,vs] Translation functions are defined in `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in `target/riscv/vcrypto_helper.c`. Signed-off-by:

[PATCH v6 08/15] target/riscv: Add Zvbb ISA extension support

From: Dickon Hood This commit adds support for the Zvbb vector-crypto extension, which consists of the following instructions: * vrol.[vv,vx] * vror.[vv,vx,vi] * vbrev8.v * vrev8.v * vandn.[vv,vx] * vbrev.v * vclz.v * vctz.v * vcpop.v * vwsll.[vv,vx,vi] Translation functions are defined in

[PATCH v6 13/15] crypto: Create sm4_subword

Allows sharing of sm4_subword between different targets. Signed-off-by: Max Chou Reviewed-by: Frank Chang Reviewed-by: Richard Henderson Signed-off-by: Max Chou --- include/crypto/sm4.h | 8 target/arm/tcg/crypto_helper.c | 10 ++ 2 files changed, 10

[PATCH v6 14/15] crypto: Add SM4 constant parameter CK

Adds sm4_ck constant for use in sm4 cryptography across different targets. Signed-off-by: Max Chou Reviewed-by: Frank Chang Signed-off-by: Max Chou --- crypto/sm4.c | 10 ++ include/crypto/sm4.h | 1 + 2 files changed, 11 insertions(+) diff --git a/crypto/sm4.c

[PATCH v6 10/15] target/riscv: Add Zvknh ISA extension support

From: Kiran Ostrolenk This commit adds support for the Zvknh vector-crypto extension, which consists of the following instructions: * vsha2ms.vv * vsha2c[hl].vv Translation functions are defined in `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in

Re: [PULL 10/33] ui/gtk: set the area of the scanout texture correctly

27.06.2023 16:02, marcandre.lur...@redhat.com wrote: From: Dongwon Kim x and y offsets and width and height of the scanout texture is not correctly configured in case guest scanout frame is dmabuf. Is this a -stable material too? Thanks, /mjt

[PATCH v6 05/15] target/riscv: Move vector translation checks

From: Nazar Kazakov Move the checks out of `do_opiv{v,x,i}_gvec{,_shift}` functions and into the corresponding macros. This enables the functions to be reused in proceeding commits without check duplication. Signed-off-by: Nazar Kazakov Reviewed-by: Richard Henderson Reviewed-by: Weiwei Li

[PATCH v6 12/15] target/riscv: Add Zvkg ISA extension support

From: Nazar Kazakov This commit adds support for the Zvkg vector-crypto extension, which consists of the following instructions: * vgmul.vv * vghsh.vv Translation functions are defined in `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in `target/riscv/vcrypto_helper.c`.

[PATCH v6 04/15] target/riscv: Add Zvbc ISA extension support

From: Lawrence Hunter This commit adds support for the Zvbc vector-crypto extension, which consists of the following instructions: * vclmulh.[vx,vv] * vclmul.[vx,vv] Translation functions are defined in `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in

[PATCH v6 01/15] target/riscv: Refactor some of the generic vector functionality

From: Kiran Ostrolenk Take some functions/macros out of `vector_helper` and put them in a new module called `vector_internals`. This ensures they can be used by both vector and vector-crypto helpers (latter implemented in proceeding commits). Signed-off-by: Kiran Ostrolenk Reviewed-by: Weiwei

[PATCH v5 00/15] Add RISC-V vector cryptographic instruction set support

Sorry for resending this patch set, because my git-send-mail has some issue. This patchset provides an implementation for Zvbb, Zvbc, Zvkned, Zvknh, Zvksh, Zvkg, and Zvksed of the draft RISC-V vector cryptography extensions as per the v20230620 version of the specification(1)(168e7b4). This is an

[PATCH v6 02/15] target/riscv: Refactor vector-vector translation macro

From: Kiran Ostrolenk Refactor the non SEW-specific stuff out of `GEN_OPIVV_TRANS` into function `opivv_trans` (similar to `opivi_trans`). `opivv_trans` will be used in proceeding vector-crypto commits. Signed-off-by: Kiran Ostrolenk Reviewed-by: Richard Henderson Reviewed-by: Alistair

[PATCH v6 07/15] target/riscv: Refactor some of the generic vector functionality

From: Kiran Ostrolenk Move some macros out of `vector_helper` and into `vector_internals`. This ensures they can be used by both vector and vector-crypto helpers (latter implemented in proceeding commits). Signed-off-by: Kiran Ostrolenk Reviewed-by: Weiwei Li Signed-off-by: Max Chou ---

[PATCH v6 03/15] target/riscv: Remove redundant "cpu_vl == 0" checks

From: Nazar Kazakov Remove the redundant "vl == 0" check which is already included within the vstart >= vl check, when vl == 0. Signed-off-by: Nazar Kazakov Reviewed-by: Weiwei Li Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvv.c.inc | 31 + 1 file

[PATCH v6 06/15] target/riscv: Refactor translation of vector-widening instruction

From: Dickon Hood Zvbb (implemented in later commit) has a widening instruction, which requires an extra check on the enabled extensions. Refactor GEN_OPIVX_WIDEN_TRANS() to take a check function to avoid reimplementing it. Signed-off-by: Dickon Hood Reviewed-by: Richard Henderson

Re: [PATCH v3 09/14] target/ppc: Move patching nip from exception handler to helper_scv

On Mon, 26 Jun 2023, Nicholas Piggin wrote: On Tue Jun 20, 2023 at 8:47 PM AEST, BALATON Zoltan wrote: On Tue, 20 Jun 2023, Nicholas Piggin wrote: On Fri Jun 16, 2023 at 9:03 AM AEST, BALATON Zoltan wrote: From: Nicholas Piggin Unlike sc, for scv a facility unavailable interrupt must be

Re: [PATCH v2 3/4] target/ppc: Make checkstop actually stop the system

On Tue, 27 Jun 2023, Nicholas Piggin wrote: checkstop state does not halt the system, interrupts continue to be serviced, and other CPUs run. Stop the machine with vm_stop(), and print a register dump too. Signed-off-by: Nicholas Piggin --- Since v1: - Fix loop exit so it stops on the attn

[PATCH v5 11/15] target/riscv: Add Zvksh ISA extension support

From: Lawrence Hunter This commit adds support for the Zvksh vector-crypto extension, which consists of the following instructions: * vsm3me.vv * vsm3c.vi Translation functions are defined in `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in `target/riscv/vcrypto_helper.c`.

[PATCH v5 12/15] target/riscv: Add Zvkg ISA extension support

From: Nazar Kazakov This commit adds support for the Zvkg vector-crypto extension, which consists of the following instructions: * vgmul.vv * vghsh.vv Translation functions are defined in `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in `target/riscv/vcrypto_helper.c`.

[PATCH v5 14/15] crypto: Add SM4 constant parameter CK

Adds sm4_ck constant for use in sm4 cryptography across different targets. Signed-off-by: Max Chou Reviewed-by: Frank Chang Signed-off-by: Max Chou --- crypto/sm4.c | 10 ++ include/crypto/sm4.h | 1 + 2 files changed, 11 insertions(+) diff --git a/crypto/sm4.c

[PATCH v5 13/15] crypto: Create sm4_subword

Allows sharing of sm4_subword between different targets. Signed-off-by: Max Chou Reviewed-by: Frank Chang Reviewed-by: Richard Henderson Signed-off-by: Max Chou --- include/crypto/sm4.h | 8 target/arm/tcg/crypto_helper.c | 10 ++ 2 files changed, 10

[PATCH v5 09/15] target/riscv: Add Zvkned ISA extension support

From: Nazar Kazakov This commit adds support for the Zvkned vector-crypto extension, which consists of the following instructions: * vaesef.[vv,vs] * vaesdf.[vv,vs] * vaesdm.[vv,vs] * vaesz.vs * vaesem.[vv,vs] * vaeskf1.vi * vaeskf2.vi Translation functions are defined in

[PATCH v5 15/15] target/riscv: Add Zvksed ISA extension support

This commit adds support for the Zvksed vector-crypto extension, which consists of the following instructions: * vsm4k.vi * vsm4r.[vv,vs] Translation functions are defined in `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in `target/riscv/vcrypto_helper.c`. Signed-off-by:

[PATCH v5 10/15] target/riscv: Add Zvknh ISA extension support

From: Kiran Ostrolenk This commit adds support for the Zvknh vector-crypto extension, which consists of the following instructions: * vsha2ms.vv * vsha2c[hl].vv Translation functions are defined in `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in

[PATCH v5 08/15] target/riscv: Add Zvbb ISA extension support

From: Dickon Hood This commit adds support for the Zvbb vector-crypto extension, which consists of the following instructions: * vrol.[vv,vx] * vror.[vv,vx,vi] * vbrev8.v * vrev8.v * vandn.[vv,vx] * vbrev.v * vclz.v * vctz.v * vcpop.v * vwsll.[vv,vx,vi] Translation functions are defined in

[PATCH v5 07/15] target/riscv: Refactor some of the generic vector functionality

From: Kiran Ostrolenk Move some macros out of `vector_helper` and into `vector_internals`. This ensures they can be used by both vector and vector-crypto helpers (latter implemented in proceeding commits). Signed-off-by: Kiran Ostrolenk Reviewed-by: Weiwei Li Signed-off-by: Max Chou ---

[PATCH v5 06/15] target/riscv: Refactor translation of vector-widening instruction

From: Dickon Hood Zvbb (implemented in later commit) has a widening instruction, which requires an extra check on the enabled extensions. Refactor GEN_OPIVX_WIDEN_TRANS() to take a check function to avoid reimplementing it. Signed-off-by: Dickon Hood Reviewed-by: Richard Henderson

[PATCH v5 05/15] target/riscv: Move vector translation checks

From: Nazar Kazakov Move the checks out of `do_opiv{v,x,i}_gvec{,_shift}` functions and into the corresponding macros. This enables the functions to be reused in proceeding commits without check duplication. Signed-off-by: Nazar Kazakov Reviewed-by: Richard Henderson Reviewed-by: Weiwei Li

[PATCH v5 02/15] target/riscv: Refactor vector-vector translation macro

From: Kiran Ostrolenk Refactor the non SEW-specific stuff out of `GEN_OPIVV_TRANS` into function `opivv_trans` (similar to `opivi_trans`). `opivv_trans` will be used in proceeding vector-crypto commits. Signed-off-by: Kiran Ostrolenk Reviewed-by: Richard Henderson Reviewed-by: Alistair

[PATCH v5 01/15] target/riscv: Refactor some of the generic vector functionality

From: Kiran Ostrolenk Take some functions/macros out of `vector_helper` and put them in a new module called `vector_internals`. This ensures they can be used by both vector and vector-crypto helpers (latter implemented in proceeding commits). Signed-off-by: Kiran Ostrolenk Reviewed-by: Weiwei

[PATCH v5 04/15] target/riscv: Add Zvbc ISA extension support

From: Lawrence Hunter This commit adds support for the Zvbc vector-crypto extension, which consists of the following instructions: * vclmulh.[vx,vv] * vclmul.[vx,vv] Translation functions are defined in `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in

[PATCH v5 00/15] Add RISC-V vector cryptographic instruction set support

This patchset provides an implementation for Zvbb, Zvbc, Zvkned, Zvknh, Zvksh, Zvkg, and Zvksed of the draft RISC-V vector cryptography extensions as per the v20230620 version of the specification(1)(168e7b4). This is an update to the patchset submitted to qemu-devel on Tue, 27 Jun 2023 09:43:24

[PATCH v5 03/15] target/riscv: Remove redundant "cpu_vl == 0" checks

From: Nazar Kazakov Remove the redundant "vl == 0" check which is already included within the vstart >= vl check, when vl == 0. Signed-off-by: Nazar Kazakov Reviewed-by: Weiwei Li Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvv.c.inc | 31 + 1 file

Re: [PATCH v8] Emulate dip switch language layout settings on SUN keyboard

On Tue, 27 Jun 2023 07:33:46 +0100 Mark Cave-Ayland wrote: > I think this is about ready to merge: the only thing I'd like to change is > to swap unsigned char to uint8_t in the signature of > sunkbd_layout_dip_switch(), but I can fix that up myself and queue it to my > qemu-sparc branch. Thanks

[PATCH v5 13/19] target/riscv/kvm.c: update KVM MISA bits

Our design philosophy with KVM properties can be resumed in two main decisions based on KVM interface availability and what the user wants to do: - if the user disables an extension that the host KVM module doesn't know about (i.e. it doesn't implement the kvm_get_one_reg() interface), keep

[PATCH v5 07/19] target/riscv: read marchid/mimpid in kvm_riscv_init_machine_ids()

Allow 'marchid' and 'mimpid' to also be initialized in kvm_riscv_init_machine_ids(). After this change, the handling of mvendorid/marchid/mimpid for the 'host' CPU type will be equal to what we already have for TCG named CPUs, i.e. the user is not able to set these values to a different val than

[PATCH v5 17/19] target/riscv: update multi-letter extension KVM properties

We're now ready to update the multi-letter extensions status for KVM. kvm_riscv_update_cpu_cfg_isa_ext() is called called during vcpu creation time to verify which user options changes host defaults (via the 'user_set' flag) and tries to write them back to KVM. Failure to commit a change to KVM

[PATCH v5 18/19] target/riscv/kvm.c: add kvmconfig_get_cfg_addr() helper

There are 2 places in which we need to get a pointer to a certain property of the cpu->cfg struct based on property offset. Next patch will add a couple more. Create a helper to avoid repeating this code over and over. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones ---

[PATCH v5 15/19] target/riscv/cpu.c: remove priv_ver check from riscv_isa_string_ext()

riscv_isa_string_ext() is being used by riscv_isa_string(), which is then used by boards to retrieve the 'riscv,isa' string to be written in the FDT. All this happens after riscv_cpu_realize(), meaning that we're already past riscv_cpu_validate_set_extensions() and, more important,

[PATCH v5 19/19] target/riscv/kvm.c: read/write (cbom|cboz)_blocksize in KVM

If we don't set a proper cbom_blocksize|cboz_blocksize in the FDT the Linux Kernel will fail to detect the availability of the CBOM/CBOZ extensions, regardless of the contents of the 'riscv,isa' DT prop. The FDT is being written using the cpu->cfg.cbom|z_blocksize attributes, so let's expose them

[PATCH v5 01/19] target/riscv: skip features setup for KVM CPUs

As it is today it's not possible to use '-cpu host' if the RISC-V host has RVH enabled. This is the resulting error: $ sudo ./qemu/build/qemu-system-riscv64 \ -machine virt,accel=kvm -m 2G -smp 1 \ -nographic -snapshot -kernel ./guest_imgs/Image \ -initrd

[PATCH v5 08/19] target/riscv: handle mvendorid/marchid/mimpid for KVM CPUs

After changing user validation for mvendorid/marchid/mimpid to guarantee that the value is validated on user input time, coupled with the work in fetching KVM default values for them by using a scratch CPU, we're certain that the values in cpu->cfg.(mvendorid|marchid|mimpid) are already good to be

[PATCH v5 04/19] target/riscv/cpu.c: restrict 'mimpid' value

Following the same logic used with 'mvendorid' let's also restrict 'mimpid' for named CPUs. Generic CPUs keep setting the value freely. Note that we're getting rid of the default RISCV_CPU_MARCHID value. The reason is that this is not a good default since it's dynamic, changing with with every

[PATCH v5 02/19] hw/riscv/virt.c: skip 'mmu-type' FDT if satp mode not set

The absence of a satp mode in riscv_host_cpu_init() is causing the following error: $ sudo ./qemu/build/qemu-system-riscv64 -machine virt,accel=kvm \ -m 2G -smp 1 -nographic -snapshot \ -kernel ./guest_imgs/Image \ -initrd ./guest_imgs/rootfs_kvm_riscv64.img \ -append

[PATCH v5 06/19] target/riscv: use KVM scratch CPUs to init KVM properties

Certain validations, such as the validations done for the machine IDs (mvendorid/marchid/mimpid), are done before starting the CPU. Non-dynamic (named) CPUs tries to match user input with a preset default. As it is today we can't prefetch a KVM default for these cases because we're only able to

[PATCH v5 09/19] linux-headers: Update to v6.4-rc1

Update to commit ac9a78681b92 ("Linux 6.4-rc1"). Signed-off-by: Daniel Henrique Barboza Acked-by: Alistair Francis --- include/standard-headers/linux/const.h| 2 +- include/standard-headers/linux/virtio_blk.h | 18 +++ .../standard-headers/linux/virtio_config.h| 6 +++

[PATCH v5 10/19] target/riscv/kvm.c: init 'misa_ext_mask' with scratch CPU

At this moment we're retrieving env->misa_ext during kvm_arch_init_cpu(), leaving env->misa_ext_mask behind. We want to set env->misa_ext_mask, and we want to set it as early as possible. The reason is that we're going to use it in the validation process of the KVM MISA properties we're going to

[PATCH v5 16/19] target/riscv/cpu.c: create KVM mock properties

KVM-specific properties are being created inside target/riscv/kvm.c. But at this moment we're gathering all the remaining properties from TCG and adding them as is when running KVM. This creates a situation where non-KVM properties are setting flags to 'true' due to its default settings (e.g.

[PATCH v5 03/19] target/riscv/cpu.c: restrict 'mvendorid' value

We're going to change the handling of mvendorid/marchid/mimpid by the KVM driver. Since these are always present in all CPUs let's put the same validation for everyone. It doesn't make sense to allow 'mvendorid' to be different than it is already set in named (vendor) CPUs. Generic (dynamic) CPUs

[PATCH v5 05/19] target/riscv/cpu.c: restrict 'marchid' value

'marchid' shouldn't be set to a different value as previously set for named CPUs. For all other CPUs it shouldn't be freely set either - the spec requires that 'marchid' can't have the MSB (most significant bit) set and every other bit set to zero, i.e. 0x8000 is an invalid 'marchid' value

[PATCH v5 14/19] target/riscv/kvm.c: add multi-letter extension KVM properties

Let's add KVM user properties for the multi-letter extensions that KVM currently supports: zicbom, zicboz, zihintpause, zbb, ssaia, sstc, svinval and svpbmt. As with MISA extensions, we're using the KVMCPUConfig type to hold information about the state of each extension. However, multi-letter

[PATCH v5 11/19] target/riscv/cpu: add misa_ext_info_arr[]

Next patch will add KVM specific user properties for both MISA and multi-letter extensions. For MISA extensions we want to make use of what is already available in misa_ext_cfgs[] to avoid code repetition. misa_ext_info_arr[] array will hold name and description for each MISA extension that

[PATCH v5 12/19] target/riscv: add KVM specific MISA properties

Using all TCG user properties in KVM is tricky. First because KVM supports only a small subset of what TCG provides, so most of the cpu->cfg flags do nothing for KVM. Second, and more important, we don't have a way of telling if any given value is an user input or not. For TCG this has a small

[PATCH v5 00/19] target/riscv, KVM: fixes and enhancements

Hi, This version has changes in patch 16 proposed by Andrew in v4. No other changes made. Patches missing review: 16 Changes from v4: - patch 16: - reworded comment to "Check if KVM created the property already" - reworded comment to "Set the default to disabled for every extension

[PATCH v3 27/36] gdbstub: Permit reverse step/break to provide stop response

From: Nicholas Piggin The final part of the reverse step and break handling is to bring the machine back to a debug stop state. gdb expects a response. A gdb 'rsi' command hangs forever because the gdbstub filters out the response (also observable with reverse_debugging.py avocado tests). Fix

[PATCH v3 26/36] gdbstub: lightly refactor connection to avoid snprintf

This may be a bit too much to avoid an snprintf and the slightly dodgy assign to a const variable. But hopefully not. Signed-off-by: Alex Bennée --- v2 - fix checkpatch warning --- gdbstub/softmmu.c | 19 +-- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git

Re: [PATCH v3 00/36] maintainer omnibus: testing, fuzz, plugins, documentation (pre-PR)

Alex Bennée writes: > As softfreeze is fast approaching I thought it would be work combining > my various trees into an omnibus series to ease the review and > merging. > Doh, apologies for double posting, this thread is incomplete. See:

Re: [PATCH v2 5/5] migration: Deprecate old compression method

On Thu, Jun 22, 2023 at 09:50:19PM +0200, Juan Quintela wrote: > Signed-off-by: Juan Quintela Acked-by: Peter Xu -- Peter Xu

Re: [PATCH v2 1/5] migration: Use proper indentation for migration.json

On Thu, Jun 22, 2023 at 09:50:15PM +0200, Juan Quintela wrote: > We broke it with dirtyrate limit patches. > > Signed-off-by: Juan Quintela Acked-by: Peter Xu -- Peter Xu

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