We are not mixing C++ with C code anymore, the only remaining
C++ code in qga/vss-win32/ is used for a plain C++ executable.
Thus we can remove the hacks for linking C code with the C++ linker
now to simplify meson.build a little bit, and also to avoid that
some C++ code sneaks in by accident again
On 7/5/23 23:17, ltaylorsimp...@gmail.com wrote:
-Original Message-
From: Matheus Tavares Bernardino
Sent: Wednesday, July 5, 2023 12:35 PM
To: qemu-devel@nongnu.org
Cc: quic_mathb...@quicinc.com; bc...@quicinc.com;
ltaylorsimp...@gmail.com; quic_mlie...@quicinc.com;
richard.hender...
On 7/6/23 05:14, Sittisak Sinprem wrote:
Hi Mike,
the FRUID data, it is used to define the BMC Mac address,
to able the CIT, test_eeprom, test_bmc_mac on Qemu.
That's enough for the commit log and the comment. Adding the EEPROM
contents in QEMU enables more tests to be performed on the FW side
On 7/6/23 04:45, Joel Stanley wrote:
Add the function name so there's an indication as to where the message
is coming from. Change all prints to use the offset instead of the
address.
Signed-off-by: Joel Stanley
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
Happy to use the address inst
On 7/6/23 07:39, Nicholas Piggin wrote:
Sorry about the paper bag bug in the first version of the patch -
I broke powernv8 and 9.
This adds a xsom_size core class field to change the P10 size without
changing the others.
Also added a P10 xscom test, and passes make check.
Now, you know there
On 7/6/23 04:33, Joel Stanley wrote:
On Wed, 5 Jul 2023 at 10:02, Cédric Le Goater wrote:
On 7/5/23 04:05, Joel Stanley wrote:
On Wed, 5 Jul 2023 at 01:27, Nicholas Piggin wrote:
The P10 core xscom memory regions overlap because the size is wrong.
The P10 core+L2 xscom region size is alloc
On 7/4/23 16:29, Stefan Hajnoczi wrote:
The following changes since commit d145c0da22cde391d8c6672d33146ce306e8bf75:
Merge tag 'pull-tcg-20230701' ofhttps://gitlab.com/rth7680/qemu into
staging (2023-07-01 08:55:37 +0200)
are available in the Git repository at:
https://gitlab.com/stefa
This series has been tested successfully by QE. Start a VM with a 8G
virtio-mem device and start memtester on it. Enable x-ignore-shared
capability and then do migration. Migration was successful and
virtio-mem can be resized as usual.
Tested-by: Mario Casquero
BR,
Mario
On Tue, Jun 20, 2023
On Mon, Jul 3, 2023 at 5:20 PM Weiwei Li wrote:
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
Acked-by: Alistair Francis
Alistair
> ---
> disas/riscv.c | 44
> 1 file changed, 44 insertions(+)
>
> diff --git a/disas/riscv.c b/disas/
This patch series mainly updates SapphireRapids CPU model and adds new
CPU model GraniteRapids.
Bit 13 (ARCH_CAP_SBDR_SSDP_NO), bit 14 (ARCH_CAP_FBSDP_NO) and bit 15
(ARCH_CAP_PSDP_NO) of MSR_IA32_ARCH_CAPABILITIES are enumerated starting
from SapphireRapids, which are missed in current SapphireRa
MCDT_NO bit indicates HW contains the security fix and doesn't need to
be mitigated to avoid data-dependent behaviour for certain instructions.
It needs no hypervisor support. Treat it as supported regardless of what
KVM reports.
Signed-off-by: Tao Su
Reviewed-by: Xiaoyao Li
---
target/i386/kvm
Currently, bit 13, 14, 15 and 24 of MSR_IA32_ARCH_CAPABILITIES are
disclosed for fixing security issues, so add those bit definitions.
Signed-off-by: Tao Su
Reviewed-by: Igor Mammedov
---
target/i386/cpu.h | 4
1 file changed, 4 insertions(+)
diff --git a/target/i386/cpu.h b/target/i386/c
The GraniteRapids CPU model mainly adds the following new features
based on SapphireRapids:
- PREFETCHITI CPUID.(EAX=7,ECX=1):EDX[bit 14]
- AMX-FP16 CPUID.(EAX=7,ECX=1):EAX[bit 21]
And adds the following security fix for corresponding vulnerabilities:
- MCDT_NO CPUID.(EAX=7,ECX=2):EDX[bit 5]
- SBD
CPUID.(EAX=7,ECX=2):EDX[bit 5] enumerates MCDT_NO. Processors enumerate
this bit as 1 do not exhibit MXCSR Configuration Dependent Timing (MCDT)
behavior and do not need to be mitigated to avoid data-dependent behavior
for certain instructions.
Since MCDT_NO is in a new sub-leaf, add a new CPUID f
Considering the case of FEAT_7_1_EAX being 0 and FEAT_7_1_EDX being
non-zero. Such as starting a VM on GraniteRapids using '-cpu host',
we can see two leafs CPUID_7_0 and CPUID_7_1 in VM, because both
CPUID_7_1_EAX and CPUID_7_1_EDX have non-zero value, but if minus all
FEAT_7_1_EAX features using
From: Lei Wang
SapphireRapids has bit 13, 14 and 15 of MSR_IA32_ARCH_CAPABILITIES
enabled, which are related to some security fixes.
Add version 2 of SapphireRapids CPU model with those bits enabled also.
Signed-off-by: Lei Wang
Signed-off-by: Tao Su
---
target/i386/cpu.c | 13 +++--
On Thu, Jul 6, 2023 at 2:13 AM Si-Wei Liu wrote:
>
>
>
> On 7/5/2023 11:03 AM, Eugenio Perez Martin wrote:
> > On Tue, Jun 27, 2023 at 8:36 AM Si-Wei Liu wrote:
> >>
> >>
> >> On 6/9/2023 7:32 AM, Eugenio Perez Martin wrote:
> >>> On Fri, Jun 9, 2023 at 12:39 AM Si-Wei Liu wrote:
> On 6/7/2
Sorry about the paper bag bug in the first version of the patch -
I broke powernv8 and 9.
This adds a xsom_size core class field to change the P10 size without
changing the others.
Also added a P10 xscom test, and passes make check.
Thanks,
Nick
Nicholas Piggin (2):
ppc/pnv: Set P10 core xsco
Add basic chip and core xscom tests for powernv10 machine, equivalent
to tests for powernv8 and 9.
Signed-off-by: Nicholas Piggin
---
tests/qtest/pnv-xscom-test.c | 44
1 file changed, 35 insertions(+), 9 deletions(-)
diff --git a/tests/qtest/pnv-xscom-test.
The P10 core xscom memory regions overlap because the size is wrong.
The P10 core+L2 xscom region size is allocated as 0x1000 (with some
unused ranges). "EC" is used as a closer match, as "EX" includes L3
which has a disjoint xscom range that would require a different
region if it were implemented.
When trying to migrate a machine type pc-q35-6.0 or lower, with this
cmdline options,
-device
driver=pcie-root-port,port=18,chassis=19,id=pcie-root-port18,bus=pcie.0,addr=0x12
\
-device
driver=nec-usb-xhci,p2=4,p3=4,id=nex-usb-xhci0,bus=pcie-root-port18,addr=0x12.0x1
the following bug happens
On Wed, Jul 5, 2023 at 3:40 AM Leonardo Bras Soares Passos
wrote:
>
> On Tue, Jul 4, 2023 at 3:43 AM Michael S. Tsirkin wrote:
> >
> > On Tue, Jul 04, 2023 at 03:20:36AM -0300, Leonardo Brás wrote:
> > > Hello Peter and Michael, I have a few updates on this:
> > >
> > > On Mon, 2023-07-03 at 02:2
If the devicetree is created before machine initialization is complete,
it misses dynamic devices. Specifically, the tpm device is not added
to the devicetree file and is therefore not instantiated in Linux.
Load/create devicetree in virt_machine_done() to solve the problem.
Cc: Daniel Henrique Ba
Hi Mike,
the FRUID data, it is used to define the BMC Mac address,
to able the CIT, test_eeprom, test_bmc_mac on Qemu.
On Thu, Jul 6, 2023 at 12:38 AM Mike Choi wrote:
> Hi Sittisak,
>
>
>
> Minipack3 is not open-sourced yet, and we are unlikely to be able to
> upstream detailed data.
>
>
>
>
Add the function name so there's an indication as to where the message
is coming from. Change all prints to use the offset instead of the
address.
Signed-off-by: Joel Stanley
---
Happy to use the address instead of the offset (or print both), but I
like the idea of being consistent.
---
hw/ppc/p
On Wed, 5 Jul 2023 at 10:02, Cédric Le Goater wrote:
>
> On 7/5/23 04:05, Joel Stanley wrote:
> > On Wed, 5 Jul 2023 at 01:27, Nicholas Piggin wrote:
> >>
> >> The P10 core xscom memory regions overlap because the size is wrong.
> >> The P10 core+L2 xscom region size is allocated as 0x1000 (with
On 2023/07/05 20:59, Ani Sinha wrote:
PCIe downstream ports only have a single device 0, so PCI Express devices can
only be plugged into slot 0 on a PCIe port. Add a warning to let users know
when the invalid configuration is used. We may enforce this more strongly later
once we get more clarity
On Wed, 5 Jul 2023, Daniel Henrique Barboza wrote:
Zoltan,
Patches 1-9 are queued. Don't need to re-send those.
Thanks, the last two patches are also reviewed and they don't depend on
the ones before so you could queue those too.
The only outstanding patches are those 3 that rename the type
Zoltan,
Patches 1-9 are queued. Don't need to re-send those.
Thanks,
Daniel
On 7/5/23 17:12, BALATON Zoltan wrote:
These are some small misc clean ups to PPC440 related device models
which is all I have ready for now.
v2:
- Added R-b tags from Philippe
- Addressed review comments
- Added ne
On 7/5/23 17:12, BALATON Zoltan wrote:
Some places already use get_system_memory() directly so replace the
remaining uses and drop the local variable.
Signed-off-by: BALATON Zoltan
---
Reviewed-by: Daniel Henrique Barboza
hw/ppc/sam460ex.c | 8
1 file changed, 4 insertions(
On 7/5/2023 11:03 AM, Eugenio Perez Martin wrote:
On Tue, Jun 27, 2023 at 8:36 AM Si-Wei Liu wrote:
On 6/9/2023 7:32 AM, Eugenio Perez Martin wrote:
On Fri, Jun 9, 2023 at 12:39 AM Si-Wei Liu wrote:
On 6/7/23 01:08, Eugenio Perez Martin wrote:
On Wed, Jun 7, 2023 at 12:43 AM Si-Wei Liu
On 7/4/2023 9:07 AM, Marc-André Lureau wrote:
Hi
On Mon, Jun 26, 2023 at 9:49 PM Kim, Dongwon
wrote:
Hi Marc-André Lureau,
On 6/26/2023 4:56 AM, Marc-André Lureau wrote:
> Hi
>
> On Wed, Jun 21, 2023 at 11:53 PM Dongwon Kim
> wrote:
>
> x and y offse
'backing_width' and 'backing_height' are commonly used to indicate the size
of the whole backing region so it makes sense to use those terms for
VGAUDMABuf as well in place of 'scanout_width' and 'scanout_height'.
Cc: Gerd Hoffmann
Cc: Marc-André Lureau
Cc: Vivek Kasireddy
Signed-off-by: Dongwo
On Wed, Jul 05, 2023 at 07:05:13PM -0300, Fabiano Rosas wrote:
> Peter Xu writes:
>
> > Provide an explicit reason for qemu_file_shutdown()s, which can be
> > displayed in query-migrate when used.
> >
>
> Can we consider this to cover the TODO:
>
> * TODO: convert to propagate Error objects in
On Wed, Jul 05, 2023 at 06:54:37PM -0300, Fabiano Rosas wrote:
> Peter Xu writes:
>
> > There're a lot of cases where we only have an errno set in last_error but
> > without a detailed error description. When this happens, try to generate
> > an error contains the errno as a descriptive error.
>
Am 5. Juli 2023 16:50:28 UTC schrieb Joel Upham :
>I believe it might have been master unstable branch. Last commit before my
>patches was:
>
>commit 19a720b74fde7e859d19f12c66a72e545947a657
>Merge: c6a5fc2ac7 367189efae
>Author: Richard Henderson
>Date: Thu Jun 1 08:30:29 2023 -0700
Indeed!
eal gentlemann and amend the
commit msg for us :D
That said, things like FreeBSD and U-Boot appear to require mmu-type
https://lore.kernel.org/all/20230705-fondue-bagginess-66c25f1a4135@spud/
so I am wondering if we should in fact make the mmu-type a required
property in the RISC-V specific bind
> -Original Message-
> From: Matheus Tavares Bernardino
> Sent: Wednesday, July 5, 2023 12:35 PM
> To: qemu-devel@nongnu.org
> Cc: quic_mathb...@quicinc.com; bc...@quicinc.com;
> ltaylorsimp...@gmail.com; quic_mlie...@quicinc.com;
> richard.hender...@linaro.org
> Subject: [PATCH v2] Hex
g.
>
> You mean this link?
>
> https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/riscv/cpus.yaml
Yeah, that's the correct file. Should probably have linked it, sorry
about that. And in case it was not clear, not suggesting that this would
require a re
Peter Xu writes:
> Provide an explicit reason for qemu_file_shutdown()s, which can be
> displayed in query-migrate when used.
>
Can we consider this to cover the TODO:
* TODO: convert to propagate Error objects instead of squashing
* to a fixed errno value
or would that need something fancie
cific cpus binding.
You mean this link?
https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/riscv/cpus.yaml
That said, things like FreeBSD and U-Boot appear to require mmu-type
https://lore.kernel.org/all/20230705-fondue-bagginess-66c25f1a4135@spud/
so I am wo
Peter Xu writes:
> There're a lot of cases where we only have an errno set in last_error but
> without a detailed error description. When this happens, try to generate
> an error contains the errno as a descriptive error.
>
> This will be helpful in cases where one relies on the Error*. E.g.,
>
Am 5. Juli 2023 10:01:21 UTC schrieb Olaf Hering :
>Tue, 4 Jul 2023 08:38:33 +0200 Paolo Bonzini :
>
>> I agree that calling pci_device_reset() would be a better match for
>> pci_xen_ide_unplug().
>
>This change works as well:
Nice!
>
>--- a/hw/i386/xen/xen_platform.c
>+++ b/hw/i386/xen/xen_p
p, as the
generic binding sets out no requirements. I think you would want to link
to the RISC-V specific cpus binding.
That said, things like FreeBSD and U-Boot appear to require mmu-type
https://lore.kernel.org/all/20230705-fondue-bagginess-66c25f1a4135@spud/
so I am wondering if we should in fac
's riscv-to-apply.next.
Patches missing review: 14
Changes from v7:
- Patch 14:
- use 'errno' to check the error code from ioctl()
- test for ENOENT instead of EINVAL
- v7 link:
https://lore.kernel.org/qemu-devel/20230630100811.287315-1-dbarb...@ventanamicro.com/
[1] https://
Let's add KVM user properties for the multi-letter extensions that KVM
currently supports: zicbom, zicboz, zihintpause, zbb, ssaia, sstc,
svinval and svpbmt.
As with MISA extensions, we're using the KVMCPUConfig type to hold
information about the state of each extension. However, multi-letter
exte
If we don't set a proper cbom_blocksize|cboz_blocksize in the FDT the
Linux Kernel will fail to detect the availability of the CBOM/CBOZ
extensions, regardless of the contents of the 'riscv,isa' DT prop.
The FDT is being written using the cpu->cfg.cbom|z_blocksize attributes,
so let's expose them
We're going to change the handling of mvendorid/marchid/mimpid by the
KVM driver. Since these are always present in all CPUs let's put the
same validation for everyone.
It doesn't make sense to allow 'mvendorid' to be different than it
is already set in named (vendor) CPUs. Generic (dynamic) CPUs
Our design philosophy with KVM properties can be resumed in two main
decisions based on KVM interface availability and what the user wants to
do:
- if the user disables an extension that the host KVM module doesn't
know about (i.e. it doesn't implement the kvm_get_one_reg() interface),
keep bootin
The absence of a satp mode in riscv_host_cpu_init() is causing the
following error:
$ ./qemu/build/qemu-system-riscv64 -machine virt,accel=kvm \
-m 2G -smp 1 -nographic -snapshot \
-kernel ./guest_imgs/Image \
-initrd ./guest_imgs/rootfs_kvm_riscv64.img \
-append "earlycon=sbi ro
At this moment we're retrieving env->misa_ext during
kvm_arch_init_cpu(), leaving env->misa_ext_mask behind.
We want to set env->misa_ext_mask, and we want to set it as early as
possible. The reason is that we're going to use it in the validation
process of the KVM MISA properties we're going to a
Update to commit ac9a78681b92 ("Linux 6.4-rc1").
Signed-off-by: Daniel Henrique Barboza
Acked-by: Alistair Francis
---
include/standard-headers/linux/const.h| 2 +-
include/standard-headers/linux/virtio_blk.h | 18 +++
.../standard-headers/linux/virtio_config.h| 6 +++
inclu
After changing user validation for mvendorid/marchid/mimpid to guarantee
that the value is validated on user input time, coupled with the work in
fetching KVM default values for them by using a scratch CPU, we're
certain that the values in cpu->cfg.(mvendorid|marchid|mimpid) are
already good to be
On 7/5/2023 5:33 PM, Steven Sistare wrote:
> On 6/7/2023 11:58 AM, Peter Xu wrote:
>> On Wed, Jun 07, 2023 at 07:35:32AM -0700, Steve Sistare wrote:
>>> Modify migrate_add_blocker and migrate_del_blocker to take an Error **
>>> reason. This allows migration to own the Error object, so that if
>>>
riscv_cpu_add_user_properties() ended up with an excess of "#ifndef
CONFIG_USER_ONLY" blocks after changes that added KVM properties
handling.
KVM specific properties are required to be created earlier than their
TCG counterparts, but the remaining props can be created at any order.
Move riscv_add
There are 2 places in which we need to get a pointer to a certain
property of the cpu->cfg struct based on property offset. Next patch
will add a couple more.
Create a helper to avoid repeating this code over and over.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
---
target
riscv_isa_string_ext() is being used by riscv_isa_string(), which is
then used by boards to retrieve the 'riscv,isa' string to be written in
the FDT. All this happens after riscv_cpu_realize(), meaning that we're
already past riscv_cpu_validate_set_extensions() and, more important,
riscv_cpu_disabl
Certain validations, such as the validations done for the machine IDs
(mvendorid/marchid/mimpid), are done before starting the CPU.
Non-dynamic (named) CPUs tries to match user input with a preset
default. As it is today we can't prefetch a KVM default for these cases
because we're only able to rea
Allow 'marchid' and 'mimpid' to also be initialized in
kvm_riscv_init_machine_ids().
After this change, the handling of mvendorid/marchid/mimpid for the
'host' CPU type will be equal to what we already have for TCG named
CPUs, i.e. the user is not able to set these values to a different val
than t
'marchid' shouldn't be set to a different value as previously set for
named CPUs.
For all other CPUs it shouldn't be freely set either - the spec requires
that 'marchid' can't have the MSB (most significant bit) set and every
other bit set to zero, i.e. 0x8000 is an invalid 'marchid' value for
We're now ready to update the multi-letter extensions status for KVM.
kvm_riscv_update_cpu_cfg_isa_ext() is called called during vcpu creation
time to verify which user options changes host defaults (via the 'user_set'
flag) and tries to write them back to KVM.
Failure to commit a change to KVM i
Next patch will add KVM specific user properties for both MISA and
multi-letter extensions. For MISA extensions we want to make use of what
is already available in misa_ext_cfgs[] to avoid code repetition.
misa_ext_info_arr[] array will hold name and description for each MISA
extension that misa_e
KVM-specific properties are being created inside target/riscv/kvm.c. But
at this moment we're gathering all the remaining properties from TCG and
adding them as is when running KVM. This creates a situation where
non-KVM properties are setting flags to 'true' due to its default
settings (e.g. Zawr
Using all TCG user properties in KVM is tricky. First because KVM
supports only a small subset of what TCG provides, so most of the
cpu->cfg flags do nothing for KVM.
Second, and more important, we don't have a way of telling if any given
value is an user input or not. For TCG this has a small imp
As it is today it's not possible to use '-cpu host' if the RISC-V host
has RVH enabled. This is the resulting error:
$ ./qemu/build/qemu-system-riscv64 \
-machine virt,accel=kvm -m 2G -smp 1 \
-nographic -snapshot -kernel ./guest_imgs/Image \
-initrd ./guest_imgs/rootfs_kvm_riscv64.im
Following the same logic used with 'mvendorid' let's also restrict
'mimpid' for named CPUs. Generic CPUs keep setting the value freely.
Note that we're getting rid of the default RISCV_CPU_MARCHID value. The
reason is that this is not a good default since it's dynamic, changing
with with every QEM
On 6/7/2023 11:58 AM, Peter Xu wrote:
> On Wed, Jun 07, 2023 at 07:35:32AM -0700, Steve Sistare wrote:
>> Modify migrate_add_blocker and migrate_del_blocker to take an Error **
>> reason. This allows migration to own the Error object, so that if
>> an error occurs, migration code can free the Erro
AF_XDP is a network socket family that allows communication directly
with the network device driver in the kernel, bypassing most or all
of the kernel networking stack. In the essence, the technology is
pretty similar to netmap. But, unlike netmap, AF_XDP is Linux-native
and works with any networ
Peter Xu writes:
> Introduce a helper to detect whether MigrationState.error is set for
> whatever reason. It is intended to not taking the error_mutex here because
> neither do we reference the pointer, nor do we modify the pointer. State
> why it's safe to do so.
>
> This is preparation work
Peter Xu writes:
> migrate_set_error() used one error_copy() so it always copy an error.
> However that's not the major use case - the major use case is one would
> like to pass the error to migrate_set_error() without further touching the
> error.
>
> It can be proved if we see most of the calle
Richard Henderson writes:
> On 7/4/23 17:44, Peter Maydell wrote:
>>> IIUC tcg_enabled(), this guard shouldn't be necessary; if CONFIG_TCG
>>> is not defined, tcg_enabled() evaluates to 0, and the compiler should
>>> elide the whole block.
>>
>> IME it's a bit optimistic to assume that the compi
On 5/7/23 16:12, Konstantin Kostiuk wrote:
Signed-off-by: Konstantin Kostiuk
---
qga/vss-win32/install.cpp | 13 +++--
qga/vss-win32/requester.cpp | 9 +
2 files changed, 12 insertions(+), 10 deletions(-)
diff --git a/qga/vss-win32/install.cpp b/qga/vss-win32/install.cpp
Hi Konstantin,
On 5/7/23 16:12, Konstantin Kostiuk wrote:
Signed-off-by: Konstantin Kostiuk
---
qga/vss-win32/vss-debug.h | 31 +++
1 file changed, 31 insertions(+)
create mode 100644 qga/vss-win32/vss-debug.h
+#define PRINT_DEBUG(fmt, ...) {
On 5/7/23 22:12, BALATON Zoltan wrote:
Add separate memory regions for the mem and io spaces of the PCIe bus
to avoid different buses using the same system io region.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440_uc.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
Reviewe
On 5/7/23 22:12, BALATON Zoltan wrote:
The iomem memory region is better used for the PCI IO space but
currently used for registers. Stop using it for that to allow this to
be cleaned up in the next patch.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440_pcix.c | 7 ---
1 file changed, 4
On 5/7/23 17:23, Cédric Le Goater wrote:
It is useful to extend the number of available PCI devices to KVM guests
for passthrough scenarios and also to expose these models to a different
(big endian) architecture. Include models for Intel Ethernet adapters
and one USB controller, which all suppor
On Wed, 5 Jul 2023, BALATON Zoltan wrote:
These are some small misc clean ups to PPC440 related device models
which is all I have ready for now.
Sorry, typo in email addresses in cc. Should I send it again or you can
pick up from the list?
Regards,
BALATON Zoltan
v2:
- Added R-b tags from
QOM prefers to call the parent field parent_obj, change
PPC460EXPCIEState ro match that convention.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/ppc/ppc440_uc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.
After previous changes we can now remove the legacy init function and
move the device creation to board code.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/ppc/ppc440.h | 1 -
hw/ppc/ppc440_uc.c | 21 -
hw/ppc/sam460ex.c | 17 ++
Add a QOM type name define for ppc4xx-host-bridge in the common header
and replace direct use of the string name with the constant.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440_pcix.c| 3 ++-
hw/ppc/ppc4xx_pci.c | 4 ++--
include/hw/ppc/ppc4xx.h | 1 +
3 files changed, 5 insertions(+)
It is shorter and more readable to wrap the complex call to
ppc_dcr_register() in a macro than to repeat it several times.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/ppc/ppc440_uc.c | 76 +-
1 file changed, 28 insertions(
The PCIe controller model uses PPC DCRs but cannot be modeled with
TYPE_PPC4xx_DCR_DEVICE as it derives from TYPE_PCIE_HOST_BRIDGE. Add a
cpu link property to it similar to other DCR devices to allow
registering DCRs from the device model.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathi
Some places already use get_system_memory() directly so replace the
remaining uses and drop the local variable.
Signed-off-by: BALATON Zoltan
---
hw/ppc/sam460ex.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c
index aaa8d2f4a5.
Rename the TYPE_PPC4xx_PCI_HOST_BRIDGE define and its string value to
match each other and other similar types and to avoid confusion with
"ppc4xx-host-bridge" type defined in same file.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440_bamboo.c | 3 +--
hw/ppc/ppc4xx_pci.c | 6 +++---
includ
The iomem memory region is better used for the PCI IO space but
currently used for registers. Stop using it for that to allow this to
be cleaned up in the next patch.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440_pcix.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a
Rename local variable storing state struct in dcr_read_pcie() for
brevity and consistency with other functions.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/ppc/ppc440_uc.c | 50 +++---
1 file changed, 25 insertions(+), 25 dele
Add separate memory regions for the mem and io spaces of the PCIe bus
to avoid different buses using the same system io region.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440_uc.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.
Instead of guessing controller number from dcrn_base add a property so
the device does not need knowledge about where it is used.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/ppc/ppc440_uc.c | 25 +++--
1 file changed, 11 insertions(+), 14 deletio
Reduce the iomem region to 64K and use it for the PCI io space and map
it directly from the board without an intermediate alias that is not
really needed.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/ppc/ppc440_pcix.c | 9 ++---
hw/ppc/sam460ex.c| 6 +-
2
Rename TYPE_PPC440_PCIX_HOST_BRIDGE to better match its string value,
move it to common header and use it also in sam460ex to replace hard
coded type name.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440_pcix.c| 9 -
hw/ppc/sam460ex.c | 2 +-
include/hw/ppc/ppc4xx.h | 1 +
3 fi
These are some small misc clean ups to PPC440 related device models
which is all I have ready for now.
v2:
- Added R-b tags from Philippe
- Addressed review comments
- Added new patch to rename parent field of PPC460EXPCIEState to parent_obj
Patches needing review: 6 7 10-13
BALATON Zoltan (14):
Change parameter of ppc460ex_pcie_init() from env to cpu to allow
further refactoring.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/ppc/ppc440.h| 2 +-
hw/ppc/ppc440_uc.c | 7 ---
hw/ppc/sam460ex.c | 2 +-
3 files changed, 6 insertions(+), 5 deletions(-)
di
Hi Sittisak,
Minipack3 is not open-sourced yet, and we are unlikely to be able to upstream
detailed data.
1. What is these FRUID datas for, is it for testing?
2. What other option do we have, since we are not able to upstream FRUID
data. (It is still OK to upstream system configuration,
On 03/07/2023 09:30, Philippe Mathieu-Daudé wrote:
On 2/7/23 17:48, Mark Cave-Ayland wrote:
The MacOS toolbox ROM calculates the number of branches that can be executed
per millisecond as part of its timer calibration. Since modern hosts are
considerably quicker than original hardware, the nega
On 7/5/23 10:41, Andrew Jones wrote:
On Fri, Jun 30, 2023 at 07:08:05AM -0300, Daniel Henrique Barboza wrote:
Let's add KVM user properties for the multi-letter extensions that KVM
currently supports: zicbom, zicboz, zihintpause, zbb, ssaia, sstc,
svinval and svpbmt.
As with MISA extensions,
On 03/07/2023 09:26, Philippe Mathieu-Daudé wrote:
On 2/7/23 17:48, Mark Cave-Ayland wrote:
Signed-off-by: Mark Cave-Ayland
---
hw/block/swim.c | 14 ++
hw/block/trace-events | 7 +++
2 files changed, 21 insertions(+)
@@ -267,6 +275,7 @@ static void iwmctrl_write(
On 7/5/23 11:23 AM, Cédric Le Goater wrote:
> It is useful to extend the number of available PCI devices to KVM guests
> for passthrough scenarios and also to expose these models to a different
> (big endian) architecture. Include models for Intel Ethernet adapters
> and one USB controller, which a
As docs/devel/loads-stores.rst states:
``GETPC()`` should be used with great care: calling
it in other functions that are *not* the top level
``HELPER(foo)`` will cause unexpected behavior. Instead, the
value of ``GETPC()`` should be read from the helper and passed
if needed to the funct
HI Leo,
On 7/2/23 11:14 PM, Leo Yan wrote:
Hi Vikram,
On Thu, Jun 29, 2023 at 10:43:10AM -0700, Oleksandr Tyshchenko wrote:
[...]
void arch_handle_ioreq(XenIOState *state, ioreq_t *req)
{
hw_error("Invalid ioreq type 0x%x\n", req->type);
@@ -135,6 +170,14 @@ static void xen_arm_ini
The TLS handshake make take some time to complete, during which time an
I/O watch might be registered with the main loop. If the owner of the
I/O channel invokes qio_channel_close() while the handshake is waiting
to continue the I/O watch must be removed. Failing to remove it will
later trigger the
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