On Fri, Jul 14, 2023 at 3:43 AM Conor Dooley wrote:
>
> +CC OpenSBI Mailing list
>
> I've not yet had the chance to bisect this, so adding the OpenSBI folks
> to CC in case they might have an idea for what to try.
>
> And a question for you below Daniel.
>
> On Wed, Jul 12, 2023 at 11:14:21PM
Translation logic may partially decode an instruction, then abort and
remove the instruction from the TB. This can happen for example when an
instruction spans two pages. In this case, plugins may get an incorrect
result when calling qemu_plugin_tb_n_insns to query for the number of
instructions
On Tue, Jul 11, 2023 at 10:20 PM Philippe Mathieu-Daudé
wrote:
>
> riscv_cpu_do_interrupt() is not reachable on user emulation.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.h| 5 +++--
> target/riscv/cpu_helper.c | 7
On Thu, Jul 13, 2023 at 6:59 AM Daniel Henrique Barboza
wrote:
>
> After the introduction of riscv_cpu_options[] all properties in
> riscv_cpu_extensions[] are booleans. This check is now obsolete.
>
> Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Alistair
> ---
>
On Thu, Jul 13, 2023 at 7:00 AM Daniel Henrique Barboza
wrote:
>
> Create a new riscv_cpu_experimental_exts[] to store the non-ratified
> extensions properties. Once they are ratified we'll move them back to
> riscv_cpu_extensions[].
>
> Change riscv_cpu_add_user_properties to keep adding them to
On Thu, Jul 13, 2023 at 6:58 AM Daniel Henrique Barboza
wrote:
>
> Our goal is to make riscv_cpu_extensions[] hold only ratified,
> non-vendor extensions.
>
> Create a new riscv_cpu_vendor_exts[] array for them, changing
> riscv_cpu_add_user_properties() accordingly.
>
> Signed-off-by: Daniel
On Thu, Jul 13, 2023 at 6:59 AM Daniel Henrique Barboza
wrote:
>
> We'll add a new CPU type that will enable a considerable amount of
> extensions. To make it easier for us we'll do a few cleanups in our
> existing riscv_cpu_extensions[] array.
>
> Start by splitting all CPU non-boolean options
On Fri, Jul 14, 2023 at 11:14 AM Daniel Henrique Barboza
wrote:
>
>
>
> On 7/13/23 19:47, Conor Dooley wrote:
> > On Thu, Jul 13, 2023 at 07:35:01PM -0300, Daniel Henrique Barboza wrote:
> >> On 7/13/23 19:12, Conor Dooley wrote:
> >
> >>> And a question for you below Daniel.
> >>>
> >>> On Wed,
On Thu, Jul 13, 2023 at 7:00 AM Daniel Henrique Barboza
wrote:
>
> The 'max' CPU type is used by tooling to determine what's the most
> capable CPU a current QEMU version implements. Other archs such as ARM
> implements this type. Let's add it to RISC-V.
>
> What we consider "most capable CPU" in
On Tue, Jul 11, 2023 at 5:52 PM Christoph Muellner
wrote:
>
> From: Christoph Müllner
>
> The GNU assembler produces the following output for instructions
> with upper immediates:
> 2597auipc a1,0x2
> 24b7lui s1,0x2
> 6409
On Tue, Jul 11, 2023 at 5:52 PM Christoph Muellner
wrote:
>
> From: Christoph Müllner
>
> The GNU assembler produces the following output for instructions
> with upper immediates:
> 2597auipc a1,0x2
> 24b7lui s1,0x2
> 6409
On Thu, Jul 13, 2023 at 4:47 PM Michael Tokarev wrote:
>
> 12.07.2023 17:37, Daniel Henrique Barboza wrote:
> > This is how the content of the "RISC-V CPU firmware" section is
> > displayed after the html is generated:
> >
> > "When using the sifive_u or virt machine there are three different
> >
On Thu, Jul 13, 2023 at 12:38 AM Daniel Henrique Barboza
wrote:
>
> This is how the content of the "RISC-V CPU firmware" section is
> displayed after the html is generated:
>
> "When using the sifive_u or virt machine there are three different
> firmware boot options: 1. -bios default - This is
Added command "request-ebpf". This command returns
eBPF program encoded base64. The program taken from the
skeleton and essentially is an ELF object that can be
loaded in the future with libbpf.
The reason to use the command to provide the eBPF object
instead of a separate artifact was to avoid
Now, the binary objects may be retrieved by id.
It would require for future qmp commands that may require specific
eBPF blob.
Signed-off-by: Andrew Melnychenko
---
ebpf/ebpf.c | 70
ebpf/ebpf.h | 31 +
It allows using file descriptors of eBPF provided
outside of QEMU.
QEMU may be run without capabilities for eBPF and run
RSS program provided by management tool(g.e. libvirt).
Signed-off-by: Andrew Melnychenko
---
ebpf/ebpf_rss-stub.c | 6 ++
ebpf/ebpf_rss.c | 27
Changed eBPF map updates through mmaped array.
Mmaped arrays provide direct access to map data.
It should omit using bpf_map_update_elem() call,
which may require capabilities that are not present.
Signed-off-by: Andrew Melnychenko
---
ebpf/ebpf_rss.c | 117
Updated section name, so libbpf should init/gues proper
program type without specifications during open/load.
Signed-off-by: Andrew Melnychenko
---
ebpf/rss.bpf.skeleton.h | 1469 ---
tools/ebpf/rss.bpf.c|2 +-
2 files changed, 741 insertions(+), 730
This series of patches provides the ability to retrieve eBPF program
through qmp, so management application may load bpf blob with proper
capabilities.
Now, virtio-net devices can accept eBPF programs and maps through properties
as external file descriptors. Access to the eBPF map is direct
eBPF RSS program and maps may now be passed during initialization.
Initially was implemented for libvirt to launch qemu without permissions,
and initialized eBPF program through the helper.
Signed-off-by: Andrew Melnychenko
---
hw/net/virtio-net.c| 55
On 7/13/23 19:47, Conor Dooley wrote:
On Thu, Jul 13, 2023 at 07:35:01PM -0300, Daniel Henrique Barboza wrote:
On 7/13/23 19:12, Conor Dooley wrote:
And a question for you below Daniel.
On Wed, Jul 12, 2023 at 11:14:21PM +0100, Conor Dooley wrote:
qemu-system-riscv64: warning:
Hi Richard,
On 7/14/23 05:27, Richard Henderson wrote:
On 7/13/23 13:34, Gavin Shan wrote:
On 7/13/23 21:52, Marcin Juszkiewicz wrote:
W dniu 13.07.2023 o 13:44, Peter Maydell pisze:
I see this isn't a change in this patch, but given that
what the user specifies is not "cortex-a8-arm-cpu"
Hi Philippe,
On 7/14/23 02:29, Philippe Mathieu-Daudé wrote:
On 13/7/23 14:34, Gavin Shan wrote:
On 7/13/23 21:52, Marcin Juszkiewicz wrote:
W dniu 13.07.2023 o 13:44, Peter Maydell pisze:
I see this isn't a change in this patch, but given that
what the user specifies is not
On Thu, Jul 13, 2023 at 11:12:33PM +0100, Conor Dooley wrote:
> +CC OpenSBI Mailing list
>
> I've not yet had the chance to bisect this, so adding the OpenSBI folks
> to CC in case they might have an idea for what to try.
NVM this, I bisected it. Logs below.
> And a question for you below
On Thu, Jul 13, 2023 at 07:35:01PM -0300, Daniel Henrique Barboza wrote:
> On 7/13/23 19:12, Conor Dooley wrote:
> > And a question for you below Daniel.
> >
> > On Wed, Jul 12, 2023 at 11:14:21PM +0100, Conor Dooley wrote:
> >
> > > qemu-system-riscv64: warning: disabling zca extension for
On 7/13/23 19:12, Conor Dooley wrote:
+CC OpenSBI Mailing list
I've not yet had the chance to bisect this, so adding the OpenSBI folks
to CC in case they might have an idea for what to try.
And a question for you below Daniel.
On Wed, Jul 12, 2023 at 11:14:21PM +0100, Conor Dooley wrote:
+CC OpenSBI Mailing list
I've not yet had the chance to bisect this, so adding the OpenSBI folks
to CC in case they might have an idea for what to try.
And a question for you below Daniel.
On Wed, Jul 12, 2023 at 11:14:21PM +0100, Conor Dooley wrote:
> On Wed, Jul 12, 2023 at 06:39:28PM -0300,
On 13/7/23 23:14, Richard Henderson wrote:
Use generic routines for 8-bit carry-less multiply.
Remove our local version of pmull_h.
Signed-off-by: Richard Henderson
---
target/arm/tcg/vec_internal.h | 5 ---
target/arm/tcg/mve_helper.c | 8 ++---
target/arm/tcg/vec_helper.c | 63
Hi Richard,
On 13/7/23 22:23, Richard Henderson wrote:
We adjust CONFIG_ATOMIC128 and CONFIG_CMPXCHG128 with
CONFIG_ATOMIC128_OPT in atomic128.h. It is difficult
to tell when those changes have been applied with the
ifdef we must use with CONFIG_CMPXCHG128. So instead
use HAVE_CMPXCHG128,
On 6/7/23 09:42, Steve Sistare wrote:
Pass the callback function to add_migration_state_change_notifier so
that migration can initialize the notifier on add and clear it on
delete, which simplifies the call sites. Shorten the function names
so the extra arg can be added more legibly. Hide
On 7/13/23 17:40, Richard Henderson wrote:
On 7/12/23 21:57, Daniel Henrique Barboza wrote:
+#define ADD_CPU_PROPERTIES_ARRAY(_dev, _array) \
+ for (prop = _array; prop && prop->name; prop++) { \
+ qdev_property_add_static(_dev, prop); \
+ } \
do { } while(0)
Watch the \ on
Tested-by: Michael Galaxy
Reviewed-by: Michael Galaxy
On 6/30/23 09:25, Steve Sistare wrote:
Add the migration URI "file:filename[,offset=offset]".
Fabiano Rosas has submitted the unit tests in the series
migration: Test the new "file:" migration
Steve Sistare (2):
migration: file URI
On 7/7/23 15:20, Steve Sistare wrote:
Modify migrate_add_blocker and migrate_del_blocker to take an Error **
reason. This allows migration to own the Error object, so that if
an error occurs, migration code can free the Error and clear the client
handle, simplifying client code.
This is also
Signed-off-by: Richard Henderson
---
host/include/generic/host/crypto/clmul.h | 4 +++
include/crypto/clmul.h | 23 ++
crypto/clmul.c | 31
3 files changed, 58 insertions(+)
diff --git
Use generic routines for 16-bit carry-less multiply.
Remove our local version of galois_multiply16.
Signed-off-by: Richard Henderson
---
target/s390x/tcg/vec_int_helper.c | 22 +++---
1 file changed, 19 insertions(+), 3 deletions(-)
diff --git
Signed-off-by: Richard Henderson
---
host/include/generic/host/crypto/clmul.h | 17 ++
include/crypto/clmul.h | 61 +++
crypto/clmul.c | 76
crypto/meson.build | 9 ++-
4 files
Signed-off-by: Richard Henderson
---
host/include/generic/host/crypto/clmul.h | 2 ++
include/crypto/clmul.h | 7 +++
crypto/clmul.c | 17 +
3 files changed, 26 insertions(+)
diff --git a/host/include/generic/host/crypto/clmul.h
Detect PCLMUL in cpuinfo; implement the accel hooks.
Signed-off-by: Richard Henderson
---
host/include/i386/host/cpuinfo.h| 1 +
host/include/i386/host/crypto/clmul.h | 187
host/include/x86_64/host/crypto/clmul.h | 1 +
util/cpuinfo-i386.c
Use generic routines for 32-bit carry-less multiply.
Remove our local version of galois_multiply32.
Signed-off-by: Richard Henderson
---
target/s390x/tcg/vec_int_helper.c | 70 ---
1 file changed, 17 insertions(+), 53 deletions(-)
diff --git
Use generic routines for 32-bit carry-less multiply.
Signed-off-by: Richard Henderson
---
target/ppc/int_helper.c | 27 +++
1 file changed, 7 insertions(+), 20 deletions(-)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 98d6310f59..828f04bce7
Use generic routines for 8-bit carry-less multiply.
Signed-off-by: Richard Henderson
---
target/ppc/int_helper.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 834da80fe3..3bf0f5dbe5 100644
---
Use generic routines for 16-bit carry-less multiply.
Signed-off-by: Richard Henderson
---
target/ppc/int_helper.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 3bf0f5dbe5..98d6310f59 100644
---
Use generic routines for 16-bit carry-less multiply.
Remove our local version of pmull_w.
Signed-off-by: Richard Henderson
---
target/arm/tcg/vec_internal.h | 6 --
target/arm/tcg/mve_helper.c | 8 ++--
target/arm/tcg/vec_helper.c | 13 -
3 files changed, 2
Signed-off-by: Richard Henderson
---
host/include/generic/host/crypto/clmul.h | 5 +++
include/crypto/clmul.h | 32 +++
crypto/clmul.c | 39
3 files changed, 76 insertions(+)
diff --git
Detect PMULL in cpuinfo; implement the accel hooks.
Signed-off-by: Richard Henderson
---
host/include/aarch64/host/cpuinfo.h | 1 +
host/include/aarch64/host/crypto/clmul.h | 230 +++
util/cpuinfo-aarch64.c | 4 +-
3 files changed, 234
Use generic routine for 64-bit carry-less multiply.
Signed-off-by: Richard Henderson
---
target/arm/tcg/vec_helper.c | 22 --
1 file changed, 4 insertions(+), 18 deletions(-)
diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c
index c81447e674..1a21aff4d9
Use the generic routine for 64-bit carry-less multiply.
Remove our local version of galois_multiply64.
Signed-off-by: Richard Henderson
---
target/s390x/tcg/vec_int_helper.c | 62 +++
1 file changed, 14 insertions(+), 48 deletions(-)
diff --git
Use generic routines for 8-bit carry-less multiply.
Remove our local version of pmull_h.
Signed-off-by: Richard Henderson
---
target/arm/tcg/vec_internal.h | 5 ---
target/arm/tcg/mve_helper.c | 8 ++---
target/arm/tcg/vec_helper.c | 63 +++
3 files
Inspired by Ard Biesheuvel's RFC patches [1] for accelerating
carry-less multiply under emulation.
This is less polished than the AES patch set:
(1) Should I split HAVE_CLMUL_ACCEL into per-width HAVE_CLMUL{N}_ACCEL?
The "_generic" and "_accel" split is different from aes-round.h
because
Use generic routine for 64-bit carry-less multiply.
Signed-off-by: Richard Henderson
---
target/ppc/int_helper.c | 17 +++--
1 file changed, 3 insertions(+), 14 deletions(-)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 828f04bce7..4e1fa2fd68 100644
---
Use generic routines for 8-bit carry-less multiply.
Remove our local version of galois_multiply8.
Signed-off-by: Richard Henderson
---
target/s390x/tcg/vec_int_helper.c | 27 ---
1 file changed, 24 insertions(+), 3 deletions(-)
diff --git
Use generic routines for 32-bit carry-less multiply.
Remove our local version of pmull_d.
Signed-off-by: Richard Henderson
---
target/arm/tcg/vec_helper.c | 14 +-
1 file changed, 1 insertion(+), 13 deletions(-)
diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c
On 7/12/23 21:57, Daniel Henrique Barboza wrote:
+#define ADD_CPU_PROPERTIES_ARRAY(_dev, _array) \
+for (prop = _array; prop && prop->name; prop++) { \
+qdev_property_add_static(_dev, prop); \
+} \
do { } while(0)
Watch the \ on the last line of the macro.
Declare the iterator
We adjust CONFIG_ATOMIC128 and CONFIG_CMPXCHG128 with
CONFIG_ATOMIC128_OPT in atomic128.h. It is difficult
to tell when those changes have been applied with the
ifdef we must use with CONFIG_CMPXCHG128. So instead
use HAVE_CMPXCHG128, which triggers -Werror-undef when
the proper header has not
..
include/standard-headers/drm/drm_fourcc.h | 8 +++---
include/standard-headers/linux/ethtool.h | 2 +-
.../standard-headers/linux/virtio_console.h | 2 +-
include/standard-headers/linux/virtio_i2c.h | 2 +-
include/standard-headers/linux/virtio_net.h | 4 +--
It
On 16.06.2023 11:26, David Hildenbrand wrote:
Having large virtio-mem devices that only expose little memory to a VM
is currently a problem: we map the whole sparse memory region into the
guest using a single memslot, resulting in one gigantic memslot in KVM.
KVM allocates metadata for the whole
Hi,
I've encountered a bug where two vcpu threads enter a device's MMIO
emulation callback at the same time. This is never supposed to happen
thanks to the Big QEMU Lock (BQL), but drain_call_rcu() and nested event
loops make it possible:
1. A device's MMIO emulation callback invokes
On 7/13/23 13:34, Gavin Shan wrote:
Hi Peter and Marcin,
On 7/13/23 21:52, Marcin Juszkiewicz wrote:
W dniu 13.07.2023 o 13:44, Peter Maydell pisze:
I see this isn't a change in this patch, but given that
what the user specifies is not "cortex-a8-arm-cpu" but
"cortex-a8", why do we include
I got annoyed enough by various misspellings, and tried to clean up this
a bit. And got this in the result, for now:
https://gitlab.com/mjt0k/qemu/-/commit/eb5a376c7282e63d9e11eb952046b01f1a5ae7d4
Below is a diffstat plus a few actual changes as a sample.
It fixes misspellings in comments and
On 7/13/23 13:18, Peter Maydell wrote:
On Thu, 13 Jul 2023 at 18:16, Stefan Berger wrote:
I guess the first point would be to decide whether to support an i2c bus on the
virt board and then whether we can use the aspeed bus that we know that the
tpm_tis_i2c device model works with but we
On 7/12/23 23:51, Joelle van Dyne wrote:
Since this device is gated to only build for targets with the PC
configuration, we should use the ISA bus like with TPM TIS.
Signed-off-by: Joelle van Dyne
I think this patch is good but I'd like to try it with resuming and old VM
snapshot and for
On 7/13/23 14:15, Joelle van Dyne wrote:
On Thu, Jul 13, 2023 at 9:49 AM Stefan Berger wrote:
The tpm-tis-device doesn't work for x86_64 but for aarch64.
We have this here in this file:
DEFINE_PROP_BOOL("ppi", TPMStateSysBus, state.ppi_enabled, false),
I don't know whether ppi
On 7/10/23 16:21, Peter Maydell wrote:
In get_phys_addr_twostage() the code that applies the effects of
VSTCR.{SA,SW} and VTCR.{NSA,NSW} only updates result->f.attrs.secure.
Now we also have f.attrs.space for FEAT_RME, we need to keep the two
in sync.
These bits only have an effect for Secure
On 7/13/23 14:10, Joelle van Dyne wrote:
In that case, do you think we should have a check in "realize" to make
sure the backend is 2.0?
Maybe. I think at the moment it would simply not work (with existing drivers)
without terminating QEMU on it due to the misconfiguration. On libvirt
On 7/10/23 16:21, Peter Maydell wrote:
In commit XXX we rearranged the logic in S1_ptw_translate() so that
the debug-access "call get_phys_addr_*" codepath is used both when S1
is doing ptw reads from stage 2 and when it is doing ptw reads from
physical memory. However, we didn't update the
On Thu, Jul 13, 2023 at 9:49 AM Stefan Berger wrote:
>
>
> The tpm-tis-device doesn't work for x86_64 but for aarch64.
>
>
> We have this here in this file:
>
> DEFINE_PROP_BOOL("ppi", TPMStateSysBus, state.ppi_enabled, false),
>
> I don't know whether ppi would work on aarch64. It needs
In that case, do you think we should have a check in "realize" to make
sure the backend is 2.0?
On Thu, Jul 13, 2023 at 9:08 AM Stefan Berger wrote:
>
>
>
> On 7/12/23 23:51, Joelle van Dyne wrote:
> > This logic is similar to TPM TIS ISA device.
> >
> > Signed-off-by: Joelle van Dyne
> > ---
>
On Thu, Jul 13, 2023 at 8:31 AM Peter Maydell wrote:
>
> On Thu, 13 Jul 2023 at 04:52, Joelle van Dyne wrote:
> >
> > TPM needs to know its own base address in order to generate its DSDT
> > device entry.
> >
> > Signed-off-by: Joelle van Dyne
> > ---
> > hw/arm/virt.c | 37
Hi Stefan,
On 7/13/23 19:19, Stefan Berger wrote:
> The ppi command line option for the TIS device on sysbus never worked
> and caused an immediate segfault. Remove support for it since it also
> needs support in the firmware and needs testing inside the VM.
>
> Reproducer with the ppi=on option
On 7/10/23 16:21, Peter Maydell wrote:
Add comments to the in_* fields in the S1Translate struct
that explain what they're doing.
Signed-off-by: Peter Maydell
---
I figured some of this out when writing commit fcc0b0418fff,
and then I found I'd forgotten it all when I was trying
to fix this new
On Thu, Jul 13, 2023 at 6:07 AM Stefan Berger wrote:
>
>
>
> On 7/12/23 23:51, Joelle van Dyne wrote:
> > The impetus for this patch set is to get TPM 2.0 working on Windows 11
> > ARM64.
> > Windows' tpm.sys does not seem to work on a TPM TIS device (as verified with
> > VMWare's
The ppi command line option for the TIS device on sysbus never worked
and caused an immediate segfault. Remove support for it since it also
needs support in the firmware and needs testing inside the VM.
Reproducer with the ppi=on option passed:
qemu-system-aarch64 \
-machine
On Thu, 13 Jul 2023 at 18:16, Stefan Berger wrote:
> I guess the first point would be to decide whether to support an i2c bus on
> the virt board and then whether we can use the aspeed bus that we know that
> the tpm_tis_i2c device model works with but we don't know how Windows may
> react to
On 7/13/23 13:07, Peter Maydell wrote:
On Thu, 13 Jul 2023 at 17:54, Stefan Berger wrote:
On 7/13/23 11:55, Peter Maydell wrote:
On Thu, 13 Jul 2023 at 16:46, Stefan Berger wrote:
On 7/13/23 11:34, Peter Maydell wrote:
On Thu, 13 Jul 2023 at 16:28, Stefan Berger wrote:
On 7/13/23
On Thu, 13 Jul 2023 at 17:54, Stefan Berger wrote:
>
>
>
> On 7/13/23 11:55, Peter Maydell wrote:
> > On Thu, 13 Jul 2023 at 16:46, Stefan Berger wrote:
> >> On 7/13/23 11:34, Peter Maydell wrote:
> >>> On Thu, 13 Jul 2023 at 16:28, Stefan Berger wrote:
> On 7/13/23 10:50, Peter Maydell
On 7/13/23 11:55, Peter Maydell wrote:
On Thu, 13 Jul 2023 at 16:46, Stefan Berger wrote:
On 7/13/23 11:34, Peter Maydell wrote:
On Thu, 13 Jul 2023 at 16:28, Stefan Berger wrote:
On 7/13/23 10:50, Peter Maydell wrote:
I'm not a super-fan of hacking around the fact that LDP
to hardware
On 7/12/23 23:51, Joelle van Dyne wrote:
If 'ppi' property is set, then `tpm_ppi_reset` is called on reset
which SEGFAULTs because `tpmppi->buf` is not allocated.
Signed-off-by: Joelle van Dyne
---
hw/tpm/tpm_tis_sysbus.c | 4
1 file changed, 4 insertions(+)
diff --git
On 13/7/23 14:34, Gavin Shan wrote:
Hi Peter and Marcin,
On 7/13/23 21:52, Marcin Juszkiewicz wrote:
W dniu 13.07.2023 o 13:44, Peter Maydell pisze:
I see this isn't a change in this patch, but given that
what the user specifies is not "cortex-a8-arm-cpu" but
"cortex-a8", why do we include
> -Original Message-
> From: Anton Johansson
> Sent: Thursday, July 13, 2023 7:09 AM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; peter.mayd...@linaro.org
> Subject: [PATCH] target/hexagon/idef-parser: Remove self-assignment
>
> WARNING: This email originated from outside of
On 13/7/23 14:08, Anton Johansson via wrote:
The self assignment is clearly useless, and @1.last_column does not have
to be set for an expression with only a single token, so remove it.
Reported-by: Peter Maydell
Signed-off-by: Anton Johansson
---
target/hexagon/idef-parser/idef-parser.y |
On 7/12/23 23:51, Joelle van Dyne wrote:
This logic is similar to TPM TIS ISA device.
Signed-off-by: Joelle van Dyne
---
hw/i386/acpi-build.c | 23 ---
hw/tpm/tpm_crb.c | 28
2 files changed, 28 insertions(+), 23 deletions(-)
diff
On 7/12/23 23:51, Joelle van Dyne wrote:
Instead of calling `memory_region_add_subregion` directly, we defer to
the caller to do it. This allows us to re-use the code for a SysBus
device.
Signed-off-by: Joelle van Dyne
Reviewed-by: Stefan Berger
---
hw/tpm/tpm_ppi.h| 10
On Thu, 13 Jul 2023 at 16:46, Stefan Berger wrote:
> On 7/13/23 11:34, Peter Maydell wrote:
> > On Thu, 13 Jul 2023 at 16:28, Stefan Berger wrote:
> >> On 7/13/23 10:50, Peter Maydell wrote:
> >>> I'm not a super-fan of hacking around the fact that LDP
> >>> to hardware registers isn't supported
Good morning,
On 7/10/23 10:10, Steven Sistare wrote:
On 6/12/2023 10:59 AM, Michael Galaxy wrote:
Hi Steve,
On 6/7/23 12:37, Steven Sistare wrote:
On 6/7/2023 11:55 AM, Michael Galaxy wrote:
Another option could be to expose "-migrate-mode-disable" (instead of enable)
and just enable all
On 7/13/23 11:34, Peter Maydell wrote:
On Thu, 13 Jul 2023 at 16:28, Stefan Berger wrote:
On 7/13/23 10:50, Peter Maydell wrote:
On Thu, 13 Jul 2023 at 15:18, Stefan Berger wrote:
On 7/12/23 23:51, Joelle van Dyne wrote:
On Apple Silicon, when Windows performs a LDP on the CRB
On 7/13/23 12:32, Peter Maydell wrote:
On Fri, 7 Jul 2023 at 11:30, Richard Henderson
wrote:
Read the left and right trees once, so that the gating
tests are meaningful. This was only a problem at -O0,
where the compiler didn't CSE the two reads.
Cc: qemu-sta...@nongnu.org
Signed-off-by:
On 7/12/23 23:51, Joelle van Dyne wrote:
The register is actually 64-bits but in order to make this more clear
than the specification, we define two 32-bit registers:
CTRL_RSP_LADDR and CTRL_RSP_HADDR to match the CTRL_CMD_* naming. This
deviates from the specs but is way more clear.
On Thu, 13 Jul 2023 at 16:28, Stefan Berger wrote:
>
>
>
> On 7/13/23 10:50, Peter Maydell wrote:
> > On Thu, 13 Jul 2023 at 15:18, Stefan Berger wrote:
> >>
> >>
> >>
> >> On 7/12/23 23:51, Joelle van Dyne wrote:
> >>> On Apple Silicon, when Windows performs a LDP on the CRB MMIO space,
> >>>
On Thu, 13 Jul 2023 at 04:52, Joelle van Dyne wrote:
>
> TPM needs to know its own base address in order to generate its DSDT
> device entry.
>
> Signed-off-by: Joelle van Dyne
> ---
> hw/arm/virt.c | 37 +
> 1 file changed, 37 insertions(+)
>
> diff --git
On 7/13/23 10:50, Peter Maydell wrote:
On Thu, 13 Jul 2023 at 15:18, Stefan Berger wrote:
On 7/12/23 23:51, Joelle van Dyne wrote:
On Apple Silicon, when Windows performs a LDP on the CRB MMIO space,
the exception is not decoded by hardware and we cannot trap the MMIO
read. This led to
On Thu, 13 Jul 2023 at 15:18, Stefan Berger wrote:
>
>
>
> On 7/12/23 23:51, Joelle van Dyne wrote:
> > On Apple Silicon, when Windows performs a LDP on the CRB MMIO space,
> > the exception is not decoded by hardware and we cannot trap the MMIO
> > read. This led to the idea from @agraf to use
On 7/12/23 23:51, Joelle van Dyne wrote:
On Apple Silicon, when Windows performs a LDP on the CRB MMIO space,
the exception is not decoded by hardware and we cannot trap the MMIO
read. This led to the idea from @agraf to use the same mapping type as
ROM devices: namely that reads should be
On 2023/07/12 21:06, Michael S. Tsirkin wrote:
On Wed, Jul 12, 2023 at 08:50:32PM +0900, Akihiko Odaki wrote:
On 2023/07/12 20:46, Michael S. Tsirkin wrote:
On Wed, Jul 12, 2023 at 08:27:32PM +0900, Akihiko Odaki wrote:
Current SR/IOV implementations assume that hardcoded Function numbers
are
On 7/12/23 23:51, Joelle van Dyne wrote:
In preparation for the SysBus variant, we move common code styled
after the TPM TIS devices.
To maintain compatibility, we do not rename the existing tpm-crb
device.
Signed-off-by: Joelle van Dyne
---
docs/specs/tpm.rst | 1 +
QEMU Summit Minutes 2023
As usual, we held a QEMU Summit meeting at KVM Forum. This is an
invite-only meeting for the most active maintainers and submaintainers
in the project, and we discuss various project-wide issues, usually
process stuff. We then post the minutes of
Peter Maydell writes:
> On Thu, 6 Jul 2023 at 20:52, Fabiano Rosas wrote:
>>
>> The convention in qemu-file.c is to return a negative value on
>> error.
>>
>> The only place that could use qemu_file_set_error() to store a
>> positive value to f->last_error was vmstate_save() which has been
>>
Hi Connie,
On 7/13/23 22:46, Cornelia Huck wrote:
On Thu, Jul 13 2023, Gavin Shan wrote:
The CPU type 'host-arm-cpu' class won't be registered until KVM or
HVF is configured in target/arm/cpu64.c. Support the corresponding
CPU type only when KVM or HVF is configured.
Signed-off-by: Gavin
On 7/12/23 23:51, Joelle van Dyne wrote:
TPM needs to know its own base address in order to generate its DSDT
device entry.
This and the loongarch patch seem to have largely identical virt_tpm_plug
functions.
Could they be consolidated in hw/tpm/virt.c ?
Stefan
Signed-off-by: Joelle
I'll take this via target-arm.next unless there are any
objections...
thanks
-- PMM
On Tue, 4 Jul 2023 at 14:26, Peter Maydell wrote:
>
> Laurent, ping? This patch has been reviewed.
>
> thanks
> -- PMM
>
> On Fri, 23 Jun 2023 at 15:44, Peter Maydell wrote:
> >
> > In the code for
On 7/12/23 23:51, Joelle van Dyne wrote:
The impetus for this patch set is to get TPM 2.0 working on Windows 11 ARM64.
Windows' tpm.sys does not seem to work on a TPM TIS device (as verified with
VMWare's implementation). However, the current TPM CRB device uses a fixed
system bus address
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