On 2023/7/15 01:43, Daniel Henrique Barboza wrote:
The 'max' CPU type is used by tooling to determine what's the most
capable CPU a current QEMU version implements. Other archs such as ARM
implements this type. Let's add it to RISC-V.
What we consider "most capable CPU" in this context are rel
On 2023/7/15 01:43, Daniel Henrique Barboza wrote:
The code inside riscv_cpu_add_user_properties() became quite repetitive
after recent changes. Add a macro to hide the repetition away.
Signed-off-by: Daniel Henrique Barboza
---
Reviewed-by: Weiwei Li
Weiwei Li
target/riscv/cpu.c | 21
Adds qtest_irq_intercept_out_named method, which utilizes a new optional
name parameter to the irq_intercept_out qtest command.
Signed-off-by: Chris Laplante
---
softmmu/qtest.c| 39 ++-
tests/qtest/libqtest.c | 6 ++
tests/qtest/libqtest.h | 11 +
This is much better than just silently failing with OK.
Signed-off-by: Chris Laplante
---
softmmu/qtest.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/softmmu/qtest.c b/softmmu/qtest.c
index 051bbf4177..e888acb319 100644
--- a/softmmu/qtest.c
+++ b/softmmu/q
Exercise the DETECT mechanism of the GPIO peripheral.
Signed-off-by: Chris Laplante
---
tests/qtest/microbit-test.c | 42 +
1 file changed, 42 insertions(+)
diff --git a/tests/qtest/microbit-test.c b/tests/qtest/microbit-test.c
index 6022a92b6a..3c85adba37 10
Simplify the code a bit.
Signed-off-by: Chris Laplante
---
softmmu/qtest.c | 23 +++
1 file changed, 11 insertions(+), 12 deletions(-)
diff --git a/softmmu/qtest.c b/softmmu/qtest.c
index 74482ce3cd..051bbf4177 100644
--- a/softmmu/qtest.c
+++ b/softmmu/qtest.c
@@ -365,6 +36
Named interception of in-GPIOs is not supported yet.
Signed-off-by: Chris Laplante
---
softmmu/qtest.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/softmmu/qtest.c b/softmmu/qtest.c
index 7c3dea5760..74482ce3cd 100644
--- a/softmmu/qtest.c
+++ b/softmmu/qtest.c
@@ -4
This patch series implements the nRF51 DETECT signal
in the GPIO peripheral. A qtest is added exercising the signal.
To implement the test, named out-GPIO IRQ interception had to be added
to the qtest framework. I also took the opportunity to improve IRQ
interception a bit by adding 'FAIL' respons
Implement nRF51 DETECT signal in the GPIO peripheral.
The reference manual makes mention of a per-pin DETECT signal, but these
are not exposed to the user. See
https://devzone.nordicsemi.com/f/nordic-q-a/39858/gpio-per-pin-detect-signal-available
for more information. Currently, I don't see a rea
On 7/14/23 11:59, Paolo Bonzini wrote:
The following changes since commit 3dd9e54703e6ae4f9ab3767f5cecc99edf08:
Merge tag 'block-pull-request' ofhttps://gitlab.com/stefanha/qemu into
staging (2023-07-12 20:46:10 +0100)
are available in the Git repository at:
https://gitlab.com/bonz
Hi
On Fri, Jul 14, 2023 at 7:42 PM Erico Nunes wrote:
> virglrenderer recently added virgl_renderer_resource_get_info_ext as a
> new api, which gets resource information, including dmabuf modifiers.
> https://gitlab.freedesktop.org/virgl/virglrenderer/-/merge_requests/1024
>
> We have to support
On 7/14/23 15:44, Joelle van Dyne wrote:
On Fri, Jul 14, 2023 at 12:12 PM Stefan Berger wrote:
On 7/14/23 14:49, Joelle van Dyne wrote:
On Fri, Jul 14, 2023 at 11:41 AM Stefan Berger wrote:
On 7/14/23 14:22, Stefan Berger wrote:
On 7/14/23 13:04, Joelle van Dyne wrote:
On Fri, Jul
14.07.2023 22:43, Michael Tokarev wrote:
..
./arm-linux-user/qemu-arm /usr/lib/klibc/bin/fstype
qemu: uncaught target signal 11 (Segmentation fault) - core dumped
Segmentation fault
Note: the segfault happens before qemu tries to run the program,
apparently when it is doing the file sections pr
14.07.2023 22:40, Alex Williamson wrote:
$ git diff qemu-master..spelling | grep -c re-enable
8
I can drop those 8 out of 400 :)
If we consider codespell to be the authority I guess we can leave it,
but it seems a bit pedantic to me. Thanks,
Let's just drop this one. Please if you conside
On Fri, Jul 14, 2023 at 12:12 PM Stefan Berger wrote:
>
>
>
> On 7/14/23 14:49, Joelle van Dyne wrote:
> > On Fri, Jul 14, 2023 at 11:41 AM Stefan Berger
> > wrote:
> >>
> >>
> >>
> >> On 7/14/23 14:22, Stefan Berger wrote:
> >>> On 7/14/23 13:04, Joelle van Dyne wrote:
> On Fri, Jul 14, 20
On Fri, 14 Jul 2023 21:50:01 +0300
Michael Tokarev wrote:
> 14.07.2023 21:22, Alex Williamson wrote:
> > On Fri, 14 Jul 2023 14:38:06 +0300
> > Michael Tokarev wrote:
> >
> >> diff --git a/hw/ppc/spapr_pci_vfio.c b/hw/ppc/spapr_pci_vfio.c
> >> index d8aeee0b7e..12e7790cf6 100644
> >> --- a/hw
On 7/14/23 14:49, Joelle van Dyne wrote:
On Fri, Jul 14, 2023 at 11:41 AM Stefan Berger wrote:
On 7/14/23 14:22, Stefan Berger wrote:
On 7/14/23 13:04, Joelle van Dyne wrote:
On Fri, Jul 14, 2023 at 7:51 AM Stefan Berger wrote:
On 7/14/23 10:05, Stefan Berger wrote:
On 7/14/23 0
14.07.2023 21:22, Alex Williamson wrote:
On Fri, 14 Jul 2023 14:38:06 +0300
Michael Tokarev wrote:
diff --git a/hw/ppc/spapr_pci_vfio.c b/hw/ppc/spapr_pci_vfio.c
index d8aeee0b7e..12e7790cf6 100644
--- a/hw/ppc/spapr_pci_vfio.c
+++ b/hw/ppc/spapr_pci_vfio.c
@@ -39,7 +39,7 @@ static void spapr_
On Fri, Jul 14, 2023 at 11:41 AM Stefan Berger wrote:
>
>
>
> On 7/14/23 14:22, Stefan Berger wrote:
> > On 7/14/23 13:04, Joelle van Dyne wrote:
> >> On Fri, Jul 14, 2023 at 7:51 AM Stefan Berger
> >> wrote:
> >>>
> >>>
> >>>
> >>> On 7/14/23 10:05, Stefan Berger wrote:
>
>
> On
On 7/14/23 14:22, Stefan Berger wrote:
On 7/14/23 13:04, Joelle van Dyne wrote:
On Fri, Jul 14, 2023 at 7:51 AM Stefan Berger wrote:
On 7/14/23 10:05, Stefan Berger wrote:
On 7/14/23 03:09, Joelle van Dyne wrote:
When we moved to a single mapping and modified TPM CRB's VMState, it
br
Translation logic may partially decode an instruction, then abort and
remove the instruction from the TB. This can happen for example when an
instruction spans two pages. In this case, plugins may get an incorrect
result when calling qemu_plugin_tb_n_insns to query for the number of
instructions in
Hi Philippe,
> num_insns is a 'size_t'.
You are right. I copied the `int` type from `DisasContextBase`, but it
should really be `size_t`. I'll send an updated patch.
Thanks,
Matt
On Fri, Jul 14, 2023 at 11:09 AM Philippe Mathieu-Daudé
wrote:
>
> Hi Matt,
>
> On 14/7/23 06:18, Matt Borgerson wr
In the virtio_iommu_handle_command() when a PROBE request is handled,
output_size takes a value greater than the tail size and on a subsequent
iteration we can get a stack out-of-band access. Initialize the
output_size on each iteration.
The issue was found with ASAN. Credits to:
Yiming Tao(Zhejia
On 7/14/23 13:04, Joelle van Dyne wrote:
On Fri, Jul 14, 2023 at 7:51 AM Stefan Berger wrote:
On 7/14/23 10:05, Stefan Berger wrote:
On 7/14/23 03:09, Joelle van Dyne wrote:
When we moved to a single mapping and modified TPM CRB's VMState, it
broke restoring of VMs that were saved on an
On Fri, 14 Jul 2023 14:38:06 +0300
Michael Tokarev wrote:
> diff --git a/hw/ppc/spapr_pci_vfio.c b/hw/ppc/spapr_pci_vfio.c
> index d8aeee0b7e..12e7790cf6 100644
> --- a/hw/ppc/spapr_pci_vfio.c
> +++ b/hw/ppc/spapr_pci_vfio.c
> @@ -39,7 +39,7 @@ static void spapr_phb_vfio_eeh_reenable(SpaprPhbStat
On Fri, Jul 14, 2023 at 11:01 AM Stefan Berger wrote:
>
>
>
> On 7/14/23 13:46, Joelle van Dyne wrote:
> > On Fri, Jul 14, 2023 at 10:43 AM Stefan Berger
> > wrote:
> >>
> >>
> >>
> >> On 7/14/23 13:39, Joelle van Dyne wrote:
> >>> On Fri, Jul 14, 2023 at 10:37 AM Stefan Berger
> >>> wrote:
>
Hi Matt,
On 14/7/23 06:18, Matt Borgerson wrote:
Translation logic may partially decode an instruction, then abort and
remove the instruction from the TB. This can happen for example when an
instruction spans two pages. In this case, plugins may get an incorrect
result when calling qemu_plugin_t
On 7/14/23 13:58, Philippe Mathieu-Daudé wrote:
Hi Stefan,
On 14/7/23 17:41, Stefan Berger wrote:
The ppi command line option for the TIS device on sysbus never worked
and caused an immediate segfault. Remove support for it since it also
needs support in the firmware and needs testing inside
On 7/14/23 13:46, Joelle van Dyne wrote:
On Fri, Jul 14, 2023 at 10:43 AM Stefan Berger wrote:
On 7/14/23 13:39, Joelle van Dyne wrote:
On Fri, Jul 14, 2023 at 10:37 AM Stefan Berger wrote:
On 7/14/23 13:29, Joelle van Dyne wrote:
On Fri, Jul 14, 2023 at 9:19 AM Stefan Berger wrot
Hi Stefan,
On 14/7/23 17:41, Stefan Berger wrote:
The ppi command line option for the TIS device on sysbus never worked
and caused an immediate segfault. Remove support for it since it also
needs support in the firmware and needs testing inside the VM.
Reproducer with the ppi=on option passed:
On 7/14/23 03:09, Joelle van Dyne wrote:
This logic is similar to TPM TIS ISA device. Since TPM CRB can only
support TPM 2.0 backends, we check for this in realize.
Signed-off-by: Joelle van Dyne
This patch changes the order of in which the ACPI table elements are created
but doesn't matt
On 7/14/23 13:20, Joelle van Dyne wrote:
On Fri, Jul 14, 2023 at 7:27 AM Stefan Berger wrote:
On 7/14/23 03:09, Joelle van Dyne wrote:
This SysBus variant of the CRB interface supports dynamically locating
the MMIO interface so that Virt machines can use it. This interface
is currently t
Hi Peter,
On 14/7/23 19:26, Peter Maydell wrote:
In CPUSparcState we define the fprs field as uint64_t. However we
then refer to it in translate.c via a TCGv_i32 which we set up with
tcg_global_mem_new_ptr(). This means that on a big-endian host when
the guest does something to writo te the FP
On Fri, Jul 14, 2023 at 10:43 AM Stefan Berger wrote:
>
>
>
> On 7/14/23 13:39, Joelle van Dyne wrote:
> > On Fri, Jul 14, 2023 at 10:37 AM Stefan Berger
> > wrote:
> >>
> >>
> >>
> >> On 7/14/23 13:29, Joelle van Dyne wrote:
> >>> On Fri, Jul 14, 2023 at 9:19 AM Stefan Berger
> >>> wrote:
> >
Create a new riscv_cpu_experimental_exts[] to store the non-ratified
extensions properties. Once they are ratified we'll move them back to
riscv_cpu_extensions[].
Change riscv_cpu_add_user_properties to keep adding them to users.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Franc
Our goal is to make riscv_cpu_extensions[] hold only ratified,
non-vendor extensions.
Create a new riscv_cpu_vendor_exts[] array for them, changing
riscv_cpu_add_user_properties() accordingly.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 33
Hi,
This version has changes suggested in v2. The most significant change is
the deprecation of the 'any' CPU in patch 8.
The reasoning behind it is that Alistair mentioned that the 'any' CPU
intended to work like the newly added 'max' CPU, so we're better of
removing the 'any' CPU since it'll be
The code inside riscv_cpu_add_user_properties() became quite repetitive
after recent changes. Add a macro to hide the repetition away.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 21 ++---
1 file changed, 10 insertions(+), 11 deletions(-)
diff --git a/target/
The 'max' CPU type is used by tooling to determine what's the most
capable CPU a current QEMU version implements. Other archs such as ARM
implements this type. Let's add it to RISC-V.
What we consider "most capable CPU" in this context are related to
ratified, non-vendor extensions. This means tha
The 'any' CPU type was introduced in commit dc5bd18fa5725 ("RISC-V CPU
Core Definition"), being around since the beginning. It's not an easy
CPU to use: it's undocumented and its name doesn't tell users much about
what the CPU is supposed to bring. 'git log' doesn't help us either in
knowing what w
On 7/14/23 13:39, Joelle van Dyne wrote:
On Fri, Jul 14, 2023 at 10:37 AM Stefan Berger wrote:
On 7/14/23 13:29, Joelle van Dyne wrote:
On Fri, Jul 14, 2023 at 9:19 AM Stefan Berger wrote:
I don't know whether we would want multiple devices. tpm_find() usage is
certainly not prepa
After the introduction of riscv_cpu_options[] all properties in
riscv_cpu_extensions[] are booleans. This check is now obsolete.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 14 --
1 file changed, 4 insertions(+), 10 deletions(-)
dif
We'll add a new CPU type that will enable a considerable amount of
extensions. To make it easier for us we'll do a few cleanups in our
existing riscv_cpu_extensions[] array.
Start by splitting all CPU non-boolean options from it. Create a new
riscv_cpu_options[] array for them. Add all these prope
Add smoke tests to ensure that we'll not break the 'max' CPU type when
adding new ratified extensions to be enabled.
Signed-off-by: Daniel Henrique Barboza
---
tests/avocado/riscv_opensbi.py | 16
1 file changed, 16 insertions(+)
diff --git a/tests/avocado/riscv_opensbi.py b/te
On Fri, Jul 14, 2023 at 10:37 AM Stefan Berger wrote:
>
>
>
> On 7/14/23 13:29, Joelle van Dyne wrote:
> > On Fri, Jul 14, 2023 at 9:19 AM Stefan Berger wrote:
> >>
> >>
> >>
> >>
> >> I don't know whether we would want multiple devices. tpm_find() usage is
> >> certainly not prepared for multip
On Fri, Jul 14, 2023 at 4:57 AM Stefan Berger wrote:
>
>
>
> On 7/14/23 06:05, Peter Maydell wrote:
> > On Thu, 13 Jul 2023 at 19:43, Stefan Berger wrote:
> >>
> >>
> >>
> >> On 7/13/23 13:18, Peter Maydell wrote:
> >>> On Thu, 13 Jul 2023 at 18:16, Stefan Berger wrote:
> I guess the first
On 7/14/23 13:29, Joelle van Dyne wrote:
On Fri, Jul 14, 2023 at 9:19 AM Stefan Berger wrote:
I don't know whether we would want multiple devices. tpm_find() usage is
certainly not prepared for multiple devices.
Sorry, "multiple TPM interfaces" here does not mean "at the same
time". Wi
On Fri, 14 Jul 2023 at 18:26, Peter Maydell wrote:
>
> In CPUSparcState we define the fprs field as uint64_t. However we
> then refer to it in translate.c via a TCGv_i32 which we set up with
> tcg_global_mem_new_ptr(). This means that on a big-endian host when
> the guest does something to writo
On Fri, Jul 14, 2023 at 9:19 AM Stefan Berger wrote:
>
>
>
>
> I don't know whether we would want multiple devices. tpm_find() usage is
> certainly not prepared for multiple devices.
Sorry, "multiple TPM interfaces" here does not mean "at the same
time". Will clarify the description.
>
>
> Good
In CPUSparcState we define the fprs field as uint64_t. However we
then refer to it in translate.c via a TCGv_i32 which we set up with
tcg_global_mem_new_ptr(). This means that on a big-endian host when
the guest does something to writo te the FPRS register this value
ends up in the wrong half of
On Fri, Jul 14, 2023 at 7:27 AM Stefan Berger wrote:
>
>
>
> On 7/14/23 03:09, Joelle van Dyne wrote:
> > This SysBus variant of the CRB interface supports dynamically locating
> > the MMIO interface so that Virt machines can use it. This interface
> > is currently the only one supported by QEMU t
On Fri, Jul 14, 2023 at 5:11 AM Stefan Berger wrote:
>
>
>
> On 7/14/23 03:09, Joelle van Dyne wrote:
> > TPM needs to know its own base address in order to generate its DSDT
> > device entry.
> >
> > Signed-off-by: Joelle van Dyne
> > ---
> > hw/arm/virt.c | 37
On Fri, Jul 14, 2023 at 7:51 AM Stefan Berger wrote:
>
>
>
> On 7/14/23 10:05, Stefan Berger wrote:
> >
> >
> > On 7/14/23 03:09, Joelle van Dyne wrote:
> >> When we moved to a single mapping and modified TPM CRB's VMState, it
> >> broke restoring of VMs that were saved on an older version. This
>
On 7/14/23 17:35, Eric Blake wrote:
On Thu, Jul 06, 2023 at 09:15:45PM +0200, Denis V. Lunev wrote:
Commit e6df58a5578fee7a50bbf36f4a50a2781cff855d
Author: Hanna Reitz
Date: Wed May 8 23:18:18 2019 +0200
qemu-nbd: Do not close stderr
has introduced an interesting regression. Or
On Wed, 2023-07-12 at 22:11 +0200, Thomas Huth wrote:
> On 12/07/2023 21.37, Nina Schoetterl-Glausch wrote:
> > On Wed, 2023-07-05 at 12:22 +0200, Thomas Huth wrote:
> > > On 30/06/2023 11.17, Pierre Morel wrote:
> > > > This test takes care to check the changes on different
> > > > entitlements
>
On 7/14/23 03:09, Joelle van Dyne wrote:
This reduces redundent code in different machine types with ACPI table
generation. Additionally, this will allow us to support multiple TPM
interfaces. Finally, this matches up with the TPM TIS ISA
I don't know whether we would want multiple devices.
The PAR_EL1.SH field documents that for the cases of:
* Device memory
* Normal memory with both Inner and Outer Non-Cacheable
the field should be 0b10 rather than whatever was in the
translation table descriptor field. (In the pseudocode this
is handled by PAREncodeShareability().) Perform this
a
Plumb the ARMSecurityState through to regime_translation_disabled()
rather than just a bool is_secure.
Signed-off-by: Peter Maydell
---
target/arm/ptw.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index a873fbe0239..63dd
Replace the last uses of ptw->in_secure with appropriate
checks on ptw->in_space.
Signed-off-by: Peter Maydell
---
target/arm/ptw.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index c30d3fe69a0..bc834675fb2 100644
--- a/targ
When we do a translation in Secure state, the NSTable bits in table
descriptors may downgrade us to NonSecure; we update ptw->in_secure
and ptw->in_space accordingly. We guard that check correctly with a
conditional that means it's only applied for Secure stage 1
translations. However, later on i
When we report faults due to stage 2 faults during a stage 1
page table walk, the 'level' parameter should be the level
of the walk in stage 2 that faulted, not the level of the
walk in stage 1. Correct the reporting of these faults.
Signed-off-by: Peter Maydell
---
target/arm/ptw.c | 10 +++
In S1_ptw_translate() we set up the ARMMMUFaultInfo if the attempt to
translate the page descriptor address into a physical address fails.
This used to only be possible if we are doing a stage 2 ptw for that
descriptor address, and so the code always sets fi->stage2 and
fi->s1ptw to true. However,
For an Unsupported Atomic Update fault where the stage 1 translation
table descriptor update can't be done because it's to an unsupported
memory type, this is a stage 1 abort (per the Arm ARM R_VSXXT). This
means we should not set fi->s1ptw, because this will cause the code
in the get_phys_addr_lp
Based-on: 20230710152130.3928330-1-peter.mayd...@linaro.org
("target/arm: Fix ptw bugs introduced by FEAT_RME changes")
While I was fixing the ptw bug in the series above, I noticed
that we had a somewhat confusing mix of ptw->in_space and
ptw->in_secure, where in theory the two are supposed to be
In commit 6d2654ffacea813916176 we created the S1Translate struct and
used it to plumb through various arguments that we were previously
passing one-at-a-time to get_phys_addr_v5(), get_phys_addr_v6(), and
get_phys_addr_lpae(). Extend that pattern to get_phys_addr_pmsav5(),
get_phys_addr_pmsav7(),
The s1ns bit in ARMMMUFaultInfo is documented as "true if
we faulted on a non-secure IPA while in secure state". Both the
places which look at this bit only do so after having confirmed
that this is a stage 2 fault and we're dealing with Secure EL2,
which leaves the ptw.c code free to set the bit t
The architecture doesn't permit block descriptors at any arbitrary
level of the page table walk; it depends on the granule size which
levels are permitted. We implemented only a partial version of this
check which assumes that block descriptors are valid at all levels
except level 3, which meant t
arm_hcr_el2_eff_secstate() takes a bool secure, which it uses to
determine whether EL2 is enabled in the current security state.
With the advent of FEAT_RME this is no longer sufficient, because
EL2 can be enabled for Secure state but not for Root, and both
of those will pass 'secure == true' in th
We no longer look at the in_secure field of the S1Translate struct
anyway, so we can remove it and all the code which sets it.
Signed-off-by: Peter Maydell
---
target/arm/ptw.c | 13 -
1 file changed, 13 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index bc834675fb2
When the MMU is disabled, data accesses should be Device nGnRnE,
Outer Shareable, Untagged. We handle the other cases from
AArch64.S1DisabledOutput() correctly but missed this one.
Device nGnRnE is memattr == 0, so the only part we were missing
was that shareability should be set to 2 for both ins
We only use S1Translate::out_secure in two places, where we are
setting up MemTxAttrs for a page table load. We can use
arm_space_is_secure(ptw->out_space) instead, which guarantees
that we're setting the MemTxAttrs secure and space fields
consistently, and allows us to drop the out_secure field in
The ppi command line option for the TIS device on sysbus never worked
and caused an immediate segfault. Remove support for it since it also
needs support in the firmware and needs testing inside the VM.
Reproducer with the ppi=on option passed:
qemu-system-aarch64 \
-machine virt,gic-version=3
Hello!
This PR removes the 'ppi' boolean property from the tpm tis sysbus
device. It could never be activated since it was leading to a segfault
immediatley.
Stefan
The following changes since commit 3dd9e54703e6ae4f9ab3767f5cecc99edf08:
Merge tag 'block-pull-request' of https://git
virglrenderer recently added virgl_renderer_resource_get_info_ext as a
new api, which gets resource information, including dmabuf modifiers.
We have to support dmabuf modifiers since the driver may choose to
allocate buffers with these modifiers for efficiency, and importing
buffers without modifi
VHOST_USER_GPU_DMABUF_SCANOUT2 is defined as a message with all the
contents of VHOST_USER_GPU_DMABUF_SCANOUT plus the dmabuf modifiers
which were ommitted.
The VHOST_USER_GPU_PROTOCOL_F_DMABUF2 protocol feature is defined as a
way to check whether this new message is supported or not.
Signed-off
When the backend sends VHOST_USER_GPU_DMABUF_SCANOUT2, handle it
by getting the modifiers information which is now available.
Signed-off-by: Erico Nunes
---
hw/display/vhost-user-gpu.c | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/hw/display/vhost-user-gpu
virglrenderer recently added virgl_renderer_resource_get_info_ext as a
new api, which gets resource information, including dmabuf modifiers.
https://gitlab.freedesktop.org/virgl/virglrenderer/-/merge_requests/1024
We have to support dmabuf modifiers since the driver may choose to
allocate buffers
On Thu, Jul 06, 2023 at 09:15:45PM +0200, Denis V. Lunev wrote:
> Commit e6df58a5578fee7a50bbf36f4a50a2781cff855d
> Author: Hanna Reitz
> Date: Wed May 8 23:18:18 2019 +0200
> qemu-nbd: Do not close stderr
> has introduced an interesting regression. Original behavior of
> ssh som
On Tue, Jul 04, 2023 at 11:56:54AM +0200, Roger Pau Monné wrote:
> On Tue, Jul 04, 2023 at 10:37:38AM +0100, Anthony PERARD wrote:
> > On Wed, Jun 28, 2023 at 02:31:39PM +0200, Roger Pau Monné wrote:
> > > On Fri, Jun 23, 2023 at 03:04:21PM +, osstest service owner wrote:
> > > > flight 181558
From: Anthony PERARD
thread_pool_free() might have been called on the `pool`, which would
be a reason for worker_thread() to quit. In this case,
`pool->request_cond` is been destroyed.
If worker_thread() didn't managed to signal `request_cond` before it
been destroyed by thread_pool_free(), we g
On 7/14/23 10:05, Stefan Berger wrote:
On 7/14/23 03:09, Joelle van Dyne wrote:
When we moved to a single mapping and modified TPM CRB's VMState, it
broke restoring of VMs that were saved on an older version. This
change allows those VMs to gracefully migrate to the new memory
mapping.
Th
On 7/14/23 09:51, Eric Auger wrote:
Hi Stefan,
On 7/14/23 13:51, Stefan Berger wrote:
On 7/14/23 02:07, Joelle van Dyne wrote:
On Thu, Jul 13, 2023 at 10:20 AM Stefan Berger
wrote:
The ppi command line option for the TIS device on sysbus never worked
and caused an immediate segfault. Re
On 14/7/23 12:49, Thomas Huth wrote:
It's possible to compile QEMU without the USB devices (e.g. when using
"--without-default-devices" as option for the "configure" script).
To be still able to run the loongson3-virt machine in default mode with
such a QEMU binary, we have to check here for the
Queued, thanks.
Paolo
On 7/14/23 03:09, Joelle van Dyne wrote:
This SysBus variant of the CRB interface supports dynamically locating
the MMIO interface so that Virt machines can use it. This interface
is currently the only one supported by QEMU that works on Windows 11
ARM64. We largely follow the TPM TIS SysBus d
On 7/14/23 03:09, Joelle van Dyne wrote:
When we moved to a single mapping and modified TPM CRB's VMState, it
broke restoring of VMs that were saved on an older version. This
change allows those VMs to gracefully migrate to the new memory
mapping.
Thanks. This has to be in 4/11 though.
On Fri, 7 Jul 2023 13:43:36 -0400
"Annie.li" wrote:
> Hi Igor,
>
> Revisiting this thread and have more questions, please clarify, thank you!
>
> On 9/20/2021 3:53 AM, Igor Mammedov wrote:
> > On Fri, 6 Aug 2021 16:18:09 -0400
> > "Annie.li" wrote:
> >
> >> Hello Igor,
> >>
> >> This is an o
Hi Stefan,
On 7/14/23 13:51, Stefan Berger wrote:
>
>
> On 7/14/23 02:07, Joelle van Dyne wrote:
>> On Thu, Jul 13, 2023 at 10:20 AM Stefan Berger
>> wrote:
>>>
>>> The ppi command line option for the TIS device on sysbus never worked
>>> and caused an immediate segfault. Remove support for it sin
14.07.2023 15:49, Peter Maydell wrote:
On Fri, 14 Jul 2023 at 12:40, Michael Tokarev wrote:
Signed-off-by: Michael Tokarev
---
host/include/aarch64/host/cpuinfo.h | 2 +-
This...
hw/misc/allwinner-r40-dramc.c| 2 +-
hw/misc/exynos4210_rng.c
14.07.2023 16:05, Fabiano Rosas wrote:
--- a/migration/migration-stats.c
+++ b/migration/migration-stats.c
@@ -50,3 +50,3 @@ void migration_rate_set(uint64_t limit)
/*
- * 'limit' is per second. But we check it each BUFER_DELAY miliseconds.
+ * 'limit' is per second. But we check
14.07.2023 14:38, Michael Tokarev:
--- a/block/block-copy.c
+++ b/block/block-copy.c
@@ -69,3 +69,3 @@ typedef struct BlockCopyCallState {
/*
- * Fields that report information about return values and erros.
+ * Fields that report information about return values and errors.
Michael Tokarev writes:
> Signed-off-by: Michael Tokarev
> ---
> migration/migration-stats.c | 2 +-
> migration/migration.h | 4 ++--
> migration/multifd-zlib.c| 2 +-
> migration/multifd-zstd.c| 2 +-
> migration/multifd.c | 2 +-
> migration/savevm.c | 2 +-
>
Steve Sistare writes:
> Define a state object to capture events seen by migration tests, to allow
> more events to be captured in a subsequent patch, and simplify event
> checking in wait_for_migration_pass. No functional change.
>
> Signed-off-by: Steve Sistare
I'm working on top of this patc
On Fri, 14 Jul 2023 at 12:50, Igor Mammedov wrote:
>
> On Thu, 13 Jul 2023 12:59:55 +0100
> Peter Maydell wrote:
>
> > On Thu, 13 Jul 2023 at 12:52, Marcin Juszkiewicz
> > wrote:
> > >
> > > W dniu 13.07.2023 o 13:44, Peter Maydell pisze:
> > >
> > > > I see this isn't a change in this patch, bu
14.07.2023 15:44, Peter Maydell wrote:
..
Michael Tokarev (29):
tree-wide spelling fixes in comments and some messages: block
tree-wide spelling fixes in comments and some messages: bsd-user
This would be easier to deal with if it followed our
standard convention of putting the subsystem
On Fri, 14 Jul 2023 at 12:44, Michael Tokarev wrote:
>
> Signed-off-by: Michael Tokarev
> ---
> hw/arm/aspeed.c| 2 +-
> hw/arm/mps2-tz.c | 2 +-
> hw/intc/arm_gic.c | 4 ++--
> hw/intc/arm_gicv3_redist.c | 2 +-
> hw/intc/armv7m_nvic.c | 2
On Fri, 14 Jul 2023 at 12:40, Michael Tokarev wrote:
>
> Signed-off-by: Michael Tokarev
> ---
> host/include/aarch64/host/cpuinfo.h | 2 +-
This...
> hw/misc/allwinner-r40-dramc.c| 2 +-
> hw/misc/exynos4210_rng.c | 2 +-
...these...
Steve Sistare writes:
> Create a subroutine for preserving the runstate after migration,
> to be used in a subsequent patch. No functional change.
>
> Signed-off-by: Steve Sistare
Reviewed-by: Fabiano Rosas
Current migration_completion function is a bit long. Refactor the long
implementation into different subfunctions:
- migration_completion_precopy: completion code related to precopy
- migration_completion_postcopy: completion code related to postcopy
- close_return_path_on_source: rp thread related
Steve Sistare writes:
> A guest that is migrated in the suspended state automaticaly wakes and
> continues execution. This is wrong; the guest should end migration in
> the same state it started. The root causes is that the outgoing migration
> code automatically wakes the guest, then saves the
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