[PATCH RESEND v5 17/19] target/loongarch: Add avail_LAM to check atomic instructions

From: Song Gao Signed-off-by: Song Gao Reviewed-by: Richard Henderson Message-ID: <20230822032724.1353391-14-gaos...@loongson.cn> --- target/loongarch/translate.h | 1 + .../loongarch/insn_trans/trans_atomic.c.inc | 72 +-- 2 files changed, 37 insertions(+),

[PATCH RESEND v5 12/19] target/loongarch: Add avail_64 to check la64-only instructions

From: Song Gao The la32 instructions listed in Table 2 at https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#overview-of-basic-integer-instructions Co-authored-by: Jiajie Chen Signed-off-by: Song Gao Reviewed-by: Richard Henderson Message-ID: <20230822032724.1353391-9-g

[PATCH RESEND v5 16/19] target/loongarch: Add avail_LSPW to check LSPW instructions

From: Song Gao Signed-off-by: Song Gao Reviewed-by: Richard Henderson Message-ID: <20230822032724.1353391-13-gaos...@loongson.cn> --- target/loongarch/translate.h | 1 + target/loongarch/insn_trans/trans_privileged.c.inc | 8 2 files changed, 9 insertions(+) dif

[PATCH RESEND v5 14/19] hw/loongarch: Remove restriction of la464 cores in the virt machine

From: Song Gao Allow virt machine to be used with la132 instead of la464. Co-authored-by: Jiajie Chen Signed-off-by: Song Gao Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20230822032724.1353391-11-gaos...@loongson.cn> --- hw/loongarch/virt.c | 5 - 1 f

[PATCH RESEND v5 15/19] target/loongarch: Add avail_FP/FP_SP/FP_DP to check fpu instructions

From: Song Gao Signed-off-by: Song Gao Acked-by: Richard Henderson Message-ID: <20230822032724.1353391-12-gaos...@loongson.cn> --- target/loongarch/translate.h | 4 + target/loongarch/translate.c | 1 + .../loongarch/insn_trans/trans_farith.c.inc | 96

[PATCH RESEND v5 11/19] target/loongarch: Add a check parameter to the TRANS macro

From: Song Gao The default check parmeter is ALL. Suggested-by: Richard Henderson Signed-off-by: Song Gao Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-ID: <20230822032724.1353391-8-gaos...@loongson.cn> --- target/loongarch/translate.h |6 +-

[PATCH RESEND v5 13/19] target/loongarch: Add LoongArch32 cpu la132

From: Jiajie Chen Add LoongArch32 cpu la132. Due to lack of public documentation of la132, it is currently a synthetic LoongArch32 cpu model. Details need to be added in the future. Signed-off-by: Jiajie Chen Signed-off-by: Song Gao Acked-by: Richard Henderson Reviewed-by: Philippe Mathieu-D

[PATCH RESEND v5 10/19] target/loongarch: Sign extend results in VA32 mode

From: Jiajie Chen In VA32 mode, BL, JIRL and PC* instructions should sign-extend the low 32 bit result to 64 bits. Signed-off-by: Jiajie Chen Reviewed-by: Richard Henderson Signed-off-by: Song Gao Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20230822032724.1353391-7-gaos...@loongson.cn>

Re: [PATCH v5 00/19] Based-on: https://patchew.org/QEMU/20230821125959.28666-1-phi...@linaro.org/

On 22/8/23 09:09, Philippe Mathieu-Daudé wrote: (all series reviewed, for Song Gao to pick whichever v4/v5 is preferred) Incorrect subject, and SMTP failure, so disregard (will resend).

[PATCH RESEND v5 07/19] target/loongarch: Extract make_address_pc() helper

From: Jiajie Chen Signed-off-by: Jiajie Chen Reviewed-by: Richard Henderson Signed-off-by: Song Gao Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20230822032724.1353391-7-gaos...@loongson.cn> [PMD: Extract helper from bigger patch] Signed-off-by: Philippe Mathieu-Daudé --- target/loongar

[PATCH RESEND v5 09/19] target/loongarch: Truncate high 32 bits of address in VA32 mode

From: Jiajie Chen When running in VA32 mode(!LA64 or VA32L[1-3] matching PLV), virtual address is truncated to 32 bits before address mapping. Signed-off-by: Jiajie Chen Co-authored-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: Song Gao Reviewed-by: Philippe Mathieu-Dau

[PATCH RESEND v5 08/19] target/loongarch: Extract set_pc() helper

From: Jiajie Chen Signed-off-by: Jiajie Chen Co-authored-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: Song Gao Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20230822032724.1353391-6-gaos...@loongson.cn> [PMD: Extract helper from bigger patch] Signed-off-by: Philippe

[PATCH RESEND v5 03/19] target/loongarch: Support LoongArch32 VPPN

From: Jiajie Chen VPPN of TLBEHI/TLBREHI is limited to 19 bits in LA32. Signed-off-by: Jiajie Chen Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-ID: <20230822032724.1353391-4-gaos...@loongson.cn> --- target/loongarch/cpu-csr.h| 6 -- target/loongarch/tlb_helper.c |

[PATCH RESEND v5 05/19] target/loongarch: Extract make_address_x() helper

From: Jiajie Chen Signed-off-by: Jiajie Chen Co-authored-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: Song Gao Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20230822032724.1353391-6-gaos...@loongson.cn> [PMD: Extract helper from bigger patch] Signed-off-by: Philippe

[PATCH RESEND v5 06/19] target/loongarch: Extract make_address_i() helper

From: Jiajie Chen Signed-off-by: Jiajie Chen Co-authored-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: Song Gao Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20230822032724.1353391-6-gaos...@loongson.cn> [PMD: Extract helper from bigger patch] Signed-off-by: Philippe

[PATCH RESEND v5 04/19] target/loongarch: Add LA64 & VA32 to DisasContext

From: Jiajie Chen Add LA64 and VA32(32-bit Virtual Address) to DisasContext to allow the translator to reject doubleword instructions in LA32 mode for example. Signed-off-by: Jiajie Chen Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-ID: <20230822032724.1353391-5-gaos...@loong

[PATCH RESEND v5 01/19] target/loongarch: Support LoongArch32 TLB entry

From: Jiajie Chen The TLB entry of LA32 lacks NR, NX and RPLV and they are hardwired to zero in LoongArch32. Signed-off-by: Jiajie Chen Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-ID: <20230822032724.1353391-2-gaos...@loongson.cn> --- target/loongarch/cpu-csr.h| 9 +++

[PATCH RESEND v5 02/19] target/loongarch: Support LoongArch32 DMW

From: Jiajie Chen LA32 uses a different encoding for CSR.DMW and a new direct mapping mechanism. Signed-off-by: Jiajie Chen Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-ID: <20230822032724.1353391-3-gaos...@loongson.cn> --- target/loongarch/cpu-csr.h| 7 +++ target

[PATCH RESEND v5 00/19] Add some checks before translating instructions

Based-on: https://patchew.org/QEMU/20230821125959.28666-1-phi...@linaro.org/ (all series reviewed, for Song Gao to pick whichever v4/v5 is preferred) Hi, This series adds some checks before translating instructions This includes: CPUCFG[1].IOCSR CPUCFG[2].FP CPUCFG[2].FP_SP CPUCFG[2].FP_DP CP

[PATCH v5 08/19] target/loongarch: Extract set_pc() helper

From: Jiajie Chen Signed-off-by: Jiajie Chen Co-authored-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: Song Gao Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20230822032724.1353391-6-gaos...@loongson.cn> [PMD: Extract helper from bigger patch] Signed-off-by: Philippe

[PATCH v5 06/19] target/loongarch: Extract make_address_i() helper

From: Jiajie Chen Signed-off-by: Jiajie Chen Co-authored-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: Song Gao Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20230822032724.1353391-6-gaos...@loongson.cn> [PMD: Extract helper from bigger patch] Signed-off-by: Philippe

[PATCH v5 09/19] target/loongarch: Truncate high 32 bits of address in VA32 mode

From: Jiajie Chen When running in VA32 mode(!LA64 or VA32L[1-3] matching PLV), virtual address is truncated to 32 bits before address mapping. Signed-off-by: Jiajie Chen Co-authored-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: Song Gao Reviewed-by: Philippe Mathieu-Dau

[PATCH v5 02/19] target/loongarch: Support LoongArch32 DMW

From: Jiajie Chen LA32 uses a different encoding for CSR.DMW and a new direct mapping mechanism. Signed-off-by: Jiajie Chen Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-ID: <20230822032724.1353391-3-gaos...@loongson.cn> --- target/loongarch/cpu-csr.h| 7 +++ target

[PATCH v5 07/19] target/loongarch: Extract make_address_pc() helper

From: Jiajie Chen Signed-off-by: Jiajie Chen Reviewed-by: Richard Henderson Signed-off-by: Song Gao Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20230822032724.1353391-7-gaos...@loongson.cn> [PMD: Extract helper from bigger patch] Signed-off-by: Philippe Mathieu-Daudé --- target/loongar

[PATCH v5 04/19] target/loongarch: Add LA64 & VA32 to DisasContext

From: Jiajie Chen Add LA64 and VA32(32-bit Virtual Address) to DisasContext to allow the translator to reject doubleword instructions in LA32 mode for example. Signed-off-by: Jiajie Chen Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-ID: <20230822032724.1353391-5-gaos...@loong

[PATCH v5 05/19] target/loongarch: Extract make_address_x() helper

From: Jiajie Chen Signed-off-by: Jiajie Chen Co-authored-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: Song Gao Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20230822032724.1353391-6-gaos...@loongson.cn> [PMD: Extract helper from bigger patch] Signed-off-by: Philippe

[PATCH v5 01/19] target/loongarch: Support LoongArch32 TLB entry

From: Jiajie Chen The TLB entry of LA32 lacks NR, NX and RPLV and they are hardwired to zero in LoongArch32. Signed-off-by: Jiajie Chen Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-ID: <20230822032724.1353391-2-gaos...@loongson.cn> --- target/loongarch/cpu-csr.h| 9 +++

[PATCH v5 03/19] target/loongarch: Support LoongArch32 VPPN

From: Jiajie Chen VPPN of TLBEHI/TLBREHI is limited to 19 bits in LA32. Signed-off-by: Jiajie Chen Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-ID: <20230822032724.1353391-4-gaos...@loongson.cn> --- target/loongarch/cpu-csr.h| 6 -- target/loongarch/tlb_helper.c |

[PATCH v5 00/19] Based-on: https://patchew.org/QEMU/20230821125959.28666-1-phi...@linaro.org/

(all series reviewed, for Song Gao to pick whichever v4/v5 is preferred) Hi, This series adds some checks before translating instructions This includes: CPUCFG[1].IOCSR CPUCFG[2].FP CPUCFG[2].FP_SP CPUCFG[2].FP_DP CPUCFG[2].LSPW CPUCFG[2].LAM CPUCFG[2].LSX V5: - Split 2 patches, extracting he

Re: [PATCH v4 06/15] target/loongarch: Sign extend results in VA32 mode

On 22/8/23 05:27, Song Gao wrote: From: Jiajie Chen In VA32 mode, BL, JIRL and PC* instructions should sign-extend the low 32 bit result to 64 bits. Signed-off-by: Jiajie Chen Reviewed-by: Richard Henderson Signed-off-by: Song Gao --- target/loongarch/translate.c | 8 +++

Re: [PATCH v4 05/15] target/loongarch: Truncate high 32 bits of address in VA32 mode

On 22/8/23 05:27, Song Gao wrote: From: Jiajie Chen When running in VA32 mode(!LA64 or VA32L[1-3] matching PLV), virtual address is truncated to 32 bits before address mapping. Signed-off-by: Jiajie Chen Co-authored-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: Song Ga

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