25.08.2023 14:58, Dmitry Frolov wrote:
It is true, that there is no problem during runtime
from the first sight, because the memory is lost just
before qemu exits. Nevertheless, this change is necessary,
because AddressSanitizer is not able to recognize this
situation and produces crash-report
* Add TZASC as unimplemented device.
- Allow bare metal application to access this (unimplemented) device
* Add CSU as unimplemented device.
- Allow bare metal application to access this (unimplemented) device
* Add 4 missing PWM devices
Signed-off-by: Jean-Christophe Dubois
Reviewed-by:
* Add TZASC as unimplemented device.
- Allow bare metal application to access this (unimplemented) device
* Add CSU as unimplemented device.
- Allow bare metal application to access this (unimplemented) device
* Add various memory segments
- OCRAM
- OCRAM EPDC
- OCRAM PXP
- OCRAM S
-
The SRC device is normally used to start the secondary CPU.
When running Linux directly, QEMU is emulating a PSCI interface that UBOOT
is installing at boot time and therefore the fact that the SRC device is
unimplemented is hidden as Qemu respond directly to PSCI requets without
using the SRC
* Add Addr and size definition for most i.MX6UL devices in i.MX6UL header file.
* Use those newly defined named constants whenever possible.
* Standardize the way we init a familly of unimplemented devices
- SAI
- PWM
- CAN
* Add/rework few comments
Signed-off-by: Jean-Christophe Dubois
* Add Addr and size definition for all i.MX7 devices in i.MX7 header file.
* Use those newly defined named constants whenever possible.
* Standardize the way we init a familly of unimplemented devices
- SAI
- PWM
- CAN
* Add/rework few comments
Signed-off-by: Jean-Christophe Dubois
---
i.MX7 IOMUX GPR device is not equivalent to i.MX6UL IOMUXC GPR device.
In particular, register 22 is not present on i.MX6UL and this is actualy
The only register that is really emulated in the i.MX7 IOMUX GPR device.
Note: The i.MX6UL code is actually also implementing the IOMUX GPR device
as an
This patch adds a few unimplemented TZ devices (TZASC and CSU) to
i.MX6UL and i.MX7 processors to avoid bare metal application to
experiment "bus error" when acccessing these devices.
It also adds some internal memory segments (OCRAM) to the i.MX7 to
allow bare metal application to use them.
This make the cpu works the similar way like the -device option.
For device option,
"""
./qemu-system-riscv64 -device e1000,help
e1000 options:
acpi-index=- (default: 0)
addr= - Slot and optional function number, example: 06.0 or
06 (default: -1)
autonegotiation= - on/off
Some times we want to know what is the really mean of one cpu option.
For example, in RISC-V, we usually specify a cpu in this way:
-cpu rv64,v=on
If we don't look into the source code, we can't get the ISA extensions
of this -cpu command line.
In this patch set, we add one list_cpu_props API
This API used for output current configuration for one specified CPU.
Currently only RISC-V frontend implements this API.
Signed-off-by: LIU Zhiwei
---
cpu.c | 8
include/exec/cpu-common.h | 1 +
target/riscv/cpu.c| 10 ++
target/riscv/cpu.h
cpu_type_by_name is used to get the cpu type name from the command
line -cpu.
Currently it is only used by parse_cpu_option. In the next patch, it
will be used by other cpu query functions.
Signed-off-by: LIU Zhiwei
---
cpu.c | 31 +++
1 file changed, 19
It is true, that there is no problem during runtime
from the first sight, because the memory is lost just
before qemu exits. Nevertheless, this change is necessary,
because AddressSanitizer is not able to recognize this
situation and produces crash-report (which is
false-positive in fact). Lots of
On Thu, 24 Aug 2023 13:49:00 -0700
Fan Ni wrote:
> On Mon, Aug 07, 2023 at 09:53:42AM +0100, Jonathan Cameron wrote:
> > On Tue, 25 Jul 2023 18:39:56 +
> > Fan Ni wrote:
> >
> > > From: Fan Ni
> > >
> > > Not all dpa range in the dc regions is valid to access until an extent
> > >
On 24/8/23 20:31, Richard Henderson wrote:
On 8/24/23 08:31, Alex Bennée wrote:
It's some sort of timing issue, which sometimes goes away when re-run.
I was re-running tests *a lot* in order to get them to go green while
running the 8.1 release.
There is a definite regression point for the
On 24/8/23 18:23, Michael Tokarev wrote:
24.08.2023 18:31, Alex Bennée wrote:
..
which bisects to:
commit f7eaf9d702efdd02481d5f1c25f7d8e0ffb64c6e (HEAD,
refs/bisect/bad)
Author: Richard Henderson
Date: Tue Aug 1 10:46:03 2023 -0700
accel/tcg: Do not issue misaligned i/o
Introduce a new test for native calls to ensure their functionality.
The process involves cross-compiling the test cases, building them
as dynamically linked binaries, and running these binaries which
necessitates the addition of the appropriate interpreter prefix.
Signed-off-by: Yeqi Fu
---
This commit introduces support for native library calls on the
arm target. When encountering special instructions reserved
for native calls, this commit extracts the function name and
generates the corresponding native call.
Signed-off-by: Yeqi Fu
---
configs/targets/aarch64-linux-user.mak | 1
This commit implements tcg opcodes and helpers for native library
calls. A table is used to store the parameter types and return value
types for each native library function. In terms of types, only three
types are of real concern: the two base sizes int and intptr_t, and
if the value is a
This commit introduces support for native library calls on the
i386 target. When encountering special instructions reserved
for native calls, this commit extracts the function name and
generates the corresponding native call.
Signed-off-by: Yeqi Fu
---
configs/targets/i386-linux-user.mak | 1
Signed-off-by: Yeqi Fu
---
docs/user/index.rst| 1 +
docs/user/native_calls.rst | 90 ++
2 files changed, 91 insertions(+)
create mode 100644 docs/user/native_calls.rst
diff --git a/docs/user/index.rst b/docs/user/index.rst
index
This commit introduces support for native library calls on the
mips target. When encountering special instructions reserved
for native calls, this commit extracts the function name and
generates the corresponding native call.
Signed-off-by: Yeqi Fu
---
configs/targets/mips-linux-user.mak | 1
Since both TCG tests and libnative libraries require cross-building,
the config files for cross-building, config_target_mak, are now saved
in the cross-build directory for sharing. This allows TCG tests and
libnative libraries to use these config files through symbolic links
when cross-building
Signed-off-by: Yeqi Fu
---
include/qemu/envlist.h| 13 ++
tests/unit/meson.build| 1 +
tests/unit/test-envlist.c | 94 +++
util/envlist.c| 67 +++-
4 files changed, 165 insertions(+), 10 deletions(-)
create
This commit implements a shared library, where native functions are
rewritten as special instructions. At runtime, user programs load
the shared library, and special instructions are executed when
native functions are called.
Signed-off-by: Yeqi Fu
---
Makefile| 2 +
This commit implements the -native-bypass support in linux-user. The
native_calls_enabled() function can be true only when the
'-native-bypass' option is given.
Signed-off-by: Yeqi Fu
---
include/native/native.h | 9 +
linux-user/main.c | 38 ++
Executing a program under QEMU's user mode subjects the entire
program, including all library calls, to translation. It's important
to understand that many of these library functions are optimized
specifically for the guest architecture. Therefore, their
translation might not yield the most
Am 24.08.23 um 15:38 schrieb Fiona Ebner:
> Fails without the previous commit "hw/ide: reset: cancel async DMA
> operation before reseting state".
>
> I haven't ever written such a test before, but I wanted something to
> expose the problem more easily. It hardcodes the behavior that the
>
On 25.08.23 11:59, David Hildenbrand wrote:
On 25.08.23 11:56, Markus Armbruster wrote:
David Hildenbrand writes:
On 25.08.23 11:10, Markus Armbruster wrote:
David Hildenbrand writes:
On 25.08.23 08:57, ThinerLogoer wrote:
Hello,
At 2023-08-23 23:34:11, "David Hildenbrand" wrote:
For
On 23/08/2023 12:58, David Woodhouse wrote:
From: David Woodhouse
Upstream Xen now ignores this flag¹, since the only guest kernel ever to
use it was buggy.
¹ https://xenbits.xen.org/gitweb/?p=xen.git;a=commitdiff;h=19c6cbd909
Signed-off-by: David Woodhouse
---
We do take an argument to
On 25.08.23 11:56, Markus Armbruster wrote:
David Hildenbrand writes:
On 25.08.23 11:10, Markus Armbruster wrote:
David Hildenbrand writes:
On 25.08.23 08:57, ThinerLogoer wrote:
Hello,
At 2023-08-23 23:34:11, "David Hildenbrand" wrote:
For migration purposes, users might want to
David Hildenbrand writes:
> On 25.08.23 11:10, Markus Armbruster wrote:
>> David Hildenbrand writes:
>>
>>> On 25.08.23 08:57, ThinerLogoer wrote:
Hello,
At 2023-08-23 23:34:11, "David Hildenbrand" wrote:
> For migration purposes, users might want to reuse the default RAM
On Fri Aug 18, 2023 at 1:36 PM AEST, Akihiko Odaki wrote:
> GDB has XML support since 6.7 which was released in 2007.
> It's time to remove support for old GDB versions without XML support.
These 3 patches might be better to go ahead in a preparation series
with "remove support for gdb 6.7" in
It is true, that there is no problem during runtime
from the first sight, because the memmory is lost just
before qemu exits. Nevertheless, this change is necessary,
because AddressSanitizer is not able to recognize this
situation and produces crash-report (which is
false-positive in fact). Lots
25.08.2023 11:34, Philippe Mathieu-Daudé wrote:
...
__FILE__ is used by assert() family, some DEBUG_PRINTF(), but mainly
by "qapi/error.h", so all error_setg*() calls.
This has been bugging me since quite some time, since if you build
the same QEMU in different paths (usually on different
On 25.08.23 11:10, Markus Armbruster wrote:
David Hildenbrand writes:
On 25.08.23 08:57, ThinerLogoer wrote:
Hello,
At 2023-08-23 23:34:11, "David Hildenbrand" wrote:
For migration purposes, users might want to reuse the default RAM
backend id, but specify a different memory backend.
For
David Hildenbrand writes:
> On 25.08.23 08:57, ThinerLogoer wrote:
>> Hello,
>>
>> At 2023-08-23 23:34:11, "David Hildenbrand" wrote:
>>> For migration purposes, users might want to reuse the default RAM
>>> backend id, but specify a different memory backend.
>>>
>>> For example, to reuse
On 2023/08/23 15:09, Manivannan Sadhasivam wrote:
On Fri, Aug 18, 2023 at 10:46:02PM +0900, Shunsuke Mie wrote:
Hi all,
We are proposing to add a new test syste to Linux for PCIe Endpoint. That
can be run on QEMU without real hardware. At present, partially we have
confirmed that
On Wed, 2023-08-23 at 22:00 +0300, Michael Tokarev wrote:
> 23.08.2023 21:38, David Woodhouse wrote:
> > On Wed, 2023-08-23 at 09:53 +0300, Michael Tokarev wrote:
> > >
> > > include/hw/xen/interface/arch-x86/xen-x86_64.h | 2 +-
> > > include/hw/xen/interface/arch-x86/xen.h | 2 +-
> >
On 25/08/2023 10.34, Philippe Mathieu-Daudé wrote:
...
__FILE__ is used by assert() family, some DEBUG_PRINTF(), but mainly
by "qapi/error.h", so all error_setg*() calls.
This has been bugging me since quite some time, since if you build
the same QEMU in different paths (usually on different
On 25/8/23 09:46, Michael Tokarev wrote:
24.08.2023 19:38, Alex Bennée wrote:
From: Daniel P. Berrangé
The `ccache` tool can be very effective at reducing compilation times
when re-running pipelines with only minor changes each time. For example
a fresh 'build-system-fedora' job will
On Tue Aug 22, 2023 at 2:44 PM AEST, Pavel Dovgalyuk wrote:
> On 11.08.2023 04:47, Nicholas Piggin wrote:
> > RR CPU switching is driven by timers and events so it is deterministic
> > like everything else. Record a CPU switch event and use that to drive
> > the CPU switch on replay.
> >
> >
On Mon Aug 21, 2023 at 12:59 PM AEST, Richard Henderson wrote:
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1779
> Signed-off-by: Richard Henderson
Should go to qemu-stable I would say? Thanks for fixing.
Reviewed-by: Nicholas Piggin
> ---
> target/ppc/cpu.c | 1 +
> 1 file
On Fri, Aug 25, 2023 at 10:46:29AM +0300, Michael Tokarev wrote:
> 24.08.2023 19:38, Alex Bennée wrote:
> > From: Daniel P. Berrangé
> >
> > The `ccache` tool can be very effective at reducing compilation times
> > when re-running pipelines with only minor changes each time. For example
> > a
On 18/8/23 13:00, Philippe Mathieu-Daudé wrote:
ping?
On 10/7/23 11:49, Philippe Mathieu-Daudé wrote:
Similarly to commit e414ed2c47 ("virtio-iommu: Use
target-agnostic qemu_target_page_mask"), Replace the
target-specific TARGET_PAGE_SIZE and TARGET_PAGE_MASK
definitions by a call to the
On Thu, Aug 24, 2023 at 02:26:42PM -0400, Stefan Hajnoczi wrote:
> I've done most of the audit necessary to understand which AioContext is
> used where. The call graph is large because qio_channel_yield() is used
> internally by qio_channel_readv_full_all_eof(),
> qio_channel_writev_full_all(),
Ping?
On 19/7/23 16:17, Philippe Mathieu-Daudé wrote:
Do not silently ignore the user request of using MSIX.
Remove the TODO. Coverity reported this as CID 1508725.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/usb/hcd-xhci-pci.c | 21 -
1 file changed, 16 insertions(+),
On Tue Aug 22, 2023 at 10:40 PM AEST, Philippe Mathieu-Daudé wrote:
> This series factor the "byteswap each halfword within a
> 32/64-bit value" code duplication as generic helpers.
>
> Modulo the documentation added, there is a good negative
> diff-stat, so I believe this is a win from a
On [2023 Aug 24] Thu 16:32:23, Peter Maydell wrote:
> Use a g_autofree heap allocation instead of a variable length
> array in dump_receive_iov().
>
> The codebase has very few VLAs, and if we can get rid of them all we
> can make the compiler error on new additions. This is a defensive
>
On [2023 Aug 24] Thu 16:32:24, Peter Maydell wrote:
> Use a heap allocation instead of a variable length array in
> tap_receive_iov().
>
> The codebase has very few VLAs, and if we can get rid of them all we
> can make the compiler error on new additions. This is a defensive
> measure against
On [2023 Aug 24] Thu 16:32:22, Peter Maydell wrote:
> Replace an on-stack variable length array in of_dpa_ig() with
> a g_autofree heap allocation.
>
> The codebase has very few VLAs, and if we can get rid of them all we
> can make the compiler error on new additions. This is a defensive
>
24.08.2023 19:38, Alex Bennée wrote:
From: Daniel P. Berrangé
The `ccache` tool can be very effective at reducing compilation times
when re-running pipelines with only minor changes each time. For example
a fresh 'build-system-fedora' job will typically take 20 minutes on the
gitlab.com shared
On 24/8/23 18:38, Alex Bennée wrote:
From: Daniel P. Berrangé
The `ccache` tool can be very effective at reducing compilation times
when re-running pipelines with only minor changes each time. For example
a fresh 'build-system-fedora' job will typically take 20 minutes on the
gitlab.com shared
On Tue Aug 22, 2023 at 10:53 PM AEST, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/ppc/translate.c | 10 +-
> target/ppc/translate/vsx-impl.c.inc | 19 ++-
> 2 files changed, 3 insertions(+), 26 deletions(-)
>
> diff
On 25.08.23 08:57, ThinerLogoer wrote:
Hello,
At 2023-08-23 23:34:11, "David Hildenbrand" wrote:
For migration purposes, users might want to reuse the default RAM
backend id, but specify a different memory backend.
For example, to reuse "pc.ram" on q35, one has to set
-machine
On 24/8/23 18:39, Alex Bennée wrote:
Use proper kdoc style comments for this API function.
Signed-off-by: Alex Bennée
---
include/exec/gdbstub.h | 10 ++
gdbstub/gdbstub.c | 6 --
2 files changed, 10 insertions(+), 6 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 24/8/23 18:39, Alex Bennée wrote:
Try and make the self reported global hack a little less hackish by
providing a query function instead. As gdb_has_xml was always set if
we negotiated XML we can now use the presence of ->target_xml as the
test instead.
Signed-off-by: Alex Bennée
---
On 24/8/23 18:39, Alex Bennée wrote:
This was always NULL so drop it.
Signed-off-by: Alex Bennée
Acked-by: Ilya Leoshkevich
---
gdbstub/gdbstub.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 25/8/23 04:32, alloc.yo...@outlook.com wrote:
From: alloc
Convert free to g_free to match g_new and g_malloc functions.
Signed-off-by: alloc
Fixes: cc2b33eab0 ("softmmu/dirtylimit: Implement vCPU dirtyrate
calculation periodically")
Fixes: baa609832e ("softmmu/dirtylimit: Implement
Ping?
On 5/7/23 13:44, Philippe Mathieu-Daudé wrote:
Hi Alex,
On 17/11/22 18:25, Alex Bennée wrote:
The bullet points are quite long and contain process tips. Move those
bits of the bullet to the relevant sections and link to them. Use a
table for nicer formatting of the checklist.
On 24/8/23 23:04, del...@kernel.org wrote:
From: Helge Deller
Convert hppa_get_physical_address() to use the privilege helper macro.
Signed-off-by: Helge Deller
---
target/hppa/mem_helper.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
Reviewed-by: Philippe
On 24/8/23 23:04, del...@kernel.org wrote:
From: Helge Deller
Avoid using hardcoded values when calling the tlb_flush*() functions.
Instead define the correct mask (HPPA_MMU_FLUSH_MASK) and use it.
Skip flushing the MMU for physical addresses.
Alternatively:
Instead, define and use
Gurchetan Singh writes:
> On Wed, Aug 23, 2023 at 4:07 AM Alyssa Ross wrote:
>
>> Gurchetan Singh writes:
>>
>> > - Official "release commits" issued for rutabaga_gfx_ffi,
>> > gfxstream, aemu-base. For example, see crrev.com/c/4778941
>> >
>> > - The release commits can make packaging
On 24/8/23 23:04, del...@kernel.org wrote:
From: Helge Deller
The hppa CPU has 4 priviledge levels (0-3).
Mention the missing PL1 and PL2 levels, although the Linux kernel
uses only 0 (KERNEL) and 3 (USER). Not sure about HP-UX.
Signed-off-by: Helge Deller
---
target/hppa/cpu.h | 3 +++
1
On 24/8/23 23:04, del...@kernel.org wrote:
From: Helge Deller
Add two macros which convert priviledge level to/from MMU index:
- PRIV_TO_MMU_IDX(priv)
returns the MMU index for the given priviledge level
- MMU_IDX_TO_PRIV(mmu_idx)
returns the corresponding priviledge level for this
On 8/24/23 18:45, Peter Maydell wrote:
We use a variable-length array in inet_get_free_port_multiple().
This is only test code called at the start of a test, so switch to a
heap allocation instead.
The codebase has very few VLAs, and if we can get rid of them all we
can make the compiler error
From: Helge Deller
Make the conversion between privilege level and QEMU MMU index
consitent, and afterwards switch to MMU indices 11-15.
v2:
- no functional changes
- just typo fixes in commit messages
- branch rebased on v8.1.0 release
Signed-off-by: Helge Deller
Helge Deller (5):
From: Helge Deller
The MMU indices 9-15 will use shorter assembler instructions
when run on a x86-64 host. So, switch over to those to get
smaller code and maybe minimally faster emulation.
Signed-off-by: Helge Deller
---
target/hppa/cpu.h | 16
1 file changed, 8
From: Helge Deller
Convert hppa_get_physical_address() to use the privilege helper macro.
Signed-off-by: Helge Deller
---
target/hppa/mem_helper.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c
index
From: Helge Deller
Avoid using hardcoded values when calling the tlb_flush*() functions.
Instead define the correct mask (HPPA_MMU_FLUSH_MASK) and use it.
Skip flushing the MMU for physical addresses.
Signed-off-by: Helge Deller
---
target/hppa/cpu.h| 5 +
target/hppa/helper.c
From: Helge Deller
The hppa CPU has 4 privilege levels (0-3).
Mention the missing PL1 and PL2 levels, although the Linux kernel
uses only 0 (KERNEL) and 3 (USER). Not sure about HP-UX.
Signed-off-by: Helge Deller
---
target/hppa/cpu.h | 3 +++
1 file changed, 3 insertions(+)
diff --git
Hello,
At 2023-08-23 23:34:11, "David Hildenbrand" wrote:
>For migration purposes, users might want to reuse the default RAM
>backend id, but specify a different memory backend.
>
>For example, to reuse "pc.ram" on q35, one has to set
>-machine q35,memory-backend=pc.ram
>Only then, can a
From: Helge Deller
Add two macros which convert privilege level to/from MMU index:
- PRIV_TO_MMU_IDX(priv)
returns the MMU index for the given privilege level
- MMU_IDX_TO_PRIV(mmu_idx)
returns the corresponding privilege level for this MMU index
The introduction of those macros make
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