Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 8
tcg/loongarch64/tcg-target.h | 2 +-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index
Lower the following ops:
- ssadd_vec
- usadd_vec
- sssub_vec
- ussub_vec
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 32
tcg/loongarch64/tcg-target.h | 2 +-
2 files changed, 33 insertions(+), 1
Lower the following ops:
- add_vec
- sub_vec
Signed-off-by: Jiajie Chen
---
tcg/loongarch64/tcg-target-con-set.h | 1 +
tcg/loongarch64/tcg-target-con-str.h | 1 +
tcg/loongarch64/tcg-target.c.inc | 60
3 files changed, 62 insertions(+)
diff --git
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 8
tcg/loongarch64/tcg-target.h | 2 +-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index
Lower the following ops:
- rotrv_vec
- rotlv_vec
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 14 ++
tcg/loongarch64/tcg-target.h | 2 +-
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git
LSX support on host cpu is detected via hwcap.
Lower the following ops to LSX:
- dup_vec
- dupi_vec
- dupm_vec
- ld_vec
- st_vec
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
---
tcg/loongarch64/tcg-target-con-set.h | 2 +
tcg/loongarch64/tcg-target-con-str.h | 1 +
Lower the following ops:
- and_vec
- andc_vec
- or_vec
- orc_vec
- xor_vec
- nor_vec
- not_vec
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
---
tcg/loongarch64/tcg-target-con-set.h | 2 ++
tcg/loongarch64/tcg-target.c.inc | 44
Lower the following ops:
- shli_vec
- shrv_vec
- sarv_vec
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 21 +
tcg/loongarch64/tcg-target.h | 2 +-
2 files changed, 22 insertions(+), 1 deletion(-)
diff --git
If LSX is available, use LSX instructions to implement 128-bit load &
store.
Signed-off-by: Jiajie Chen
---
tcg/loongarch64/tcg-target-con-set.h | 2 ++
tcg/loongarch64/tcg-target.c.inc | 42
tcg/loongarch64/tcg-target.h | 2 +-
3 files changed, 45
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
---
tcg/loongarch64/tcg-target-con-set.h | 1 +
tcg/loongarch64/tcg-target.c.inc | 11 ++-
tcg/loongarch64/tcg-target.h | 2 +-
3 files changed, 12 insertions(+), 2 deletions(-)
diff --git
Lower the following ops:
- shlv_vec
- shrv_vec
- sarv_vec
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 24
tcg/loongarch64/tcg-target.h | 2 +-
2 files changed, 25 insertions(+), 1 deletion(-)
diff --git
Signed-off-by: Jiajie Chen
---
tcg/loongarch64/tcg-target-con-set.h | 1 +
tcg/loongarch64/tcg-target-con-str.h | 1 +
tcg/loongarch64/tcg-target.c.inc | 65
3 files changed, 67 insertions(+)
diff --git a/tcg/loongarch64/tcg-target-con-set.h
Lower the following ops:
- smin_vec
- smax_vec
- umin_vec
- umax_vec
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 32
tcg/loongarch64/tcg-target.h | 2 +-
2 files changed, 33 insertions(+), 1 deletion(-)
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 21 +
tcg/loongarch64/tcg-target.h | 2 +-
2 files changed, 22 insertions(+), 1 deletion(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
This patch series allows qemu to utilize LSX instructions on LoongArch
machines to execute TCG vector ops.
Passed tcg tests with x86_64 and aarch64 cross compilers.
Changes since v2:
- Add vece argument to tcg_target_const_match() for const args of vector ops
- Use custom constraint for
Pass vece to tcg_target_const_match() to allow correct interpretation of
const args of vector ops.
Signed-off-by: Jiajie Chen
---
tcg/aarch64/tcg-target.c.inc | 2 +-
tcg/arm/tcg-target.c.inc | 2 +-
tcg/i386/tcg-target.c.inc| 2 +-
tcg/loongarch64/tcg-target.c.inc | 2 +-
On 2023/9/2 01:48, Richard Henderson wrote:
On 9/1/23 10:28, Jiajie Chen wrote:
On 2023/9/2 01:24, Richard Henderson wrote:
On 9/1/23 02:30, Jiajie Chen wrote:
Signed-off-by: Jiajie Chen
---
tcg/loongarch64/tcg-target-con-set.h | 1 +
tcg/loongarch64/tcg-target.c.inc | 60
Queued, thanks.
Paolo
On 8/31/23 09:47, Andrew Jones wrote:
On Fri, Aug 25, 2023 at 10:08:53AM -0300, Daniel Henrique Barboza wrote:
This follows the same idea of 'tcg_support' property added in the
previous patch. Note that we're now implementing the 'cpu_realizefn' for
the KVMAccel class since this verification
Move the various open_cpuinfo functions into new files.
Move the m68k open_hardware function as well.
All other guest architectures get a boilerplate empty file.
Tested-by: Helge Deller
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
linux-user/aarch64/target_proc.h
From: Ilya Leoshkevich
Core dumps produced by gdb's gcore when connected to qemu's gdbstub
lack stack. The reason is that gdb includes only anonymous memory in
core dumps, which is distinguished by a non-0 Anonymous: value.
Consider the mappings with PAGE_ANON fully anonymous, and the mappings
Use dev_t instead of a string, and ino_t instead of uint64_t.
The latter is likely to be identical on modern systems but is
more type-correct for usage.
Tested-by: Helge Deller
Reviewed-by: Ilya Leoshkevich
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
From: Helge Deller
Add emulation for /proc/cpuinfo for arm architecture.
The output below mimics output as seen on debian porterboxes.
aarch64 output example:
processor : 0
model name : ARMv8 Processor rev 0 (v8l)
BogoMIPS: 100.00
Features: swp half thumb fast_mult
The following changes since commit 17780edd81d27fcfdb7a802efc870a99788bd2fc:
Merge tag 'quick-fix-pull-request' of https://gitlab.com/bsdimp/qemu into
staging (2023-08-31 10:06:29 -0400)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-lu-20230901
The start_mmap value is write-only.
Remove the field and the defines that populated it.
Logically, this has been replaced by task_unmapped_base.
Tested-by: Helge Deller
Reviewed-by: Ilya Leoshkevich
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
linux-user/qemu.h
If the shm region is not mapped at shmaddr, EINVAL.
Do not unmap the region until the syscall succeeds.
Use mmap_reserve_or_unmap to preserve reserved_va semantics.
Tested-by: Helge Deller
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
linux-user/mmap.c | 17
Tested-by: Helge Deller
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Ilya Leoshkevich
Signed-off-by: Richard Henderson
---
linux-user/syscall.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 0b91f996b7..0641d8f433 100644
---
Rename from do_* to target_*. Fix some minor checkpatch errors.
Tested-by: Helge Deller
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Warner Losh
Signed-off-by: Richard Henderson
---
linux-user/user-mmap.h | 4 ++
linux-user/mmap.c | 138
PIE executables are usually linked at offset 0 and are
relocated somewhere during load. The hiaddr needs to
be adjusted to keep the brk next to the executable.
Cc: qemu-sta...@nongnu.org
Fixes: 1f356e8c013 ("linux-user: Adjust initial brk when interpreter is close
to executable")
Tested-by:
Remove the fixed size shm_regions[] array.
Remove references when other mappings completely remove
or replace a region.
Tested-by: Helge Deller
Reviewed-by: Helge Deller
Signed-off-by: Richard Henderson
---
linux-user/mmap.c | 81 +++
1 file
Move the CF_PARALLEL setting outside of the mmap lock.
Tested-by: Helge Deller
Reviewed-by: Helge Deller
Signed-off-by: Richard Henderson
---
linux-user/mmap.c | 98 ++-
1 file changed, 46 insertions(+), 52 deletions(-)
diff --git
Replace the by-hand method of region identification with
the official user-exec interface. Cross-check the region
provided to the callback with the interval tree from
read_self_maps().
Tested-by: Helge Deller
Reviewed-by: Ilya Leoshkevich
Signed-off-by: Richard Henderson
---
From: Helge Deller
Add emulation for /proc/cpuinfo for the alpha architecture.
alpha output example:
(alpha-chroot)root@p100:/# cat /proc/cpuinfo
cpu : Alpha
cpu model : ev67
cpu variation : 0
cpu revision: 0
cpu serial number :
STGP writes to tag memory, it does not check it.
This happened to work because we wrote tag memory first
so that the check always succeeded.
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-a64.c | 41 +-
1 file changed, 15 insertions(+), 26
On 9/1/23 03:12, Michael Tokarev wrote:
+/*
+ * Prepare to change user ID. optarg can be one of 3 forms:
+ * - a username, in which case user ID will be changed to its uid,
+ * with primary and supplementary groups set up too;
+ * - a nemeric uid, in which case only the uid will be set;
On 8/31/23 08:00, Andrew Jones wrote:
On Fri, Aug 25, 2023 at 10:08:40AM -0300, Daniel Henrique Barboza wrote:
All generic CPUs call riscv_cpu_add_user_properties(). The 'max' CPU
calls riscv_init_max_cpu_extensions(). Both can be moved to a common
instance_post_init() callback, implemented
Add smoke tests to ensure that we'll not break the 'max' CPU type when
adding new frozen/ratified RISC-V extensions.
Signed-off-by: Daniel Henrique Barboza
---
tests/avocado/tuxrun_baselines.py | 32 +++
1 file changed, 32 insertions(+)
diff --git
The 'any' CPU type was introduced in commit dc5bd18fa5725 ("RISC-V CPU
Core Definition"), being around since the beginning. It's not an easy
CPU to use: it's undocumented and its name doesn't tell users much about
what the CPU is supposed to bring. 'git log' doesn't help us either in
knowing what
We'll add a new CPU type that will enable a considerable amount of
extensions. To make it easier for us we'll do a few cleanups in our
existing riscv_cpu_extensions[] array.
Start by splitting all CPU non-boolean options from it. Create a new
riscv_cpu_options[] array for them. Add all these
Let's change the other instances in realize() where we're enabling an
extension based on a certain criteria (e.g. it's a dependency of another
extension).
We're leaving icsr and ifencei being enabled during RVG for later -
we'll want to error out in that case. Every other extension enablement
If we want to make better decisions when auto-enabling extensions during
realize() we need a way to tell if an user set an extension manually.
The RISC-V KVM driver has its own solution via a KVMCPUConfig struct
that has an 'user_set' flag that is set during the Property set()
callback. The set()
Before adding support to detect if an extension was user set we need to
handle how we're enabling extensions in riscv_init_max_cpu_extensions().
object_property_set_bool() calls the set() callback for the property,
and we're going to use this callback to set the 'multi_ext_user_opts'
hash.
This
Add a new cpu_cfg_ext_is_user_set() helper to check if an extension was
set by the user in the command line. Use it inside
cpu_cfg_ext_auto_update() to verify if the user set a certain extension
and, if that's the case, do not change its value.
This will make us honor user choice instead of
Inside riscv_cpu_validate_v() we're always throwing a log message if the
user didn't set a vector version via 'vext_spec'.
We're going to include one case with the 'max' CPU where env->vext_ver
will be set in the cpu_init(). But that alone will not stop the "vector
version is not specified"
Add DEFINE_PROP_END_OF_LIST() and eliminate the ARRAY_SIZE() usage when
iterating in the riscv_cpu_options[] array, making it similar to what
we already do when working with riscv_cpu_extensions[].
We also have a more sophisticated motivation behind this change. In the
future we might need to
The 'max' CPU type is used by tooling to determine what's the most
capable CPU a current QEMU version implements. Other archs such as ARM
implements this type. Let's add it to RISC-V.
What we consider "most capable CPU" in this context are related to
ratified, non-vendor extensions. This means
During realize() time we're activating a lot of extensions based on some
criteria, e.g.:
if (cpu->cfg.ext_zk) {
cpu->cfg.ext_zkn = true;
cpu->cfg.ext_zkr = true;
cpu->cfg.ext_zkt = true;
}
This practice resulted in at least one case where we ended up enabling
We'll have future usage for a function where, given an offset of the
struct RISCVCPUConfig, the flag is updated to a certain val.
Change all existing callers to use edata->ext_enable_offset instead of
'edata'.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Reviewed-by:
Create a new riscv_cpu_experimental_exts[] to store the non-ratified
extensions properties. Once they are ratified we'll move them back to
riscv_cpu_extensions[].
riscv_cpu_add_user_properties() and riscv_cpu_add_kvm_properties() are
changed to keep adding non-ratified properties to users.
The code inside riscv_cpu_add_user_properties() became quite repetitive
after recent changes. Add a helper to hide the repetition away.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
---
target/riscv/cpu.c | 29 +
1 file changed, 13 insertions(+),
Enabling RVG will enable a set of extensions that we're not checking if
the user was okay enabling or not. And in this case we want to error
out, instead of ignoring, otherwise we will be inconsistent enabling RVG
without all its extensions.
After this patch, disabling ifencei or icsr while
Our goal is to make riscv_cpu_extensions[] hold only ratified,
non-vendor extensions.
Create a new riscv_cpu_vendor_exts[] array for them, changing
riscv_cpu_add_user_properties() and riscv_cpu_add_kvm_properties()
accordingly.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair
Use a helper in riscv_cpu_add_kvm_properties() to eliminate some of its
code repetition.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
---
target/riscv/cpu.c | 24 +---
1 file changed, 13 insertions(+), 11 deletions(-)
diff --git a/target/riscv/cpu.c
The RISC-V KVM driver uses a CPUCFG() macro that calculates the offset
of a certain field in the struct RISCVCPUConfig. We're going to use this
macro in target/riscv/cpu.c as well in the next patches. Make it public.
Rename it to CPU_CFG_OFFSET() for more clarity while we're at it.
Hi,
This new version contains suggestions made by Andrew Jones in v8.
Most notable change is the removal of the opensbi.py test in patch 11,
which was replaced by a TuxBoot test. It's more suitable to test the
integrity of all the extensions enabled by the 'max' CPU.
The series is available in
After the introduction of riscv_cpu_options[] all properties in
riscv_cpu_extensions[] are booleans. This check is now obsolete.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Reviewed-by: Andrew Jones
---
target/riscv/cpu.c | 14 --
1 file changed, 4
Future patches will split the existing Property arrays even further, and
the existing code in riscv_cpu_add_user_properties() will start to scale
bad with it because it's dealing with KVM constraints mixed in with TCG
constraints. We're going to pay a high price to share a couple of common
lines
On Fri, Sep 01, 2023 at 09:35:47AM +0200, Andrew Jones wrote:
> On Thu, Aug 31, 2023 at 07:00:52PM +, Colton Lewis wrote:
> > Due to recent KVM changes, QEMU is setting a ptimer offset resulting
> > in unintended trap and emulate access and a consequent performance
> > hit. Filter out the
The commit 5d8813593f ("block/qapi: Let bdrv_query_image_info()
recurse") removed the loop where we set the 'bs0' variable, so now it
is just the same as 'bs'.
Signed-off-by: Fabiano Rosas
Reviewed-by: Philippe Mathieu-Daudé
---
block/qapi.c | 5 ++---
1 file changed, 2 insertions(+), 3
Hi,
I'm resending a couple of already reviewed patches that were part of a
larger series[1].
Thanks
1- https://lore.kernel.org/r/20230609201910.12100-1-faro...@suse.de
Fabiano Rosas (2):
block: Remove bdrv_query_block_node_info
block: Remove unnecessary variable in bdrv_block_device_info
The last call site of this function has been removed by commit
c04d0ab026 ("qemu-img: Let info print block graph").
Reviewed-by: Claudio Fontana
Signed-off-by: Fabiano Rosas
---
block/qapi.c | 27 ---
include/block/qapi.h | 3 ---
2 files changed, 30
On 01/09/2023 18:59, Joao Martins wrote:
> On 03/08/2023 16:53, Peter Xu wrote:
>> @@ -2694,7 +2694,17 @@ static void migration_update_counters(MigrationState
>> *s,
>> transferred = current_bytes - s->iteration_initial_bytes;
>> time_spent = current_time - s->iteration_start_time;
Peter Xu writes:
> On Thu, Aug 31, 2023 at 03:39:16PM -0300, Fabiano Rosas wrote:
>> @@ -1166,16 +1183,9 @@ static void migrate_fd_cleanup(MigrationState *s)
>> qemu_mutex_lock_iothread();
>>
>> multifd_save_cleanup();
>> -qemu_mutex_lock(>qemu_file_lock);
>> -
On 9/1/23 02:31, Jiajie Chen wrote:
Signed-off-by: Jiajie Chen
---
tcg/loongarch64/tcg-target.c.inc | 21 +
tcg/loongarch64/tcg-target.h | 2 +-
2 files changed, 22 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson
r~
On 9/1/23 02:31, Jiajie Chen wrote:
Lower the following ops:
- rotrv_vec
- rotlv_vec
Signed-off-by: Jiajie Chen
---
tcg/loongarch64/tcg-target.c.inc | 14 ++
tcg/loongarch64/tcg-target.h | 2 +-
2 files changed, 15 insertions(+), 1 deletion(-)
Reviewed-by: Richard
On 9/1/23 02:31, Jiajie Chen wrote:
Lower the following ops:
- shli_vec
- shrv_vec
- sarv_vec
Signed-off-by: Jiajie Chen
---
tcg/loongarch64/tcg-target.c.inc | 21 +
tcg/loongarch64/tcg-target.h | 2 +-
2 files changed, 22 insertions(+), 1 deletion(-)
On 03/08/2023 16:53, Peter Xu wrote:
> @@ -2694,7 +2694,17 @@ static void migration_update_counters(MigrationState
> *s,
> transferred = current_bytes - s->iteration_initial_bytes;
> time_spent = current_time - s->iteration_start_time;
> bandwidth = (double)transferred /
On 9/1/23 02:30, Jiajie Chen wrote:
Lower the following ops:
- and_vec
- andc_vec
- or_vec
- orc_vec
- xor_vec
- nor_vec
- not_vec
Signed-off-by: Jiajie Chen
---
tcg/loongarch64/tcg-target-con-set.h | 2 ++
tcg/loongarch64/tcg-target.c.inc | 44
On 9/1/23 02:30, Jiajie Chen wrote:
Lower the following ops:
- add_vec
- sub_vec
Signed-off-by: Jiajie Chen
---
tcg/loongarch64/tcg-target-con-set.h | 1 +
tcg/loongarch64/tcg-target.c.inc | 58
2 files changed, 59 insertions(+)
diff --git
On 9/1/23 10:28, Jiajie Chen wrote:
On 2023/9/2 01:24, Richard Henderson wrote:
On 9/1/23 02:30, Jiajie Chen wrote:
Signed-off-by: Jiajie Chen
---
tcg/loongarch64/tcg-target-con-set.h | 1 +
tcg/loongarch64/tcg-target.c.inc | 60
2 files changed, 61
On 2023/9/2 01:24, Richard Henderson wrote:
On 9/1/23 02:30, Jiajie Chen wrote:
Signed-off-by: Jiajie Chen
---
tcg/loongarch64/tcg-target-con-set.h | 1 +
tcg/loongarch64/tcg-target.c.inc | 60
2 files changed, 61 insertions(+)
Reviewed-by: Richard
On Wed, Aug 30, 2023 at 01:38:28PM +0400, marcandre.lur...@redhat.com wrote:
> From: Marc-André Lureau
>
> Add stubs for the fallback paths.
>
> Signed-off-by: Marc-André Lureau
> ---
> ui/console-vc-stubs.c | 59 +++
> ui/meson.build| 2 +-
>
On Wed, Aug 30, 2023 at 05:55:26PM +0200, Philippe Mathieu-Daudé wrote:
> On 30/8/23 17:48, Philippe Mathieu-Daudé wrote:
> > On 30/8/23 11:38, marcandre.lur...@redhat.com wrote:
> > > From: Marc-André Lureau
> > >
> > > Set CONFIG_PIXMAN accordinly.
> > >
> > > Signed-off-by: Marc-André Lureau
On 9/1/23 02:30, Jiajie Chen wrote:
Signed-off-by: Jiajie Chen
---
tcg/loongarch64/tcg-target-con-set.h | 1 +
tcg/loongarch64/tcg-target.c.inc | 60
2 files changed, 61 insertions(+)
Reviewed-by: Richard Henderson
diff --git
On Wed, Aug 30, 2023 at 01:38:24PM +0400, marcandre.lur...@redhat.com wrote:
> From: Marc-André Lureau
>
> Mostly for readability reasons.
>
> Signed-off-by: Marc-André Lureau
> ---
> include/ui/console.h | 84 +---
> include/ui/surface.h | 91
On Wed, Aug 30, 2023 at 01:38:23PM +0400, marcandre.lur...@redhat.com wrote:
> From: Marc-André Lureau
>
> Move common declarations to console-priv.h, and add a new unit
> console-vc.c which will handle VC/chardev rendering, when pixman is
> available.
>
> (if necessary, the move could be done
On Wed, Aug 30, 2023 at 01:38:22PM +0400, marcandre.lur...@redhat.com wrote:
> From: Marc-André Lureau
>
> Those changes will help to split console.c unit in the following commit.
>
> Signed-off-by: Marc-André Lureau
> ---
> ui/console.c | 52
On 8/31/23 08:30, Andrew Jones wrote:
On Fri, Aug 25, 2023 at 10:08:45AM -0300, Daniel Henrique Barboza wrote:
Move the files to a 'kvm' dir to promote more code separation between
accelerators and making our lives easier supporting build options such
as --disable-tcg.
Rename kvm.c to
On Wed, Aug 30, 2023 at 01:38:21PM +0400, marcandre.lur...@redhat.com wrote:
> From: Marc-André Lureau
>
> It's already part of PIXMAN image.
>
> Signed-off-by: Marc-André Lureau
> ---
> include/ui/console.h | 15 +++
> ui/console-gl.c | 2 +-
> ui/console.c | 4
On Wed, Aug 30, 2023 at 05:41:51PM +0200, Philippe Mathieu-Daudé wrote:
> On 30/8/23 11:38, marcandre.lur...@redhat.com wrote:
> > From: Marc-André Lureau
> >
> > They are QemuTextConsole functions, let's make it clear.
> >
> > Signed-off-by: Marc-André Lureau
> > ---
> >
On Wed, Aug 30, 2023 at 01:38:18PM +0400, marcandre.lur...@redhat.com wrote:
> From: Marc-André Lureau
>
> Those functions are specifc to text/vc console, make that explicit from
> the argument type.
>
> Signed-off-by: Marc-André Lureau
> ---
> include/ui/console.h | 6 +++---
> ui/console.c
On Wed, Aug 30, 2023 at 01:38:17PM +0400, marcandre.lur...@redhat.com wrote:
> From: Marc-André Lureau
>
> In commit 6f974c843c ("gtk: overwrite the console.c char driver"), I
> shared the VC console parse handler with GTK. And later on in commit
> d8aec9d9 ("display: add -display spice-app
On 9/1/23 02:30, Jiajie Chen wrote:
Add opcodes and encoder functions for LSX.
Generated from
https://github.com/jiegec/loongarch-opcodes/tree/qemu-lsx.
Signed-off-by: Jiajie Chen
---
tcg/loongarch64/tcg-insn-defs.c.inc | 6251 ++-
1 file changed, 6134 insertions(+),
On 9/1/23 02:30, Jiajie Chen wrote:
LSX support on host cpu is detected via hwcap.
Lower the following ops to LSX:
- dup_vec
- dupi_vec
- dupm_vec
- ld_vec
- st_vec
Signed-off-by: Jiajie Chen
---
tcg/loongarch64/tcg-target-con-set.h | 2 +
tcg/loongarch64/tcg-target-con-str.h | 1 +
On 9/1/23 04:51, Cédric Le Goater wrote:
Adding more reviewers since this patch is modifying a common service.
Thanks,
C.
On 8/8/23 06:19, Nicholas Piggin wrote:
This will be used for converting time intervals in different base units
to host units, for the purpose of scheduling timers to
Am 24.08.2023 um 01:59 hat Stefan Hajnoczi geschrieben:
> Use qemu_get_current_aio_context() in mixed wrappers and coroutine
> wrappers so that code runs in the caller's AioContext instead of moving
> to the BlockDriverState's AioContext. This change is necessary for the
> multi-queue block layer
On Wed, Aug 30, 2023 at 01:38:16PM +0400, marcandre.lur...@redhat.com wrote:
> From: Marc-André Lureau
>
> This will allow to split the VC code in a separate unit more easily.
>
> Signed-off-by: Marc-André Lureau
> ---
> include/ui/console.h | 1 +
> ui/console.c | 13 +
>
On Wed, Aug 30, 2023 at 01:38:15PM +0400, marcandre.lur...@redhat.com wrote:
> From: Marc-André Lureau
>
> Signed-off-by: Marc-André Lureau
> ---
> ui/console.c | 10 --
> 1 file changed, 4 insertions(+), 6 deletions(-)
Reviewed-by: Daniel P. Berrangé
With regards,
Daniel
--
|:
On Wed, Aug 30, 2023 at 01:38:14PM +0400, marcandre.lur...@redhat.com wrote:
> From: Marc-André Lureau
>
> This function is called on invalidate, on each cursor blink.
>
> Avoid the extra copy when the console size didn't change.
>
> Signed-off-by: Marc-André Lureau
> ---
> ui/console.c | 12
On Wed, Aug 30, 2023 at 01:38:13PM +0400, marcandre.lur...@redhat.com wrote:
> From: Marc-André Lureau
>
> Signed-off-by: Marc-André Lureau
> ---
> ui/console.c | 10 ++
> 1 file changed, 2 insertions(+), 8 deletions(-)
Reviewed-by: Daniel P. Berrangé
With regards,
Daniel
--
|:
From: Pierre Morel
When the host supports the CPU topology facility, the PTF
instruction with function code 2 is interpreted by the SIE,
provided that the userland hypervisor activates the interpretation
by using the KVM_CAP_S390_CPU_TOPOLOGY KVM extension.
The PTF instructions with function
On Thu, Aug 31, 2023 at 03:39:16PM -0300, Fabiano Rosas wrote:
> @@ -1166,16 +1183,9 @@ static void migrate_fd_cleanup(MigrationState *s)
> qemu_mutex_lock_iothread();
>
> multifd_save_cleanup();
> -qemu_mutex_lock(>qemu_file_lock);
> -tmp = s->to_dst_file;
> -
Changes since v21 (range-diff below):
* fix ordering of entries in topology list
* don't leak topology list on error condition in insert_stsi_15_1_x
* make entitlement, dedication optional in query-cpu-info-fast
* rename query-cpu-polarization to query-s390x-cpu-polarization
* documentation
From: Pierre Morel
On interception of STSI(15.1.x) the System Information Block
(SYSIB) is built from the list of pre-ordered topology entries.
Signed-off-by: Pierre Morel
Co-developed-by: Nina Schoetterl-Glausch
Signed-off-by: Nina Schoetterl-Glausch
---
MAINTAINERS |
From: Pierre Morel
Introduction of the s390x cpu topology core functions and
basic tests.
We test the correlation between the command line and
the QMP results in query-cpus-fast for various CPU topology.
Signed-off-by: Pierre Morel
---
MAINTAINERS| 1 +
From: Pierre Morel
Test changes in the entitlement from both a guest and a host point of
view, depending on the polarization.
Signed-off-by: Pierre Morel
Co-developed-by: Nina Schoetterl-Glausch
Signed-off-by: Nina Schoetterl-Glausch
---
tests/avocado/s390_topology.py | 55
From: Pierre Morel
Add some basic examples for the definition of cpu topology
in s390x.
Signed-off-by: Pierre Morel
Co-developed-by: Nina Schoetterl-Glausch
Signed-off-by: Nina Schoetterl-Glausch
---
MAINTAINERS| 2 +
docs/devel/index-internals.rst | 1 +
From: Pierre Morel
When the guest asks to change the polarization this change
is forwarded to the upper layer using QAPI.
The upper layer is supposed to take according decisions concerning
CPU provisioning.
Signed-off-by: Pierre Morel
Reviewed-by: Thomas Huth
Reviewed-by: Nina
From: Pierre Morel
A dedicated CPU in vertical polarization can only have
a high entitlement.
Let's check this from both host and guest point of view.
Signed-off-by: Pierre Morel
Co-developed-by: Nina Schoetterl-Glausch
Signed-off-by: Nina Schoetterl-Glausch
---
From: Pierre Morel
S390x provides two more topology attributes, entitlement and dedication.
Let's add these CPU attributes to the QAPI command query-cpu-fast.
Signed-off-by: Pierre Morel
Reviewed-by: Nina Schoetterl-Glausch
Co-developed-by: Nina Schoetterl-Glausch
Signed-off-by: Nina
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