Re: [PATCH v3 06/13] docs/devel: simplify the minimal checklist

Philippe Mathieu-Daudé writes: > Ping? > > On 5/7/23 13:44, Philippe Mathieu-Daudé wrote: >> Hi Alex, >> On 17/11/22 18:25, Alex Bennée wrote: >>> The bullet points are quite long and contain process tips. Move those >>> bits of the bullet to the relevant sections and link to them. Use a >>>

Re: [PATCH RFC 1/7] include/sysemu/os-posix.h: move *daemonize* declaration together

15.08.2023 19:22, Eric Blake wrote: On Sat, Aug 12, 2023 at 03:47:55PM +0300, Michael Tokarev wrote: Signed-off-by: Michael Tokarev --- include/sysemu/os-posix.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) Reviewed-by: Eric Blake Eric, thank you very much for the review!

Re: [RFC PATCH v3 20/20] hw/virtio: allow vhost-user-device to be driven by backend

On Mon, Jul 10, 2023 at 6:44 PM Alex Bennée wrote: > Instead of requiring all the information up front allow the > vhost_dev_init to complete and then see what information we have from > the backend. > > This does change the order around somewhat. > > Signed-off-by: Alex Bennée > --- >

Re: [PATCH 00/16] tests: Add CPU topology related smbios test cases

25.08.2023 06:36, Zhao Liu wrote: From: Zhao Liu Hi all, This patchset is the follow up tests of previous topology fixes in smbios [1]. In this patchset, add these test cases: 1. Add the case to test 2 newly added topology helpers (patch 1): * machine_topo_get_cores_per_socket() *

[PULL 05/26] tests/avocado/machine_aspeed.py: Update SDK images

Switch to the latest v8.06 release which introduces interesting changes for the AST2600 I2C and I3C models. Also take the AST2600 A2 images instead of the default since QEMU tries to model The AST2600 A3 SoC. Signed-off-by: Cédric Le Goater Reviewed-by: Joel Stanley Signed-off-by: Cédric Le

[PULL 17/26] hw/sd: Introduce sd_cmd_handler type

From: Philippe Mathieu-Daudé Add 2 command handler arrays in SDProto, for CMD and ACMD. Have sd_normal_command() / sd_app_command() use these arrays: if an command handler is registered, call it, otherwise fall back to current code base. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bin

[PULL 21/26] hw/sd: Add sd_cmd_SEND_OP_CMD() handler

From: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé [ clg: Update cmd_abbrev ] Message-Id: <20210624142209.1193073-9-f4...@amsat.org> Signed-off-by: Cédric Le Goater --- hw/sd/sd.c | 18 +- hw/sd/sdmmc-internal.c | 2 +- 2 files changed, 10

[PULL 24/26] hw/sd: Add sd_cmd_SEND_TUNING_BLOCK() handler

From: Joel Stanley Signed-off-by: Joel Stanley Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Cédric Le Goater --- hw/sd/sd.c | 28 +--- 1 file changed, 17 insertions(+), 11 deletions(-) diff --git a/hw/sd/sd.c b/hw/sd/sd.c index b46072424108..00a59450b726 100644

[PULL 06/26] hw/ssi: Add a "cs" property to SSIPeripheral

Boards will use this new property to identify the device CS line and wire the SPI controllers accordingly. Cc: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Joel Stanley Signed-off-by: Cédric Le Goater --- include/hw/ssi/ssi.h | 3 +++ hw/ssi/ssi.c | 7 +++ 2

[PULL 26/26] hw/sd: Introduce a "sd-card" SPI variant model

and replace the SDState::spi attribute with a test checking the SDProto array of commands. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Cédric Le Goater --- include/hw/sd/sd.h | 3 +++ hw/arm/stellaris.c | 3 +-- hw/riscv/sifive_u.c | 3 +-- hw/sd/sd.c | 54

[PULL 19/26] hw/sd: Add sd_cmd_unimplemented() handler

From: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé [ clg: Fix redundant assignment of .cmd ] Message-Id: <20210624142209.1193073-7-f4...@amsat.org> Signed-off-by: Cédric Le Goater --- hw/sd/sd.c | 21 - 1 file changed, 12 insertions(+), 9 deletions(-) diff

[PULL 08/26] aspeed/smc: Wire CS lines at reset

Currently, a set of default flash devices is created at machine init and drives defined on the QEMU command line are associated to the FMC and SPI controllers in sequence : -drive file,format=raw,if=mtd -drive file,format=raw,if=mtd The CS lines are wired in the same creation loop. This

[PULL 02/26] hw/i2c/aspeed: Fix Tx count and Rx size error in buffer pool mode

From: Hang Yu Fixed inconsistency between the regisiter bit field definition header file and the ast2600 datasheet. The reg name is I2CD1C:Pool Buffer Control Register in old register mode and I2CC0C: Master/Slave Pool Buffer Control Register in new register mode. They share bit field

[PULL 16/26] hw/sd: Move proto_name to SDProto structure

From: Philippe Mathieu-Daudé Introduce a new structure to hold the bus protocol specific fields: SDProto. The first field is the protocol name. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bin Meng Message-Id: <20210624142209.1193073-4-f4...@amsat.org> Signed-off-by: Cédric Le Goater

[PULL 15/26] hw/sd: When card is in wrong state, log which spec version is used

From: Philippe Mathieu-Daudé Add the sd_version_str() helper. Signed-off-by: Philippe Mathieu-Daudé Signed-off-by: Cédric Le Goater --- hw/sd/sd.c | 18 -- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/hw/sd/sd.c b/hw/sd/sd.c index 4412559c05be..20e62aff70b6

[PULL 25/26] hw/sd: Add sd_cmd_SET_BLOCK_COUNT() handler

From: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Signed-off-by: Cédric Le Goater --- hw/sd/sd.c | 30 -- 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/hw/sd/sd.c b/hw/sd/sd.c index 00a59450b726..d1c0b132c227 100644 ---

[PULL 18/26] hw/sd: Add sd_cmd_illegal() handler

From: Philippe Mathieu-Daudé Log illegal commands as GUEST_ERROR. Note: we are logging back the SDIO commands (CMD5, CMD52-54). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bin Meng Message-Id: <20210624142209.1193073-6-f4...@amsat.org> Signed-off-by: Cédric Le Goater --- hw/sd/sd.c

[PULL 14/26] hw/sd: When card is in wrong state, log which state it is

From: Philippe Mathieu-Daudé We report the card is in an inconsistent state, but don't precise in which state it is. Add this information, as it is useful when debugging problems. Since we will reuse this code, extract as sd_invalid_state_for_cmd() helper. Signed-off-by: Philippe Mathieu-Daudé

[PULL 20/26] hw/sd: Add sd_cmd_GO_IDLE_STATE() handler

From: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bin Meng Message-Id: <20210624142209.1193073-8-f4...@amsat.org> Signed-off-by: Cédric Le Goater --- hw/sd/sd.c | 24 1 file changed, 12 insertions(+), 12 deletions(-) diff --git

[PULL 11/26] m25p80: Introduce an helper to retrieve the BlockBackend of a device

It will help in getting rid of some drive_get(IF_MTD) calls by retrieving the BlockBackend directly from the m25p80 device. Cc: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Joel Stanley Signed-off-by: Cédric Le Goater --- include/hw/block/flash.h | 4

[PULL 10/26] aspeed: Create flash devices only when defaults are enabled

When the -nodefaults option is set, flash devices should be created with : -blockdev node-name=fmc0,driver=file,filename=./flash.img \ -device mx66u51235f,cs=0x0,bus=ssi.0,drive=fmc0 \ To be noted that in this case, the ROM will not be installed and the initial boot sequence (U-Boot

[PULL 07/26] hw/ssi: Introduce a ssi_get_cs() helper

Simple routine to retrieve a DeviceState object on a SPI bus using its CS index. It will be useful for the board to wire the CS lines. Cc: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Joel Stanley Signed-off-by: Cédric Le Goater --- include/hw/ssi/ssi.h | 2 ++

[PULL 03/26] hw/i2c/aspeed: Fix TXBUF transmission start position error

From: Hang Yu According to the ast2600 datasheet and the linux aspeed i2c driver, the TXBUF transmission start position should be TXBUF[0] instead of TXBUF[1],so the arg pool_start is useless,and the address is not included in TXBUF.So even if Tx Count equals zero,there is at least 1 byte data

[PULL 09/26] hw/ssi: Check for duplicate CS indexes

This to avoid indexes conflicts on the same SSI bus. Adapt machines using multiple devices on the same bus to avoid breakage. Cc: "Edgar E. Iglesias" Cc: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Joel Stanley Signed-off-by: Cédric Le Goater --- hw/arm/stellaris.c

[PULL 23/26] hw/sd: Add sd_cmd_SEND_RELATIVE_ADDR() handler

From: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bin Meng Message-Id: <20210624142209.1193073-11-f4...@amsat.org> Signed-off-by: Cédric Le Goater --- hw/sd/sd.c | 28 +++- 1 file changed, 15 insertions(+), 13 deletions(-) diff --git

[PULL 04/26] hw/i2c/aspeed: Add support for buffer organization

From: Hang Yu Added support for the buffer organization option in pool buffer control register.when set to 1,The buffer is split into two parts: Lower 16 bytes for Tx and higher 16 bytes for Rx. Signed-off-by: Hang Yu Reviewed-by: Cédric Le Goater [ clg: checkpatch fixes ] Signed-off-by:

[PULL 12/26] aspeed: Get the BlockBackend of FMC0 from the flash device

and get rid of an unnecessary drive_get(IF_MTD) call. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Joel Stanley Signed-off-by: Cédric Le Goater --- hw/arm/aspeed.c | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index

[PULL 13/26] hw/sd/sdcard: Return ILLEGAL for CMD19/CMD23 prior SD spec v3.01

From: Philippe Mathieu-Daudé CMD19 (SEND_TUNING_BLOCK) and CMD23 (SET_BLOCK_COUNT) were added in the Physical Layer Simplified Specification v3.01. When earlier spec version is requested, we should return ILLEGAL. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bin Meng Message-Id:

[PULL 22/26] hw/sd: Add sd_cmd_ALL_SEND_CID() handler

From: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bin Meng Message-Id: <20210624142209.1193073-10-f4...@amsat.org> Signed-off-by: Cédric Le Goater --- hw/sd/sd.c | 23 --- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git

[PULL 01/26] aspeed: Introduce helper for 32-bit hosts limitation

On 32-bit hosts, RAM has a 2047 MB limit. Use a macro to define the default ram size of machines (AST2600 SoC) that can have 2 GB. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Signed-off-by: Cédric Le Goater --- hw/arm/aspeed.c | 21 + 1 file changed, 9

[PULL 00/26] aspeed queue

The following changes since commit 17780edd81d27fcfdb7a802efc870a99788bd2fc: Merge tag 'quick-fix-pull-request' of https://gitlab.com/bsdimp/qemu into staging (2023-08-31 10:06:29 -0400) are available in the Git repository at: https://github.com/legoater/qemu/ tags/pull-aspeed-20230901

[PATCH v2 05/14] tcg/loongarch64: Lower vector bitwise operations

Lower the following ops: - and_vec - andc_vec - or_vec - orc_vec - xor_vec - nor_vec - not_vec Signed-off-by: Jiajie Chen --- tcg/loongarch64/tcg-target-con-set.h | 2 ++ tcg/loongarch64/tcg-target.c.inc | 44 tcg/loongarch64/tcg-target.h | 8 ++--- 3

[PATCH v2 02/14] tcg/loongarch64: Lower basic tcg vec ops to LSX

LSX support on host cpu is detected via hwcap. Lower the following ops to LSX: - dup_vec - dupi_vec - dupm_vec - ld_vec - st_vec Signed-off-by: Jiajie Chen --- tcg/loongarch64/tcg-target-con-set.h | 2 + tcg/loongarch64/tcg-target-con-str.h | 1 + tcg/loongarch64/tcg-target.c.inc |

[PATCH v2 08/14] tcg/loongarch64: Lower vector min max ops

Lower the following ops: - smin_vec - smax_vec - umin_vec - umax_vec Signed-off-by: Jiajie Chen Reviewed-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 32 tcg/loongarch64/tcg-target.h | 2 +- 2 files changed, 33 insertions(+), 1 deletion(-)

[PATCH v2 04/14] tcg/loongarch64: Lower add/sub_vec to vadd/vsub

Lower the following ops: - add_vec - sub_vec Signed-off-by: Jiajie Chen --- tcg/loongarch64/tcg-target-con-set.h | 1 + tcg/loongarch64/tcg-target.c.inc | 58 2 files changed, 59 insertions(+) diff --git a/tcg/loongarch64/tcg-target-con-set.h

[PATCH v2 07/14] tcg/loongarch64: Lower mul_vec to vmul

Signed-off-by: Jiajie Chen Reviewed-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 8 tcg/loongarch64/tcg-target.h | 2 +- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index

[PATCH v2 10/14] tcg/loongarch64: Lower vector shift vector ops

Lower the following ops: - shlv_vec - shrv_vec - sarv_vec Signed-off-by: Jiajie Chen Reviewed-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 24 tcg/loongarch64/tcg-target.h | 2 +- 2 files changed, 25 insertions(+), 1 deletion(-) diff --git

[PATCH v2 00/14] Lower TCG vector ops to LSX

This patch series allows qemu to utilize LSX instructions on LoongArch machines to execute TCG vector ops. Passed tcg tests with x86_64 and aarch64 cross compilers. Changes since v1: - Optimize dupi_vec/st_vec/ld_vec/cmp_vec/add_vec/sub_vec generation - Lower not_vec/shi_vec/roti_vec/rotv_vec

[PATCH v2 06/14] tcg/loongarch64: Lower neg_vec to vneg

Signed-off-by: Jiajie Chen Reviewed-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 8 tcg/loongarch64/tcg-target.h | 2 +- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index

[PATCH v2 09/14] tcg/loongarch64: Lower vector saturated ops

Lower the following ops: - ssadd_vec - usadd_vec - sssub_vec - ussub_vec Signed-off-by: Jiajie Chen Reviewed-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 32 tcg/loongarch64/tcg-target.h | 2 +- 2 files changed, 33 insertions(+), 1

[PATCH v2 13/14] tcg/loongarch64: Lower rotv_vec ops to LSX

Lower the following ops: - rotrv_vec - rotlv_vec Signed-off-by: Jiajie Chen --- tcg/loongarch64/tcg-target.c.inc | 14 ++ tcg/loongarch64/tcg-target.h | 2 +- 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/tcg/loongarch64/tcg-target.c.inc

[PATCH v2 14/14] tcg/loongarch64: Lower rotli_vec to vrotri

Signed-off-by: Jiajie Chen --- tcg/loongarch64/tcg-target.c.inc | 21 + tcg/loongarch64/tcg-target.h | 2 +- 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index 6fe319a77e..c4e9e0309e

[PATCH v2 11/14] tcg/loongarch64: Lower bitsel_vec to vbitsel

Signed-off-by: Jiajie Chen Reviewed-by: Richard Henderson --- tcg/loongarch64/tcg-target-con-set.h | 1 + tcg/loongarch64/tcg-target.c.inc | 11 ++- tcg/loongarch64/tcg-target.h | 2 +- 3 files changed, 12 insertions(+), 2 deletions(-) diff --git

[PATCH v2 12/14] tcg/loongarch64: Lower vector shift integer ops

Lower the following ops: - shli_vec - shrv_vec - sarv_vec Signed-off-by: Jiajie Chen --- tcg/loongarch64/tcg-target.c.inc | 21 + tcg/loongarch64/tcg-target.h | 2 +- 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/tcg/loongarch64/tcg-target.c.inc

[PATCH v2 03/14] tcg/loongarch64: Lower cmp_vec to vseq/vsle/vslt

Signed-off-by: Jiajie Chen --- tcg/loongarch64/tcg-target-con-set.h | 1 + tcg/loongarch64/tcg-target.c.inc | 60 2 files changed, 61 insertions(+) diff --git a/tcg/loongarch64/tcg-target-con-set.h b/tcg/loongarch64/tcg-target-con-set.h index

Re: [PATCH 3/4] cxl/type3: minimum MHD cci support

On Thu, 31 Aug 2023 12:59:24 -0400 Gregory Price wrote: > On Mon, Aug 07, 2023 at 03:56:09PM +0100, Jonathan Cameron wrote: > > On Fri, 21 Jul 2023 12:35:08 -0400 > > Gregory Price wrote: > > > > > Implement the MHD GET_INFO cci command and add a shared memory > > > region to the type3

Re: [PATCH] roms: Support compile the efi bios for loongarch

ping! Hi,Philippe Mathieu-Daudé: Would like to know if there is any progress in the discussion on this issue? In addition, is the compilation of our UEFI done on the fedora38 operating system or on a later version of fedora? The loongarch cross-compilation tool on the fedora38 operating

Re: [PATCH 7/7] qobject atomics osdep: Make a few macros more hygienic

Eric Blake writes: > On Thu, Aug 31, 2023 at 03:25:46PM +0200, Markus Armbruster wrote: > > [This paragraph written last: Bear with my stream of consciousness > review below, where I end up duplicating some of the conslusions you > reached before the point where I saw where the patch was headed]

Re: [PATCH v3.2 5/7] aspeed: Create flash devices only when defaults are enabled

On Thu, 31 Aug 2023 at 21:13, Cédric Le Goater wrote: > > When the -nodefaults option is set, flash devices should be created > with : > > -blockdev node-name=fmc0,driver=file,filename=./flash.img \ > -device mx66u51235f,cs=0x0,bus=ssi.0,drive=fmc0 \ > > To be noted that in this case,

Re: [PATCH for-8.2 v2 2/2] migration: Allow user to specify migration switchover bandwidth

On Fri, Sep 01, 2023 at 02:55:08PM +0800, Wang, Lei wrote: > On 8/3/2023 23:53, Peter Xu wrote: > > Migration bandwidth is a very important value to live migration. It's > > because it's one of the major factors that we'll make decision on when to > > switchover to destination in a precopy

Re: [PATCH v3 10/20] hw/virtio: add config support to vhost-user-device

On Thu, Aug 31, 2023 at 6:03 PM Alex Bennée wrote: > > Albert Esteve writes: > > > Sorry to bring up this post, it's been a while since you posted. > > But I have been testing the patch the last couple of days. > > > > On Mon, Jul 10, 2023 at 9:58 PM Michael S. Tsirkin > wrote: > > > > On

Re: [PATCH v3 14/17] i386: Use CPUCacheInfo.share_level to encode CPUID[4]

Hi Babu, On Wed, Aug 23, 2023 at 12:18:30PM -0500, Moger, Babu wrote: > Date: Wed, 23 Aug 2023 12:18:30 -0500 > From: "Moger, Babu" > Subject: Re: [PATCH v3 14/17] i386: Use CPUCacheInfo.share_level to encode > CPUID[4] > > Hi Zhao, > > On 8/18/23 02:37, Zhao Liu wrote: > > Hi Babu, > > > >

[PULL 09/14] block/throttle-groups: Use ThrottleDirection instread of bool is_write

From: zhenwei pi 'bool is_write' style is obsolete from throttle framework, adapt block throttle groups to the new style: - use ThrottleDirection instead of 'bool is_write'. Ex, schedule_next_request(ThrottleGroupMember *tgm, bool is_write) -> schedule_next_request(ThrottleGroupMember *tgm,

[PULL 04/14] test-throttle: test read only and write only

From: zhenwei pi Reviewed-by: Alberto Garcia Reviewed-by: Hanna Czenczek Signed-off-by: zhenwei pi Message-Id: <20230728022006.1098509-5-pizhen...@bytedance.com> Signed-off-by: Hanna Czenczek --- tests/unit/test-throttle.c | 66 ++ 1 file changed, 66

[PULL 06/14] throttle: use enum ThrottleDirection instead of bool is_write

From: zhenwei pi enum ThrottleDirection is already there, use ThrottleDirection instead of 'bool is_write' for throttle API, also modify related codes from block, fsdev, cryptodev and tests. Reviewed-by: Hanna Czenczek Signed-off-by: zhenwei pi Message-Id:

[PULL 12/14] file-posix: Fix zone update in I/O error path

We must check that zone information is present before running update_zones_wp(). Fixes: https://bugzilla.redhat.com/show_bug.cgi?id=2234374 Fixes: Coverity CID 1512459 Signed-off-by: Hanna Czenczek Message-Id: <20230824155345.109765-4-hre...@redhat.com> Reviewed-by: Sam Li ---

[PULL 14/14] tests/file-io-error: New test

This is a regression test for https://bugzilla.redhat.com/show_bug.cgi?id=2234374. All this test needs to do is trigger an I/O error inside of file-posix (specifically raw_co_prw()). One reliable way to do this without requiring special privileges is to use a FUSE export, which allows us to

[PULL 13/14] file-posix: Simplify raw_co_prw's 'out' zone code

We duplicate the same condition three times here, pull it out to the top level. Signed-off-by: Hanna Czenczek Message-Id: <20230824155345.109765-5-hre...@redhat.com> Reviewed-by: Sam Li --- block/file-posix.c | 18 +- 1 file changed, 5 insertions(+), 13 deletions(-) diff --git

[PULL 11/14] file-posix: Check bs->bl.zoned for zone info

Instead of checking bs->wps or bs->bl.zone_size for whether zone information is present, check bs->bl.zoned. That is the flag that raw_refresh_zoned_limits() reliably sets to indicate zone support. If it is set to something other than BLK_Z_NONE, other values and objects like bs->wps and

[PULL 08/14] fsdev: Use ThrottleDirection instread of bool is_write

From: zhenwei pi 'bool is_write' style is obsolete from throttle framework, adapt fsdev to the new style. Cc: Greg Kurz Reviewed-by: Hanna Czenczek Signed-off-by: zhenwei pi Message-Id: <20230728022006.1098509-9-pizhen...@bytedance.com> Reviewed-by: Greg Kurz Signed-off-by: Hanna Czenczek

[PULL 02/14] test-throttle: use enum ThrottleDirection

From: zhenwei pi Use enum ThrottleDirection instead in the throttle test codes. Reviewed-by: Alberto Garcia Reviewed-by: Hanna Czenczek Signed-off-by: zhenwei pi Message-Id: <20230728022006.1098509-3-pizhen...@bytedance.com> Signed-off-by: Hanna Czenczek --- tests/unit/test-throttle.c | 6

[PULL 10/14] file-posix: Clear bs->bl.zoned on error

bs->bl.zoned is what indicates whether the zone information is present and valid; it is the only thing that raw_refresh_zoned_limits() sets if CONFIG_BLKZONED is not defined, and it is also the only thing that it sets if CONFIG_BLKZONED is defined, but there are no zones. Make sure that it is

[PULL 01/14] throttle: introduce enum ThrottleDirection

From: zhenwei pi Use enum ThrottleDirection instead of number index. Reviewed-by: Alberto Garcia Reviewed-by: Hanna Czenczek Signed-off-by: zhenwei pi Message-Id: <20230728022006.1098509-2-pizhen...@bytedance.com> Signed-off-by: Hanna Czenczek --- include/qemu/throttle.h | 11 ---

[PULL 00/14] Block patches

The following changes since commit f5fe7c17ac4e309e47e78f0f9761aebc8d2f2c81: Merge tag 'pull-tcg-20230823-2' of https://gitlab.com/rth7680/qemu into staging (2023-08-28 16:07:04 -0400) are available in the Git repository at: https://gitlab.com/hreitz/qemu.git tags/pull-block-2023-09-01

[PULL 05/14] cryptodev: use NULL throttle timer cb for read direction

From: zhenwei pi Operations on a cryptodev are considered as *write* only, the callback of read direction is never invoked. Use NULL instead of an unreachable path(cryptodev_backend_throttle_timer_cb on read direction). The dummy read timer(never invoked) is already removed here, it means that

[PULL 07/14] throttle: use THROTTLE_MAX/ARRAY_SIZE for hard code

From: zhenwei pi The first dimension of both to_check and bucket_types_size/bucket_types_units is used as throttle direction, use THROTTLE_MAX instead of hard coded number. Also use ARRAY_SIZE() to avoid hard coded number for the second dimension. Hanna noticed that the two array should be

[PULL 03/14] throttle: support read-only and write-only

From: zhenwei pi Only one direction is necessary in several scenarios: - a read-only disk - operations on a device are considered as *write* only. For example, encrypt/decrypt/sign/verify operations on a cryptodev use a single *write* timer(read timer callback is defined, but never invoked).

Re: [PATCH 7/7] qobject atomics osdep: Make a few macros more hygienic

Richard Henderson writes: > On 8/31/23 06:25, Markus Armbruster wrote: >> +#define PASTE(a, b) a##b > > We already have glue() in qemu/compiler.h. Missed it, will fix. > The rest of it looks quite sensible. Thanks!

Re: [PATCH 3/7] ui: Clean up local variable shadowing

Peter Maydell writes: > On Thu, 31 Aug 2023 at 14:25, Markus Armbruster wrote: >> >> Local variables shadowing other local variables or parameters make the >> code needlessly hard to understand. Tracked down with -Wshadow=local. >> Clean up: delete inner declarations when they are actually

Re: [PATCH 0/7] Steps towards enabling -Wshadow=local

Markus Armbruster writes: > Local variables shadowing other local variables or parameters make the > code needlessly hard to understand. Bugs love to hide in such code. > Evidence: PATCH 1. > > Enabling -Wshadow would prevent bugs like this one. But we'd have to > clean up all the offenders

Re: [PATCH 00/11] (few more) Steps towards enabling -Wshadow

Philippe Mathieu-Daudé writes: > For rational see Markus cover on > https://lore.kernel.org/qemu-devel/20230831132546.3525721-1-arm...@redhat.com/ > > This series contains few more, my take. > > Based-on: <20230831132546.3525721-1-arm...@redhat.com> Awesome, thanks!

Re: [PATCH] arm64: Restore trapless ptimer access

On Thu, Aug 31, 2023 at 07:00:52PM +, Colton Lewis wrote: > Due to recent KVM changes, QEMU is setting a ptimer offset resulting > in unintended trap and emulate access and a consequent performance > hit. Filter out the PTIMER_CNT register to restore trapless ptimer > access. > > Quoting

Re: [PATCH 10/11] net/eth: Clean up local variable shadowing

On 2023/09/01 7:56, Philippe Mathieu-Daudé wrote: Fix: net/eth.c:435:20: error: declaration shadows a local variable [-Werror,-Wshadow] size_t input_size = iov_size(pkt, pkt_frags); ^ net/eth.c:413:16: note: previous declaration is here size_t

Re: [PATCH v2 12/12] hw/vmapple/vmapple: Add vmapple machine type

On 30/08/2023 17:14, Alexander Graf wrote: Hi Alex, Apple defines a new "vmapple" machine type as part of its proprietary macOS Virtualization.Framework vmm. This machine type is similar to the virt one, but with subtle differences in base devices, a few special vmapple device additions and a

Re: [PATCH for-8.2 v2 2/2] migration: Allow user to specify migration switchover bandwidth

On 8/3/2023 23:53, Peter Xu wrote: > Migration bandwidth is a very important value to live migration. It's > because it's one of the major factors that we'll make decision on when to > switchover to destination in a precopy process. > > This value is currently estimated by QEMU during the whole

Re: [PATCH v2 11/12] hw/vmapple/virtio-blk: Add support for apple virtio-blk

On 30/08/2023 17:14, Alexander Graf wrote: Hi Alex, Apple has its own virtio-blk PCI device ID where it deviates from the official virtio-pci spec slightly: It puts a new "apple type" field at a static offset in config space and introduces a new barrier command. This patch first creates a

Re: [PATCH v4 2/5] s390x: switch pv and subsystem reset ordering on reboot

On 8/31/23 18:21, Marc Hartmayer wrote: On Wed, Aug 23, 2023 at 04:22 PM +0200, Steffen Eiden wrote: From: Janosch Frank Bound APQNs have to be reset before tearing down the secure config via s390_machine_unprotect(). Otherwise the Ultravisor will return a error code. So let's switch the

[PATCH 1/1] accel/tcg: Fix the comment for CPUTLBEntryFull

When memory region is ram, the lower TARGET_PAGE_BITS is not the physical section number. Instead, its value is always 0. Add comment and assert to make it clear. Signed-off-by: LIU Zhiwei --- accel/tcg/cputlb.c | 11 +++ include/exec/cpu-defs.h | 12 ++-- 2 files changed,

[PATCH 4/4] target/i386: add live migration support for FRED

FRED CPU states are managed in 10 FRED MSRs, in addtion to a few existing CPU registers and MSRs, e.g., the CR4.FRED bit. Add the 10 new FRED MSRs to x86 CPUArchState for live migration support. Tested-by: Shan Kang Signed-off-by: Xin Li --- target/i386/cpu.h | 24 +++

[PATCH 3/4] target/i386: enumerate VMX nested-exception support

Allow VMX nested-exception support to be exposed in KVM guests, thus nested KVM guests can enumerate it. Tested-by: Shan Kang Signed-off-by: Xin Li --- target/i386/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 3dba6b46d9..ba579e1fb7

[PATCH 0/4] target/i386: add support for FRED

This patch set adds support for the Intel flexible return and event delivery (FRED) architecture to allow Qemu to run KVM guests with FRED enabled. The FRED architecture defines simple new transitions that change privilege level (ring transitions). The FRED architecture was designed with the

[PATCH 2/4] target/i386: mark CR4.FRED not reserved

The CR4.FRED bit, i.e., CR4[32], is no longer a reserved bit when FRED is exposed to guests, otherwise it is still a reserved bit. Tested-by: Shan Kang Signed-off-by: Xin Li --- target/i386/cpu.h | 12 +++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.h

[PATCH 1/4] target/i386: add support for FRED in CPUID enumeration

FRED, i.e., the Intel flexible return and event delivery architecture, defines simple new transitions that change privilege level (ring transitions). In addition to these transitions, the FRED architecture defines a new instruction (LKGS) for managing the state of the GS segment register. The

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