On 9/7/23 06:36, Nicholas Piggin wrote:
On Wed Sep 6, 2023 at 2:33 PM AEST, Harsh Prateek Bora wrote:
This patch introduces new data structures to be used with Nested PAPR
API. Also extends kvmppc_hv_guest_state with additional set of registers
supported with nested PAPR API.
Signed-off-by:
From: Daniel Henrique Barboza
The cpu->cfg.epmp extension is still experimental, but it already has a
'smepmp' riscv,isa string. Add it.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Weiwei Li
Reviewed-by: Alistair Francis
Message-Id: <20230720132424.371132-3-dbarb...@ventanamicro.com>
From: Nazar Kazakov
This commit adds support for the Zvkg vector-crypto extension, which
consists of the following instructions:
* vgmul.vv
* vghsh.vv
Translation functions are defined in
`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
`target/riscv/vcrypto_helper.c`.
From: LIU Zhiwei
We should not use types dependend on host arch for target_ucontext.
This bug is found when run rv32 applications.
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Philippe Mathieu-Daudé
Message-ID:
From: Dickon Hood
This commit adds support for the Zvbb vector-crypto extension, which
consists of the following instructions:
* vrol.[vv,vx]
* vror.[vv,vx,vi]
* vbrev8.v
* vrev8.v
* vandn.[vv,vx]
* vbrev.v
* vclz.v
* vctz.v
* vcpop.v
* vwsll.[vv,vx,vi]
Translation functions are defined in
From: Max Chou
Allows sharing of sm4_subword between different targets.
Signed-off-by: Max Chou
Reviewed-by: Frank Chang
Reviewed-by: Richard Henderson
Signed-off-by: Max Chou
Message-ID: <20230711165917.2629866-14-max.c...@sifive.com>
Signed-off-by: Alistair Francis
---
From: Yong-Xuan Wang
Select KVM AIA when the host kernel has in-kernel AIA chip support.
Since KVM AIA only has one APLIC instance, we map the QEMU APLIC
devices to KVM APLIC.
Signed-off-by: Yong-Xuan Wang
Reviewed-by: Jim Shu
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
From: Yong-Xuan Wang
KVM AIA can't emulate APLIC only. When "aia=aplic" parameter is passed,
APLIC devices is emulated by QEMU. For "aia=aplic-imsic", remove the
mmio operations of APLIC when using KVM AIA and send wired interrupt
signal via KVM_IRQ_LINE API.
After KVM AIA enabled, MSI messages
From: Vineet Gupta
zicond is now codegen supported in both llvm and gcc.
This change allows seamless enabling/testing of zicond in downstream
projects. e.g. currently riscv-gnu-toolchain parses elf attributes
to create a cmdline for qemu but fails short of enabling it because of
the "x-"
From: Daniel Henrique Barboza
zmmul was promoted from experimental to ratified in commit 6d00ffad4e95.
Add a riscv,isa string for it.
Fixes: 6d00ffad4e95 ("target/riscv: move zmmul out of the experimental
properties")
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Weiwei Li
Reviewed-by:
On 9/8/23 11:29, Joao Martins wrote:
QEMU computes the DMA logging ranges for two predefined ranges: 32-bit
and 64-bit. In the OVMF case, when the dynamic MMIO window is enabled,
QEMU includes in the 64-bit range the RAM regions at the lower part
and vfio-pci device RAM regions which are at the
From: Kiran Ostrolenk
Refactor the non SEW-specific stuff out of `GEN_OPIVV_TRANS` into
function `opivv_trans` (similar to `opivi_trans`). `opivv_trans` will be
used in proceeding vector-crypto commits.
Signed-off-by: Kiran Ostrolenk
Reviewed-by: Richard Henderson
Reviewed-by: Alistair
From: Lawrence Hunter
This commit adds support for the Zvksh vector-crypto extension, which
consists of the following instructions:
* vsm3me.vv
* vsm3c.vi
Translation functions are defined in
`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
`target/riscv/vcrypto_helper.c`.
From: Yong-Xuan Wang
In this patch, we create the APLIC and IMSIC FDT helper functions and
remove M mode AIA devices when using KVM acceleration.
Signed-off-by: Yong-Xuan Wang
Reviewed-by: Jim Shu
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
Message-ID:
From: Conor Dooley
On a dtb dumped from the virt machine, dt-validate complains:
soc: pmu: {'riscv,event-to-mhpmcounters': [[1, 1, 524281], [2, 2, 524284],
[65561, 65561, 524280], [65563, 65563, 524280], [65569, 65569, 524280]],
'compatible': ['riscv,pmu']} should not be valid under {'type':
From: Daniel Henrique Barboza
Commit 6df0b37e2ab breaks a --enable-debug build in a non-KVM
environment with the following error:
/usr/bin/ld: libqemu-riscv64-softmmu.fa.p/hw_intc_riscv_aplic.c.o: in function
`riscv_kvm_aplic_request':
./qemu/build/../hw/intc/riscv_aplic.c:486: undefined
From: Max Chou
This commit adds support for the Zvksed vector-crypto extension, which
consists of the following instructions:
* vsm4k.vi
* vsm4r.[vv,vs]
Translation functions are defined in
`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
`target/riscv/vcrypto_helper.c`.
From: Rob Bradford
These are WARL fields - zero out the bits for unavailable counters and
special case the TM bit in mcountinhibit which is hardwired to zero.
This patch achieves this by modifying the value written so that any use
of the field will see the correctly masked bits.
Tested by
From: Kiran Ostrolenk
Move some macros out of `vector_helper` and into `vector_internals`.
This ensures they can be used by both vector and vector-crypto helpers
(latter implemented in proceeding commits).
Signed-off-by: Kiran Ostrolenk
Reviewed-by: Weiwei Li
Signed-off-by: Max Chou
From: Yong-Xuan Wang
We create a vAIA chip by using the KVM_DEV_TYPE_RISCV_AIA and then set up
the chip with the KVM_DEV_RISCV_AIA_GRP_* APIs.
We also extend KVM accelerator to specify the KVM AIA mode. The "riscv-aia"
parameter is passed along with --accel in QEMU command-line.
1)
From: Lawrence Hunter
This commit adds support for the Zvbc vector-crypto extension, which
consists of the following instructions:
* vclmulh.[vx,vv]
* vclmul.[vx,vv]
Translation functions are defined in
`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
From: Nazar Kazakov
This commit adds support for the Zvkned vector-crypto extension, which
consists of the following instructions:
* vaesef.[vv,vs]
* vaesdf.[vv,vs]
* vaesdm.[vv,vs]
* vaesz.vs
* vaesem.[vv,vs]
* vaeskf1.vi
* vaeskf2.vi
Translation functions are defined in
From: LIU Zhiwei
Commit bef6f008b98(accel/tcg: Return bool from page_check_range) converts
integer return value to bool type. However, it wrongly converted the use
of the API in riscv fault-only-first, where page_check_range < = 0, should
be converted to !page_check_range.
Signed-off-by: LIU
From: Nazar Kazakov
Remove the redundant "vl == 0" check which is already included within the
vstart >= vl check, when vl == 0.
Signed-off-by: Nazar Kazakov
Reviewed-by: Weiwei Li
Signed-off-by: Max Chou
Acked-by: Alistair Francis
Message-ID: <20230711165917.2629866-4-max.c...@sifive.com>
From: Nazar Kazakov
Move the checks out of `do_opiv{v,x,i}_gvec{,_shift}` functions
and into the corresponding macros. This enables the functions to be
reused in proceeding commits without check duplication.
Signed-off-by: Nazar Kazakov
Reviewed-by: Richard Henderson
Reviewed-by: Weiwei Li
From: Max Chou
Adds sm4_ck constant for use in sm4 cryptography across different targets.
Signed-off-by: Max Chou
Reviewed-by: Frank Chang
Signed-off-by: Max Chou
Message-ID: <20230711165917.2629866-15-max.c...@sifive.com>
Signed-off-by: Alistair Francis
---
include/crypto/sm4.h | 1 +
From: Daniel Henrique Barboza
The 'host' CPU is available in a CONFIG_KVM build and it's currently
available for all accels, but is a KVM only CPU. This means that in a
RISC-V KVM capable host we can do things like this:
$ ./build/qemu-system-riscv64 -M virt,accel=tcg -cpu host --nographic
From: Thomas Huth
Values that have been read via cpu_physical_memory_read() from the
guest's memory have to be swapped in case the host endianess differs
from the guest.
Fixes: a6e13e31d5 ("riscv_htif: Support console output via proxy syscall")
Signed-off-by: Thomas Huth
Reviewed-by: Alistair
-20230911
for you to fetch changes up to e7a03409f29e2da59297d55afbaec98c96e43e3a:
target/riscv: don't read CSR in riscv_csrrw_do64 (2023-09-11 11:45:55 +1000)
First RISC-V PR for 8.2
* Remove 'host' CPU from TCG
* riscv_htif
From: Thomas Huth
The character that should be printed is stored in the 64 bit "payload"
variable. The code currently tries to print it by taking the address
of the variable and passing this pointer to qemu_chr_fe_write(). However,
this only works on little endian hosts where the least
Signed-off-by: LIU Zhiwei
---
v2:
1) Use rdtime instead of rdcycle for dynamic cpuclk adjustment.
2) Read timeh twice in case of time overflow for 32-bit cpu.
---
include/qemu/timer.h | 22 ++
1 file changed, 22 insertions(+)
diff --git a/include/qemu/timer.h
On 9/7/23 05:18, Nicholas Piggin wrote:
On Wed Sep 6, 2023 at 2:33 PM AEST, Harsh Prateek Bora wrote:
Adding new macros for the new hypercall op-codes, their return codes,
Guest State Buffer (GSB) element IDs and few registers which shall be
used in following patches to support Nested PAPR
On 10/09/2023 09.30, Michael Tokarev wrote:
There's one commit, tagged v7.2.2, without Signed-off-by line.
Due to this, check-dco test always fail on 7.2. Since this is
a stable branch with almost all commits coming from master
already with S-o-b (except of the version bumps and very rare
301 - 333 of 333 matches
Mail list logo
