Laurent Vivier writes:
> Fix following warnings
>
> .../disas/m68k.c: In function ‘print_insn_arg’:
> .../disas/m68k.c:1635:13: warning: declaration of ‘val’ shadows a previous
> local [-Wshadow=compatible-local]
> 1635 | int val = fetch_arg (buffer, place, 5, info);
> |
Klaus Jensen writes:
> From: Klaus Jensen
>
> Fix local variable shadowing in nvme_ns_init().
>
> Reported-by: Markus Armbruster
> Signed-off-by: Klaus Jensen
Queued, thanks!
Daniel Henrique Barboza writes:
> CCing Markus since he might want to add these in his shadow-next tree.
Queued, thanks!
Eric Blake writes:
> Address all compiler complaints from -Wshadow in qemu-nbd. Several
> instances of 'int ret' became shadows when commit 4fbec260 added 'ret'
> at a higher scope in main. More interesting was the 'void *ret'
> capturing the result of a pthread; where we were conceptually doin
Queued, thanks!
Daniel P. Berrangé writes:
> This is confusing as one 'action' variable is used for storing
> a SCMP_ enum value, while the other 'action' variable is used
> for storing a SECCOMP_ enum value.
>
> Signed-off-by: Daniel P. Berrangé
> ---
> softmmu/qemu-seccomp.c | 4 ++--
> 1 file changed, 2 ins
Peter Xu writes:
> This patch fixes the warning of shadowed local variable:
>
> ../hw/i386/intel_iommu.c: In function ‘vtd_address_space_unmap’:
> ../hw/i386/intel_iommu.c:3773:18: warning: declaration of ‘size’ shadows a
> previous local [-Wshadow=compatible-local]
> 3773 | uint64_t si
Cédric Le Goater writes:
> Hello,
>
> Here are cleanups for local variable shadowing warnings in aspeed models.
>
> Joel, Andrew,
>
> Could you please double check patch 4 ?
>
> Thanks,
>
> C.
Queued, thanks!
Reviewed-by: Richard Henderson
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1667
Signed-off-by: Bastian Koppelmann
Message-ID: <20230828112651.522058-8-kbast...@mail.uni-paderborn.de>
---
target/tricore/fpu_helper.c | 36 +++
target/tricore/helper.h
this is not something other ISAs do, so clarify it with a comment.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message-ID: <20230828112651.522058-6-kbast...@mail.uni-paderborn.de>
---
target/tricore/fpu_helper.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/targe
Markus Armbruster writes:
> Philippe Mathieu-Daudé writes:
>
>> Since v1:
>> - Addressed review comments
>> - Added R-b tags
>> - More patches
>>
>> For rational see Markus cover on
>> https://lore.kernel.org/qemu-devel/20230831132546.3525721-1-arm...@redhat.com/
>>
>> This series contains few m
RSx for d regs and e regs now use the same numbering. This makes sure
that mixing d and e registers in an insn test will not overwrite data
between registers.
Signed-off-by: Bastian Koppelmann
Message-ID: <20230913105326.40832-2-kbast...@mail.uni-paderborn.de>
---
tests/tcg/tricore/asm/macros.h
these are already defined in 'csfr.h.inc'. We don't need to duplicate
these registers.
Signed-off-by: Bastian Koppelmann
Message-ID: <20230913105326.40832-10-kbast...@mail.uni-paderborn.de>
---
target/tricore/cpu.h | 143 +++
1 file changed, 9 insertions(+
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message-ID: <20230828112651.522058-5-kbast...@mail.uni-paderborn.de>
---
target/tricore/fpu_helper.c | 32 +++
target/tricore/helper.h | 1 +
target/tricore/translate.c
as this is an effective address and those cannot be signed,
it should not be a signed integer.
Signed-off-by: Bastian Koppelmann
Message-ID: <20230913105326.40832-11-kbast...@mail.uni-paderborn.de>
---
target/tricore/op_helper.c | 16
1 file changed, 8 insertions(+), 8 deletions
Acked-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message-ID: <20230828112651.522058-10-kbast...@mail.uni-paderborn.de>
---
target/tricore/translate.c | 8
tests/tcg/tricore/asm/macros.h | 9 +
tests/tcg/tricore/asm/test_insert.S | 5 +
3 files chan
reported in https://gitlab.com/qemu-project/qemu/-/issues/1667
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message-ID: <20230828112651.522058-3-kbast...@mail.uni-paderborn.de>
---
target/tricore/helper.h | 1 +
target/tricore/op_helper.c|
when we reconstructed PSW using psw_read(), we were trying to clear the
cached USB bits out of env->PSW. The mask was wrong and we would clear
PSW.RM as well.
when we write the PSW using psw_write() we update the rounding modes in
env->fp_status for softfloat. The order of bits used by TriCore is
Signed-off-by: Bastian Koppelmann
Message-ID: <20230913105326.40832-3-kbast...@mail.uni-paderborn.de>
---
hw/tricore/tricore_testdevice.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/tricore/tricore_testdevice.c b/hw/tricore/tricore_testdevice.c
index a1563aa568..9028d970b0 100644
-
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message-ID: <20230828112651.522058-11-kbast...@mail.uni-paderborn.de>
---
target/tricore/translate.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message-ID: <20230828112651.522058-12-kbast...@mail.uni-paderborn.de>
---
target/tricore/translate.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
i
reported in https://gitlab.com/qemu-project/qemu/-/issues/1667
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message-ID: <20230828112651.522058-7-kbast...@mail.uni-paderborn.de>
---
target/tricore/fpu_helper.c | 38 +++
target/tricore/helper.
some insns use the result register implicitly as an input. Thus, we
could end up with data from the previous insn spilling over.
Signed-off-by: Bastian Koppelmann
Message-ID: <20230913105326.40832-4-kbast...@mail.uni-paderborn.de>
---
tests/tcg/tricore/asm/macros.h | 3 ++-
1 file changed, 2 ins
The following changes since commit 36e9aab3c569d4c9ad780473596e18479838d1aa:
migration: Move return path cleanup to main migration thread (2023-09-27
13:58:02 -0400)
are available in the Git repository at:
https://github.com/bkoppelmann/qemu.git tags/pull-tricore-20230929
for you to fetch
we don't want to exclude ISA v1.6.2 insns from our tests.
Acked-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message-Id: <20230828112651.522058-2-kbast...@mail.uni-paderborn.de>
---
tests/tcg/tricore/Makefile.softmmu-target | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
we would crash if width was 0 for these insns, as tcg_gen_deposit() is
undefined for that case. For TriCore, width = 0 is a mov from the src reg
to the dst reg, so we special case this here.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Mes
Hi,
On Thu, Sep 28, 2023 at 10:26:18AM -0400, Stefan Hajnoczi wrote:
> Please take a look at these CI test failures:
> https://gitlab.com/qemu-project/qemu/-/jobs/5185201978
> https://gitlab.com/qemu-project/qemu/-/jobs/5185202098
I'll fix the build failure and drop the patches that fail the TriC
On 29/09/2023 02.08, Chris Rauer wrote:
npcm7xx_timer-test occasionally fails due to the state of the timers
from the previous test iteration. Advancing the clock step after the
reset resolves this issue.
Fixes: https://gitlab.com/qemu-project/qemu/-/issues/1897
Signed-off-by: Chris Rauer
---
On 9/29/23 11:37, Cédric Le Goater wrote:
On 9/29/23 07:39, Markus Armbruster wrote:
Harsh Prateek Bora writes:
On Tue, 19 Sept, 2023, 5:39 pm Cédric Le Goater, wrote:
On 9/19/23 10:48, Harsh Prateek Bora wrote:
On 9/18/23 20:28, Cédric Le Goater wrote:
Rename 'name' variable to avo
Peter Maydell writes:
> These patches fix some -Wshadow warnings in arm related code.
Queued, thanks!
> On 29-Sep-2023, at 11:43 AM, Markus Armbruster wrote:
>
> Ani Sinha writes:
>
>>> On 29-Sep-2023, at 11:17 AM, Markus Armbruster wrote:
>>>
>>> Ani Sinha writes:
>>>
Code changes in acpi that addresses all compiler complaints coming from
enabling
-Wshadow flags. Enablin
Ani Sinha writes:
>> On 29-Sep-2023, at 11:17 AM, Markus Armbruster wrote:
>>
>> Ani Sinha writes:
>>
>>> Code changes in acpi that addresses all compiler complaints coming from
>>> enabling
>>> -Wshadow flags. Enabling -Wshadow catches cases of local variables shadowing
>>> other local vari
On 9/29/23 07:30, Markus Armbruster wrote:
Cédric Le Goater writes:
On 9/19/23 08:57, Harsh Prateek Bora wrote:
On 9/18/23 20:28, Cédric Le Goater wrote:
to fix :
../hw/ppc/pnv_psi.c: In function ‘pnv_psi_p9_mmio_write’:
../hw/ppc/pnv_psi.c:741:24: warning: declaration of ‘addr’ sha
On 9/29/23 07:39, Markus Armbruster wrote:
Harsh Prateek Bora writes:
On Tue, 19 Sept, 2023, 5:39 pm Cédric Le Goater, wrote:
On 9/19/23 10:48, Harsh Prateek Bora wrote:
On 9/18/23 20:28, Cédric Le Goater wrote:
Rename 'name' variable to avoid this warning :
../hw/ppc/spapr_drc.c:
Markus Armbruster writes:
> Local variables shadowing other local variables or parameters make the
> code needlessly hard to understand. Bugs love to hide in such code.
> Evidence: PATCH 1.
>
> Enabling -Wshadow would prevent bugs like this one. But we'd have to
> clean up all the offenders fir
> On 29-Sep-2023, at 11:17 AM, Markus Armbruster wrote:
>
> Ani Sinha writes:
>
>> Code changes in acpi that addresses all compiler complaints coming from
>> enabling
>> -Wshadow flags. Enabling -Wshadow catches cases of local variables shadowing
>> other local variables or parameters. Thes
Ani Sinha writes:
> Code changes in acpi that addresses all compiler complaints coming from
> enabling
> -Wshadow flags. Enabling -Wshadow catches cases of local variables shadowing
> other local variables or parameters. These makes the code confusing and/or
> adds
> bugs that are difficult to
On 9/29/23 11:04, Markus Armbruster wrote:
Harsh Prateek Bora writes:
On Tue, 19 Sept, 2023, 5:33 pm Cédric Le Goater, wrote:
On 9/19/23 10:29, Harsh Prateek Bora wrote:
On 9/18/23 20:28, Cédric Le Goater wrote:
Remove extra 'drc_index' variable to avoid this warning :
../hw/ppc
Alberto Garcia writes:
> Fixes build with -Wshadow=local
>
> Signed-off-by: Alberto Garcia
> ---
> tests/unit/test-throttle.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/tests/unit/test-throttle.c b/tests/unit/test-throttle.c
> index cb587e33e7..ac35d65d19 100644
>
Harsh Prateek Bora writes:
> On Tue, 19 Sept, 2023, 5:39 pm Cédric Le Goater, wrote:
>
>> On 9/19/23 10:48, Harsh Prateek Bora wrote:
>> >
>> >
>> > On 9/18/23 20:28, Cédric Le Goater wrote:
>> >> Rename 'name' variable to avoid this warning :
>> >>
>> >>../hw/ppc/spapr_drc.c: In function ‘p
Harsh Prateek Bora writes:
> On Tue, 19 Sept, 2023, 5:33 pm Cédric Le Goater, wrote:
>
>> On 9/19/23 10:29, Harsh Prateek Bora wrote:
>> >
>> >
>> > On 9/18/23 20:28, Cédric Le Goater wrote:
>> >> Remove extra 'drc_index' variable to avoid this warning :
>> >>
>> >>../hw/ppc/spapr_drc.c: In
On Wed, Sep 27, 2023 at 4:32 AM Daniel Henrique Barboza
wrote:
>
> Hi,
>
> At this moment we do not expose extension properties for vendor CPUs
> because that would allow users to enable extensions in them. But that
> comes at a cost: if we were to add an API that shows all CPU properties,
> e.g.
Cédric Le Goater writes:
> On 9/19/23 08:57, Harsh Prateek Bora wrote:
>> On 9/18/23 20:28, Cédric Le Goater wrote:
>>> to fix :
>>>
>>> ../hw/ppc/pnv_psi.c: In function ‘pnv_psi_p9_mmio_write’:
>>> ../hw/ppc/pnv_psi.c:741:24: warning: declaration of ‘addr’ shadows a
>>> parameter [-Wshado
Philippe Mathieu-Daudé writes:
> Just missed while posting v2 eh :/
> (https://lore.kernel.org/qemu-devel/20230904161235.84651-1-phi...@linaro.org/)
PATCH 3 has become commit 82fdcd3e140c8d4c63f177ece554f90f2bccdf68.
Remainder queued. Thanks!
On Wed, Sep 27, 2023 at 4:32 AM Daniel Henrique Barboza
wrote:
>
> At this moment we do not expose extension properties for vendor CPUs
> because that would allow users to change them via command line. The
> drawback is that if we were to add an API that shows all CPU properties,
> e.g. qmp-query-
Philippe Mathieu-Daudé writes:
> Since v1:
> - Addressed review comments
> - Added R-b tags
> - More patches
>
> For rational see Markus cover on
> https://lore.kernel.org/qemu-devel/20230831132546.3525721-1-arm...@redhat.com/
>
> This series contains few more, my take.
>
> Based-on: <20230831132
On Wed, Sep 27, 2023 at 6:10 AM Daniel Henrique Barboza
wrote:
>
> We got along without property getters in the KVM driver because we never
> needed them. But the incoming query-cpu-model-expansion API will use
> property getters and setters to retrieve the CPU characteristics.
>
> Add the missing
Philippe Mathieu-Daudé writes:
> hw/ide/ahci.c:1577:23: error: declaration shadows a local variable
> [-Werror,-Wshadow]
> IDEState *s = &ad->port.ifs[j];
> ^
> hw/ide/ahci.c:1569:29: note: previous declaration is here
> void ahci_uninit(AHCIState *s)
>
Philippe Mathieu-Daudé writes:
> Fix:
>
> hw/mips/boston.c:472:5: error: declaration shadows a local variable
> [-Werror,-Wshadow]
> qemu_fdt_setprop_cells(fdt, name, "reg", reg_base, reg_size);
> ^
> include/sysemu/device_tree.h:129:13: note: expanded from macro
> 'qemu_fdt_setprop
Hi Salil,
On 9/26/23 20:36, Salil Mehta wrote:
Physical CPU hotplug results in (un)setting of ACPI _STA.Present bit. AARCH64
platforms do not support physical CPU hotplug. Virtual CPU hotplug support being
implemented toggles ACPI _STA.Enabled Bit to achieve hotplug functionality. This
is not sa
Hi Salil,
On 9/26/23 20:36, Salil Mehta wrote:
From: Author Salil Mehta
Add registration and Handling of HVC/SMC hypercall exits to VMM
Co-developed-by: Salil Mehta
Signed-off-by: Salil Mehta
Co-developed-by: Jean-Philippe Brucker
Signed-off-by: Jean-Philippe Brucker
Signed-off-by: Salil
Ping.
r~
On 8/31/23 19:22, Richard Henderson wrote:
Based-on: 20230829220228.928506-1-richard.hender...@linaro.org
("[PATCH v5 00/20] linux-user: Implement VDSOs")
Changes for v2:
* Minor adjustments to bsd-user.
* Update docs for deprecation.
* Philippe's r-b.
Blurb from v1:
While
On 9/28/23 17:41, Nick Bowler wrote:
On 2023-09-28, Richard Henderson wrote:
Belated follow-up suggestion:
- if ((tmp & 0xff) > 0x7f) {
- tmp += 0x100;
- }
+ tmp += 0x80;
7 occurrences throughout vis_helper.c.
I agree with making this particular change but I think since it doesn
One comment on the logging stuff in vhost-scsi. As far as I can tell the
logging in vhost-user-scsi looks good.
Markus - does this look better to you? Otherwise do you think we should also
fix up the vhost-user-blk realize function?
> On Sep 22, 2023, at 7:46 AM, Li Feng wrote:
>
> If the bac
> On Sep 22, 2023, at 7:46 AM, Li Feng wrote:
>
> Let's keep the same behavior as vhost-user-blk.
>
> Some old guests kick virtqueue before setting VIRTIO_CONFIG_S_DRIVER_OK.
>
Reviewed-by: Raphael Norwitz
> Signed-off-by: Li Feng
> ---
> hw/scsi/vhost-user-scsi.c | 48 ++
> On Sep 22, 2023, at 7:46 AM, Li Feng wrote:
>
> When the vhost-user is reconnecting to the backend, and if the vhost-user
> fails
> at the get_features in vhost_dev_init(), then the reconnect will fail
> and it will not be retriggered forever.
>
> The reason is:
> When the vhost-user fails
> On Sep 22, 2023, at 7:46 AM, Li Feng wrote:
>
> When the vhost-user is reconnecting to the backend, and if the vhost-user
> fails
> at the get_features in vhost_dev_init(), then the reconnect will fail
> and it will not be retriggered forever.
>
> The reason is:
> When the vhost-user fails
> On Sep 22, 2023, at 7:46 AM, Li Feng wrote:
>
> Currently the get_inflight_fd will be sent every time the device is started,
> and
> the backend will allocate shared memory to save the inflight state. If the
> backend finds that it receives the second get_inflight_fd, it will release the
> p
On 2023-09-28, Richard Henderson wrote:
> Belated follow-up suggestion:
>
> - if ((tmp & 0xff) > 0x7f) {
> - tmp += 0x100;
> - }
> + tmp += 0x80;
>
> 7 occurrences throughout vis_helper.c.
I agree with making this particular change but I think since it doesn't
fix a bug, it should go
On 2023-09-28, Richard Henderson wrote:
> On 9/24/23 01:03, Nick Bowler wrote:
>> case 0x04b: /* VIS I fpmerge */
>> CHECK_FPU_FEATURE(dc, VIS1);
>> -gen_ne_fop_DDD(dc, rd, rs1, rs2,
>> gen_helper_fpmerge);
>> +cpu_src
On 2023-09-28, Richard Henderson wrote:
> On 9/24/23 01:03, Nick Bowler wrote:
>> All of the VIS subtraction instructions are documented to subtract the
>> second input operand from the first. This is also consistent with how
>> the instructions actually work on a real UltraSparc II.
>>
>> But th
Hi Salil,
On 9/26/23 20:04, Salil Mehta wrote:
During any vCPU hot-(un)plug, running guest VM needs to be intimated about the
new vCPU being added or request the deletion of the vCPU which is already part
of the guest VM. This is done using the ACPI GED event which eventually gets
demultiplexed
Hi Salil,
On 9/26/23 20:04, Salil Mehta wrote:
Add CPU hot-unplug hooks and update hotplug hooks with additional sanity checks
for use in hotplug paths.
Note, Functional contents of the hooks(now left with TODO comment) shall be
gradually filled in the subsequent patches in an incremental appro
npcm7xx_timer-test occasionally fails due to the state of the timers
from the previous test iteration. Advancing the clock step after the
reset resolves this issue.
Fixes: https://gitlab.com/qemu-project/qemu/-/issues/1897
Signed-off-by: Chris Rauer
---
tests/qtest/npcm7xx_timer-test.c | 1 +
1
Ack. will send out v2.
On Wed, Sep 27, 2023 at 9:44 PM Thomas Huth wrote:
> On 28/09/2023 05.45, Chris Rauer wrote:
>
> Could you please add a proper patch description how this is fixing the
> issue?
>
> Thanks,
>Thomas
>
>
> > Fixes: https://gitlab.com/qemu-project/qemu/-/issues/1897
> >
Hi Salil,
On 9/26/23 20:04, Salil Mehta wrote:
During machvirt_init(), QOM ARMCPU objects are also pre-created along with the
corresponding KVM vCPUs in the host for all possible vCPUs. This necessary
because of the architectural constraint, KVM restricts the deferred creation of
the KVM vCPUs a
On 9/26/23 20:04, Salil Mehta wrote:
From: Jean-Philippe Brucker
The GICC interface on arm64 vCPUs is statically defined in the MADT, and
doesn't require a _MAT entry. Although the GICC is indicated as present
by the MADT entry, it can only be used from vCPU sysregs, which aren't
accessible unt
Hi Salil,
On 9/26/23 20:04, Salil Mehta wrote:
Changes required during building of MADT Table by QEMU to accomodate disabled
possible vCPUs. This info shall be used by the guest kernel to size up its
resources during boot time. This pre-sizing of the guest kernel done on
possible vCPUs will faci
On 9/26/23 20:04, Salil Mehta wrote:
OSPM evaluates _EVT method to map the event. The cpu hotplug event eventually
results in start of the cpu scan. Scan figures out the cpu and the kind of
event(plug/unplug) and notifies it back to the guest.
The change in this patch updates the GED AML _EVT me
Hi Salil,
On 9/26/23 20:04, Salil Mehta wrote:
ACPI AML changes to properly reflect the _STA.PRES and _STA.ENA Bits to the
guest during initialzation, when CPUs are hotplugged and after CPUs are
hot-unplugged.
Signed-off-by: Salil Mehta
---
hw/acpi/cpu.c | 49 +++
Hi Salil,
On 9/26/23 20:04, Salil Mehta wrote:
ARM arch does not allow CPUs presence to be changed [1] after kernel has booted.
Hence, firmware/ACPI/Qemu must ensure persistent view of the vCPUs to the Guest
kernel even when they are not present in the QoM i.e. are unplugged or are
yet-to-be-plu
Ping.
r~
On 8/30/23 22:57, Richard Henderson wrote:
This is aimed at improving gvec generated code, which involves large
numbers of loads and stores to the env slots of the guest cpu vector
registers. The final patch helps eliminate redundant zero-extensions
that can appear with e.g. avx2 and
On 9/24/23 01:03, Nick Bowler wrote:
All of the VIS subtraction instructions are documented to subtract the
second input operand from the first. This is also consistent with how
the instructions actually work on a real UltraSparc II.
But the emulator is implementing the subtraction in the wrong
On 9/24/23 01:03, Nick Bowler wrote:
This instruction is documented to get its input from the second
single-precision input operand; the first operand is ignored.
This is exactly what a real UltraSparc II does. Meanwhile, the
the emulator uses only the irrelevant first operand, treating
it as a
On 9/24/23 01:03, Nick Bowler wrote:
case 0x04b: /* VIS I fpmerge */
CHECK_FPU_FEATURE(dc, VIS1);
-gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpmerge);
+cpu_src1_32 = gen_load_fpr_F(dc, rs1);
+cpu
On 9/24/23 01:03, Nick Bowler wrote:
On a real UltraSparc II, the fmuld8ulx16 instruction takes two single-
precision input operands and returns a double-precision result.
However, the emulation is taking two double-precision input operands,
which are unlikely to contain the correct values, so t
On 9/24/23 01:03, Nick Bowler wrote:
On a real UltraSparc II, the fmuld8sux16 instruction takes two single-
precision input operands and returns a double-precision result.
However, the emulation is taking two double-precision input operands,
which are unlikely to contain the correct values. Eve
On 9/24/23 01:03, Nick Bowler wrote:
On a real UltraSparc II, the fmul8x16al instruction takes two single-
precision input operands and returns a double-precision result. For
the second operand, bits 15:0 are used, and bits 31:16 are ignored.
However, the emulation is taking two double-precisio
On 9/24/23 01:03, Nick Bowler wrote:
On a real UltraSparc II, the fmul8x16au instruction takes two single-
precision input operands and returns a double-precision result. For
the second operand, bits 31:16 are used, and bits 15:0 are ignored.
However, the emulation is taking two double-precisio
On 9/24/23 01:03, Nick Bowler wrote:
On a real UltraSparc II CPU, the fmul8x16 instruction reads its first
input from any of the single-precision floating point registers.
But the emulator is reading the input as if the first operand encodes
a double-precision register, which in most cases will
On 28.09.23 17:33, Eric Blake wrote:
On Thu, Sep 28, 2023 at 12:09:51PM +0300, Vladimir Sementsov-Ogievskiy wrote:
On 27.09.23 18:59, Eric Blake wrote:
We could also try to be a bit more complicated by peeking at the next
few bytes: if they look like a magic number of the next request,
assume t
On 9/27/23 06:18, Peter Maydell wrote:
For the Thumb T32 encoding of LDM, if only a single register is
specified in the register list this instruction is UNPREDICTABLE,
with the following choices:
* instruction UNDEFs
* instruction is a NOP
* instruction loads a single register
* instruct
On 26/09/2023 09:09, Laurent Vivier wrote:
Le 09/09/2023 à 11:48, Mark Cave-Ayland a écrit :
The swim chip provides an implementation of both Apple's IWM and ISM floppy disk
controllers. Split the existing implementation into separate register banks for
each controller, whilst also switching the
On 26/09/2023 09:04, Laurent Vivier wrote:
Le 09/09/2023 à 11:48, Mark Cave-Ayland a écrit :
NetBSD assumes it can send its first ADB command after sending the ADB_BUSRESET
command in ADB_STATE_NEW without changing the state back to ADB_STATE_IDLE
first as detailed in the ADB protocol.
Add a w
On 25/09/2023 18:19, Laurent Vivier wrote:
Le 09/09/2023 à 11:48, Mark Cave-Ayland a écrit :
MacOS (un)helpfully leaves the FIFO engine running even when all the samples
have
been written to the hardware, and expects the FIFO status flags and IRQ to be
updated continuously.
There is an additi
On 9/26/23 11:56, Peter Maydell wrote:
Resolves:https://gitlab.com/qemu-project/qemu/-/issues/1899
Signed-off-by: Peter Maydell
---
target/arm/cpu.h | 22 +
hw/arm/boot.c | 95 ++-
target/arm/arm-powerctl.c | 53 +---
On 25/09/2023 06:03, Nick Bowler wrote:
I noticed that the fmul8x16 instruction did not appear to be emulated
correctly[1]. It would seem that emulation was not using a single-
precision input register like the real hardware does, but rather a
double-precision register, causing it to operate on
On Thu, 28 Sep 2023, Richard Henderson wrote:
> Just call force_sig_fault directly.
>
>
> r~
OK. Here I'm resending it.
Mikulas
From: Mikulas Patocka
Qemu mips userspace emulation crashes with "qemu: unhandled CPU exception
0x15 - aborting" when one of the integer arithmetic instructi
On 9/25/23 07:22, Peter Maydell wrote:
The hw/arm/boot.h include in common-semi-target.h is not actually
needed, and it's a bit odd because it pulls a hw/arm header into a
target/arm file.
This include was originally needed because the semihosting code used
the arm_boot_info struct to get the ba
With CF_NOIRQ and without !CF_USE_ICOUNT, the load isn't used.
Avoid emitting it.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
accel/tcg/translator.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/accel/tcg/translator.c b/accel/tcg/tr
The condition checked is loop invariant; check it only once.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
accel/tcg/translator.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c
index a
Initialize can_do_io to true if this the TB has CF_LAST_IO
and will consist of a single instruction. This avoids a
set to 0 followed immediately by a set to 1.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
accel/tcg/translator.c | 4 ++--
1 file changed, 2 insertions
Simplify translator_io_start by recording the current
known value of can_do_io within DisasContextBase.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/exec/translator.h | 2 ++
accel/tcg/translator.c| 31 ++-
2 files changed, 16
/rth7680/qemu.git tags/pull-tcg-20230928
for you to fetch changes up to 18a536f1f8d6222e562f59179e837fdfd8b92718:
accel/tcg: Always require can_do_io (2023-09-28 10:08:13 -0700)
accel/tcg: Always require can_do_io, for #1866
Require i/o as the last insn of a TranslationBlock always,
not only with icount. This is required for i/o that alters
the address space, such as a pci config space write.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1866
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Hende
Without this we can get see loops through cpu_io_recompile,
in which the cpu makes no progress.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
accel/tcg/cpu-exec.c | 2 +-
accel/tcg/tb-maint.c | 6 --
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/a
On 9/24/23 07:16, Mikulas Patocka wrote:
Qemu mips userspace emulation crashes with "qemu: unhandled CPU exception
0x15 - aborting" when one of the integer arithmetic instructions detects
an overflow.
This patch fixes it so that it delivers SIGFPE with FPE_INTOVF instead.
Signed-off-by: Mikulas
On 9/21/23 14:54, Peter Maydell wrote:
FEAT_HPMN0 is a small feature which defines that it is valid for
MDCR_EL2.HPMN to be set to 0, meaning "no PMU event counters provided
to an EL1 guest" (previously this setting was reserved). QEMU's
implementation almost gets HPMN == 0 right, but we need to
On Mon, Sep 18, 2023 at 05:53:12PM +0800, Sam Li wrote:
> By adding zone operations and zoned metadata, the zoned emulation
> capability enables full emulation support of zoned device using
> a qcow2 file. The zoned device metadata includes zone type,
> zoned device state and write pointer of each
On Mon, Sep 25, 2023 at 05:11:10PM +0100, Jonathan Cameron wrote:
> To avoid repetition of switch upstream port specific data in the
> CXLDeviceState structure it will be necessary to access the switch USP
> specific data from mailbox callbacks. Hence move it to cxl_device.h so it
> is no longer an
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