Please add a short patch description if this moves from RFC to a real patch
On 17/10/2023 21.06, BALATON Zoltan wrote:
Signed-off-by: BALATON Zoltan
---
I have no idea if this works so testing and corrections are welcome
Why don't you test it on your own? I think this should be sufficient:
On Tue, Oct 17, 2023 at 05:32:34PM -0700, Si-Wei Liu wrote:
>
>
> On 10/6/2023 2:48 AM, Michael S. Tsirkin wrote:
> > On Fri, Oct 06, 2023 at 09:58:30AM +0100, Joao Martins wrote:
> > > On 03/10/2023 15:01, Michael S. Tsirkin wrote:
> > > > On Wed, Sep 27, 2023 at 12:14:28PM +0100, Joao Martins
On 2023/10/18 2:53, Akihiko Odaki wrote:
It is initialized with a simple assignment and there is little room for
error. In fact, the validation is even more complex.
Signed-off-by: Akihiko Odaki
---
target/riscv/tcg/tcg-cpu.c | 13 ++---
1 file changed, 2 insertions(+), 11
+CC Richard
On 2023/10/17 11:37, Akihiko Odaki wrote:
On 2023/10/17 11:29, LIU Zhiwei wrote:
On 2023/10/12 13:42, Akihiko Odaki wrote:
It is initialized with a simple assignment and there is little room for
error. In fact, the validation is even more complex.
Signed-off-by: Akihiko Odaki
On 17/10/2023 17.36, Paolo Bonzini wrote:
Meson used to allow both "pkgconfig" and "pkg-config" entries in machine
files; the former was used for dependency lookup and the latter
was used as return value for "find_program('pkg-config')", which is a less
common use-case and one that QEMU does not
Peter Xu writes:
> On Tue, Oct 17, 2023 at 08:32:02AM +0200, Markus Armbruster wrote:
>> I can see two useful QAPI generator features:
>
> Agreed.
>
>>
>> * Improved handling of missing member documentation
>>
>> Problem: many members lack documentation. We silently generate
>>
On 17/10/23 17:19, Thomas Huth wrote:
hw/input/lasips2.c and the corresponding header include/hw/input/lasips2.h
are only used by the HPPA machine, so add them to the corresponding section
in the MAINTAINERS file.
Signed-off-by: Thomas Huth
---
MAINTAINERS | 2 ++
1 file changed, 2
On 18/10/23 03:19, gaosong wrote:
在 2023/10/14 上午1:51, Richard Henderson 写道:
Do not require the translators to jump through concat and
extract of i64 in order to move values to and from env.
Signed-off-by: Richard Henderson
---
include/tcg/tcg-op-common.h | 3 +++
tcg/tcg-op.c
On 17/10/23 22:08, Mark Cave-Ayland wrote:
On 17/10/2023 14:50, Philippe Mathieu-Daudé wrote:
pcspk_init() is a legacy init function, inline and remove it.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/audio/pcspk.h | 10 --
hw/i386/pc.c | 3 ++-
> -Original Message-
> From: Philippe Mathieu-Daudé
> Sent: Tuesday, October 10, 2023 12:23 AM
> To: Brian Cain ; richard.hender...@linaro.org;
> a...@rev.ng
> Cc: arm...@redhat.com; peter.mayd...@linaro.org; Matheus Bernardino
> (QUIC) ; stefa...@redhat.com; a...@rev.ng;
> Marco Liebel
David,
On 7/6/2023 3:56 PM, David Hildenbrand wrote:
ram_block_discard_range() cannot possibly do the right thing in
MAP_PRIVATE file mappings in the general case.
To achieve the documented semantics, we also have to punch a hole into
the file, possibly messing with other
This patch closes the file descriptor fd on error return to avoid
resource leak.
Fixes: ec7ee95db909 ("contrib/plugins: fix coverity warning in lockstep")
Signed-off-by: Cong Liu
---
contrib/plugins/lockstep.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/contrib/plugins/lockstep.c
Hi Cédric,
>-Original Message-
>From: Cédric Le Goater
>Sent: Tuesday, October 17, 2023 11:51 PM
>Subject: Re: [PATCH v2 02/27] vfio: Introduce base object for VFIOContainer and
>targetted interface
>
>On 10/16/23 10:31, Zhenzhong Duan wrote:
>> From: Eric Auger
>>
>> Introduce a dumb
>-Original Message-
>From: Cédric Le Goater
>Sent: Tuesday, October 17, 2023 11:51 PM
>Subject: Re: [PATCH v2 01/27] vfio: Rename VFIOContainer into
>VFIOLegacyContainer
>
>Hello,
>
>On 10/16/23 10:31, Zhenzhong Duan wrote:
>> From: Eric Auger
>>
>> In the prospect to introduce a base
On 10/14/23 03:01, Paolo Bonzini wrote:
It is not used anymore by the old decoder, inline the CMP case into CMPS and
SCAS.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 145 +++-
1 file changed, 12 insertions(+), 133 deletions(-)
On 10/14/23 03:01, Paolo Bonzini wrote:
The new decoder likes to compute the address in A0 very early, so the
gen_lea_v_seg in gen_pop_T0 would clobber the address of the memory
operand. Instead use T0 since it is already available and will be
overwritten immediately after.
Signed-off-by:
On 10/14/23 03:01, Paolo Bonzini wrote:
Use MO_SIGN to indicate signed vs. unsigned extension, and filter out
bits other than MO_SIGN and MO_SIZE.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 30 +++---
1 file changed, 15 insertions(+), 15
On 10/14/23 03:01, Paolo Bonzini wrote:
Some instructions use YMM0 implicitly, or use YMM9 as a read-modify-write
register destination. Initialize those registers as well.
Signed-off-by: Paolo Bonzini
Reviewed-by: Richard Henderson
r~
On 10/14/23 03:01, Paolo Bonzini wrote:
Instructions in VEX exception class 6 generally look at the value of
VEX.W. Note that the manual places some instructions incorrectly in
class 4, for example VPERMQ which has no non-VEX encoding and no legacy
SSE analogue. AMD does a mess of its own, as
On 10/14/23 03:01, Paolo Bonzini wrote:
@@ -224,6 +233,8 @@ struct X86OpEntry {
unsigned vex_class:8;
X86VEXSpecial vex_special:8;
uint16_t valid_prefix:16;
+uint8_t check:8;
+uint8_t intercept:8;
bool is_decode:1;
};
Unless you have
在 2023/10/14 上午1:51, Richard Henderson 写道:
Do not require the translators to jump through concat and
extract of i64 in order to move values to and from env.
Signed-off-by: Richard Henderson
---
include/tcg/tcg-op-common.h | 3 +++
tcg/tcg-op.c| 22 ++
在 2023/10/17 下午8:38, Philippe Mathieu-Daudé 写道:
RFC because unsure and untested...
Based-on: <20231013175109.124308-1-richard.hender...@linaro.org>
tcg: Add tcg_gen_{ld,st}_i128
Philippe Mathieu-Daudé (2):
target/loongarch: Use i128 for 128-bit load/store in VST[X]/XVST
On 10/6/2023 2:48 AM, Michael S. Tsirkin wrote:
On Fri, Oct 06, 2023 at 09:58:30AM +0100, Joao Martins wrote:
On 03/10/2023 15:01, Michael S. Tsirkin wrote:
On Wed, Sep 27, 2023 at 12:14:28PM +0100, Joao Martins wrote:
On setups with one or more virtio-net devices with vhost on,
dirty
On Tue, Oct 17, 2023 at 4:04 PM Nabih Estefan
wrote:
> From: Nabih Estefan Diaz
>
> - Add PCS Register check to npcm_gmac-test
>
> Signed-off-by: Nabih Estefan Diaz
>
Reviewed-by: Hao Wu
> ---
> tests/qtest/npcm_gmac-test.c | 134 ++-
> 1 file changed, 133
Please consolidate the commit message in this patch. I think we only need
to describe the functionality you implemented here (i.e. the receive (RX)
for the GMAC model) and how you did it. There's no need to keep the verbose
comment on each corner cases we had.
On Tue, Oct 17, 2023 at 4:04 PM
On Tue, Oct 17, 2023 at 4:04 PM Nabih Estefan
wrote:
> From: Nabih Estefan Diaz
>
> - General GMAC Register handling
> - GMAC IRQ Handling
> - Added traces in some methods for debugging
> - Lots of declarations for accessing information on GMAC Descriptors
> (npcm_gmac.h file)
>
> NOTE: With
On Tue, Oct 17, 2023 at 4:04 PM Nabih Estefan
wrote:
> From: Nabih Estefan Diaz
>
> - Implemeted classes for GMAC Receive and Transmit Descriptors
> - Implemented Masks for said descriptors
>
> Signed-off-by: Nabih Estefan Diaz
>
Reviewed-by: Hao Wu
> ---
> hw/net/npcm_gmac.c |
You have an extra "\" in the title.
On Tue, Oct 17, 2023 at 4:04 PM Nabih Estefan
wrote:
> From: Nabih Estefan Diaz
>
> - Created qtest to check initialization of registers in GMAC Module.
> - Implemented test into Build File.
>
> Signed-off-by: Nabih Estefan Diaz
> ---
>
Hi Marc-André,
> Hi
>
> On Fri, Oct 13, 2023 at 2:51 AM Dongwon Kim
> wrote:
> >
> > When turning on or off full-screen menu, all detached windows should
> > be full-screened or un-full-screened altogether.
>
> I am not convinced this is desirable. Not only having multiple fullscreen
>
From: Hao Wu
This patch wires the PCI mailbox module to Nuvoton SoC.
Google-Rebase-Count: 5
Google-Bug-Id: 262938292
Signed-off-by: Hao Wu
Change-Id: Ifd858a7ed760557faa15a7a1cef66b2056f06e2e
---
docs/system/arm/nuvoton.rst | 2 ++
hw/arm/npcm7xx.c| 3 ++-
include/hw/arm/npcm7xx.h
From: Nabih Estefan Diaz
- General GMAC Register handling
- GMAC IRQ Handling
- Added traces in some methods for debugging
- Lots of declarations for accessing information on GMAC Descriptors
(npcm_gmac.h file)
NOTE: With code on this state, the GMAC can boot-up properly and will show up
in
From: Hao Wu
Signed-off-by: Hao Wu
---
hw/arm/npcm7xx.c | 36 ++--
include/hw/arm/npcm7xx.h | 2 ++
2 files changed, 36 insertions(+), 2 deletions(-)
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
index c9e87162cb..12e11250e1 100644
---
From: Hao Wu
This patch implements the basic registers of GMAC device. Actual network
communications are not supported yet.
Signed-off-by: Hao Wu
include/hw: Fix type problem in NPCMGMACState
- Fix type problem in NPCMGMACState
- Fix Register Initalization which was breaking boot-up in
From: Hao Wu
The PCI Mailbox Module is a high-bandwidth communcation module
between a Nuvoton BMC and CPU. It features 16KB RAM that are both
accessible by the BMC and core CPU. and supports interrupt for
both sides.
This patch implements the BMC side of the PCI mailbox module.
Communication
From: Nabih Estefan Diaz
- Created qtest to check initialization of registers in GMAC Module.
- Implemented test into Build File.
Signed-off-by: Nabih Estefan Diaz
---
tests/qtest/meson.build | 11 +-
tests/qtest/npcm_gmac-test.c | 209 +++
2 files
From: Nabih Estefan Diaz
- Implementation of Receive function for packets
- Implementation for reading and writing from and to descriptors in
memory for Rx
NOTE: At this point in development we believe this function is working
as intended, and the kernel supports these findings, but we need
From: Nabih Estefan Diaz
- Implementation of Transmit function for packets
- Implementation for reading and writing from and to descriptors in
memory for Tx
NOTE: This function implements the steps detailed in the datasheet for
transmitting messages from the GMAC.
Signed-off-by: Nabih
From: Hao Wu
This patches adds a qtest for NPCM7XX PCI Mailbox module.
It sends read and write requests to the module, and verifies that
the module contains the correct data after the requests.
Signed-off-by: Hao Wu
---
tests/qtest/meson.build | 1 +
From: Nabih Estefan Diaz
- Add PCS Register check to npcm_gmac-test
Signed-off-by: Nabih Estefan Diaz
---
tests/qtest/npcm_gmac-test.c | 134 ++-
1 file changed, 133 insertions(+), 1 deletion(-)
diff --git a/tests/qtest/npcm_gmac-test.c
From: Nabih Estefan Diaz
- Implemeted classes for GMAC Receive and Transmit Descriptors
- Implemented Masks for said descriptors
Signed-off-by: Nabih Estefan Diaz
---
hw/net/npcm_gmac.c | 183 +++
hw/net/trace-events | 9 ++
From: Nabih Estefan Diaz
[Changes since v2]
Fixed bugs related to the RC functionality of the GMAC. Added and
squashed patches related to that.
[Changes since v1]
Fixed some errors in formatting.
Fixed a merge error that I didn't see in v1.
Removed Nuvoton 8xx references since that is a separate
Peter Xu writes:
> It's possible that some errors can be overwritten with success retval later
> on, and then ignored. Always capture all errors and report.
>
> Reported by Coverity 1522861, but actually I spot one more in the same
> function.
>
> Fixes: CID 1522861
> Signed-off-by: Peter Xu
Wires up four I2C controller instances to the powernv10 chip
XSCOM address space.
Each controller instance is wired up to two I2C buses of
its own. No other I2C devices are connected to the buses
at this time.
Signed-off-by: Glenn Miles
---
Based-on:
the lack of
both zicntr and zihpm when running TCG, although attempting to use the
timers will result in SIGILL.
[1]
https://lore.kernel.org/qemu-riscv/20230717215419.124258-1-dbarb...@ventanamicro.com/
[2]
https://lore.kernel.org/qemu-riscv/20231017-e7a4712137165b59844499e3@orel/T
zihpm is the Hardware Performance Counters extension described in
chapter 12 of the unprivileged spec. It describes support for 29
unprivileged performance counters, hpmcounter3-hpmcounter31.
As with zicntr, QEMU already implements zihpm before it was even an
extension. zihpm is also part of the
zicntr is the Base Counters and Timers extension described in chapter 12
of the unprivileged spec. It describes support for RDCYCLE, RDTIME and
RDINSTRET.
QEMU already implements it way before it was a discrete extension.
zicntr is part of the RVA22 profile, so let's add it to QEMU to make the
Add zihpm support in the KVM driver now that QEMU supports it.
This reg was added in Linux 6.6.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/kvm/kvm-cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index
Support for the zicntr counters are already in place. We need a way to
disable them if the user wants to. This is done by restricting access to
the CYCLE, TIME, and INSTRET counters via the 'ctr()' predicate when
we're about to access them.
Disabling zicntr happens via the command line or if its
Add zicntr support in the KVM driver now that QEMU supports it.
This reg was added in Linux 6.6.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/kvm/kvm-cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index
Disabling ext_zihpm does nothing at this moment. Add support to disable
the hpmcounter3-hpmcounter31 counters if the user disables zihpm.
There is already code in place in target/riscv/csr.c in all predicates
for these counters (ctr() and mctr()) that disables them if
cpu->cfg.pmu_num is zero.
On Fri, Oct 13, 2023 at 10:56:31AM +0300, Emmanouil Pitsidianakis wrote:
> In preparation of raising -Wimplicit-fallthrough to 5, replace all
> fall-through comments with the fallthrough attribute pseudo-keyword.
>
> Signed-off-by: Emmanouil Pitsidianakis
> ---
> qapi/opts-visitor.c | 1
On Fri, Oct 13, 2023 at 10:56:29AM +0300, Emmanouil Pitsidianakis wrote:
> In preparation of raising -Wimplicit-fallthrough to 5, replace all
> fall-through comments with the fallthrough attribute pseudo-keyword.
>
> Signed-off-by: Emmanouil Pitsidianakis
> ---
> block/block-copy.c| 1 +
>
On Fri, Oct 13, 2023 at 10:56:28AM +0300, Emmanouil Pitsidianakis wrote:
> Signed-off-by: Emmanouil Pitsidianakis
The subject line gives the 'what', but the commit body is
conspicuously lacking on the 'why'.
> ---
> audio/pwaudio.c | 8
> hw/arm/smmuv3.c |
On Fri, Oct 13, 2023 at 10:56:27AM +0300, Emmanouil Pitsidianakis wrote:
> /* resubmitted because git-send-email crashed with previous attempt */
>
> Hello,
>
> This RFC is inspired by the kernel's move to -Wimplicit-fallthrough=3
> back in 2019.[0]
> We take one step (or two) further by
On Tue, 17 Oct 2023, Mark Cave-Ayland wrote:
On 16/10/2023 23:16, BALATON Zoltan wrote:
On Sun, 15 Oct 2023, Mark Cave-Ayland wrote:
On 14/10/2023 17:13, BALATON Zoltan wrote:
On Sat, 14 Oct 2023, Mark Cave-Ayland wrote:
Using the portio_list*() APIs really is the right way to implement this
On Tue, 2023-10-17 at 17:28 -0400, Michael S. Tsirkin wrote:
> On Tue, Oct 17, 2023 at 10:19:55PM +0100, David Woodhouse wrote:
> > On Wed, 2023-08-23 at 11:37 -0400, Peter Xu wrote:
> > > On Wed, Aug 23, 2023 at 01:23:25PM +0100, David Woodhouse wrote:
> > > > From: David Woodhouse
> > > >
> >
On Tue, Oct 17, 2023 at 10:19:55PM +0100, David Woodhouse wrote:
> On Wed, 2023-08-23 at 11:37 -0400, Peter Xu wrote:
> > On Wed, Aug 23, 2023 at 01:23:25PM +0100, David Woodhouse wrote:
> > > From: David Woodhouse
> > >
> > > A generic X86IOMMUClass->int_remap function should not return VT-d
>
On Wed, 2023-08-30 at 21:20 +0100, David Woodhouse wrote:
> From: David Woodhouse
>
> The interrupt from timer 0 in legacy mode is supposed to go to IRQ 0 on
> the i8259 and IRQ 2 on the I/O APIC. The generic x86 GSI handling can't
> cope with IRQ numbers differing between the two chips (despite
On Wed, 2023-08-23 at 11:37 -0400, Peter Xu wrote:
> On Wed, Aug 23, 2023 at 01:23:25PM +0100, David Woodhouse wrote:
> > From: David Woodhouse
> >
> > A generic X86IOMMUClass->int_remap function should not return VT-d
> > specific values; fix it to return 0 if the interrupt was successfully
> >
On 17/10/2023 07:11, Richard Henderson wrote:
While doing some other testing the other day, I noticed my sparc64
chroot running particularly slowly. I think I know what the problem
is there, but fixing that was going to be particularly ugly with the
existing sparc translator.
So I've
Juan Quintela wrote:
> Use blocked-mirror with NBD instead.
>
> Signed-off-by: Juan Quintela
> Acked-by: Stefan Hajnoczi
> Reviewed-by: Thomas Huth
> Reviewed-by: Markus Armbruster
Hi Kevin and Stefan
Can we change the iotest output to fix this?
On Tue, 2023-10-17 at 09:01 +0200, Cédric Le Goater wrote:
> On 10/17/23 00:20, Glenn Miles wrote:
> > Upstreams the PowerNV I2C controller model originally
> > authored by Cédric Le Goater with minor changes by
> > myself to split the actual addition of the model from
> > wiring it up to a power
On 10/17/23 22:21, BALATON Zoltan wrote:
On Tue, 17 Oct 2023, Helge Deller wrote:
On 10/17/23 21:19, BALATON Zoltan wrote:
On Tue, 17 Oct 2023, Helge Deller wrote:
On 10/17/23 18:13, BALATON Zoltan wrote:
On Tue, 17 Oct 2023, del...@kernel.org wrote:
From: Helge Deller
Signed-off-by:
It's possible that some errors can be overwritten with success retval later
on, and then ignored. Always capture all errors and report.
Reported by Coverity 1522861, but actually I spot one more in the same
function.
Fixes: CID 1522861
Signed-off-by: Peter Xu
---
migration/ram.c | 6 --
1
From: Fabiano Rosas
To do so, create two paired sockets, but make them not providing real data.
Feed those fake sockets to src/dst QEMUs for recovery to let them go into
RECOVER stage without going out. Test that we can always kick it out and
recover again with the right ports.
This patch is
rp_state.error was a boolean used to show error happened in return path
thread. That's not only duplicating error reporting (migrate_set_error),
but also not good enough in that we only do error_report() and set it to
true, we never can keep a history of the exact error and show it in
After we have errp which contains the more detailed error message, make
ram_save_queue_pages() returns bool in its stack.
Signed-off-by: Peter Xu
---
migration/ram.h | 4 ++--
migration/migration.c | 16
migration/ram.c | 18 +-
3 files changed, 19
Use the FIELD macro to describe the PHYMNTNC register fields.
Signed-off-by: Luc Michel
---
hw/net/cadence_gem.c | 27 ++-
1 file changed, 14 insertions(+), 13 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 955a8da134..4c5fe10316 100644
---
Describe screening registers fields using the FIELD macros.
Signed-off-by: Luc Michel
---
hw/net/cadence_gem.c | 92 ++--
1 file changed, 47 insertions(+), 45 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index
Use the FIELD macro to describe the NWCTRL register fields.
Signed-off-by: Luc Michel
---
hw/net/cadence_gem.c | 53 +---
1 file changed, 40 insertions(+), 13 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index
Use the FIELD macro to describe the DESCONF6 register fields.
Signed-off-by: Luc Michel
---
hw/net/cadence_gem.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 6d084a3b31..955a8da134 100644
--- a/hw/net/cadence_gem.c
+++
Use de FIELD macro to describe the NWCFG register fields.
Signed-off-by: Luc Michel
---
hw/net/cadence_gem.c | 60
1 file changed, 39 insertions(+), 21 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index
Hi,
This series brings small changes to the Cadence GEM Ethernet model.
There is (almost) no behaviour change.
Patches 1 to 9 replace handcrafted defines with the use of REG32 and
FIELDS macros for register and fields declarations.
Patch 10 fixes PHY accesses so that they are done only on a
Normally the postcopy recover phase should only exist for a super short
period, that's the duration when QEMU is trying to recover from an
interrupted postcopy migration, during which handshake will be carried out
for continuing the procedure with state changes from PAUSED -> RECOVER ->
v4:
- Some patches merged, reposting the rest patches
- Fixed a bug in the new test case reported by Fabiano
- Try to keep close_return_path_on_source() return a value (even though it
still fetches from migrate_has_error)
- Two more patches added to cleanup retval of rp thread functions
v1:
The CRC was stored in an unsigned variable in gem_receive. Change it for
a uint32_t to ensure we have the correct variable size here.
Signed-off-by: Luc Michel
---
hw/net/cadence_gem.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/net/cadence_gem.c
Use de FIELD macro to describe the DMACFG register fields.
Signed-off-by: Luc Michel
---
hw/net/cadence_gem.c | 48
1 file changed, 31 insertions(+), 17 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index
Now we have a Error** passed into the return path thread stack, which is
even clearer than an int retval. Change ram_dirty_bitmap_reload() and the
callers to use a bool instead to replace errnos.
Suggested-by: Philippe Mathieu-Daudé
Signed-off-by: Peter Xu
---
migration/ram.h | 2 +-
The MDIO access is done only on a write to the PHYMNTNC register. A
subsequent read is used to retrieve the result but does not trigger an
MDIO access by itself.
Refactor the PHY access logic to perform all accesses (MDIO reads and
writes) at PHYMNTNC write time.
Signed-off-by: Luc Michel
---
Use de FIELD macro to describe the IRQ related register fields.
Signed-off-by: Luc Michel
---
hw/net/cadence_gem.c | 51 +---
1 file changed, 39 insertions(+), 12 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index
Use de FIELD macro to describe the TXSTATUS and RXSTATUS register
fields.
Signed-off-by: Luc Michel
---
hw/net/cadence_gem.c | 34 +-
1 file changed, 25 insertions(+), 9 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index
Replace register defines with the REG32 macro from registerfields.h in
the Cadence GEM device.
Signed-off-by: Luc Michel
---
hw/net/cadence_gem.c | 527 +--
1 file changed, 261 insertions(+), 266 deletions(-)
diff --git a/hw/net/cadence_gem.c
On 17/10/2023 16:19, Thomas Huth wrote:
hw/input/lasips2.c and the corresponding header include/hw/input/lasips2.h
are only used by the HPPA machine, so add them to the corresponding section
in the MAINTAINERS file.
Signed-off-by: Thomas Huth
---
MAINTAINERS | 2 ++
1 file changed, 2
On Tue, 17 Oct 2023, Helge Deller wrote:
On 10/17/23 21:19, BALATON Zoltan wrote:
On Tue, 17 Oct 2023, Helge Deller wrote:
On 10/17/23 18:13, BALATON Zoltan wrote:
On Tue, 17 Oct 2023, del...@kernel.org wrote:
From: Helge Deller
Signed-off-by: Helge Deller
---
hw/net/tulip.c | 2
On 17/10/2023 15:01, Philippe Mathieu-Daudé wrote:
Pull the 'dma' property to the core XHCI type, declare
its link statically using DEFINE_PROP_LINK().
Signed-off-by: Philippe Mathieu-Daudé
---
hw/usb/hcd-xhci-sysbus.c | 4
hw/usb/hcd-xhci.c| 2 ++
2 files changed, 2
On 17/10/2023 15:01, Philippe Mathieu-Daudé wrote:
Declare link statically using DEFINE_PROP_LINK().
Signed-off-by: Philippe Mathieu-Daudé
---
hw/net/cadence_gem.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index
On 17/10/2023 15:01, Philippe Mathieu-Daudé wrote:
Declare link statically using DEFINE_PROP_LINK().
Signed-off-by: Philippe Mathieu-Daudé
---
hw/dma/xilinx_axidma.c | 6 ++
hw/dma/xlnx-zdma.c | 7 ++-
hw/dma/xlnx_csu_dma.c | 13 -
3 files changed, 8
On 21.04.23 00:52, Alexander Graf wrote:
Hvf on x86 only supported 2MiB large pages, but never bothered to strip
out the 1GiB page size capability from -cpu host. With QEMU 8.0.0 this
became a problem because OVMF started to use 1GiB pages by default.
Let's just unconditionally add 1GiB page
On 17/10/2023 15:01, Philippe Mathieu-Daudé wrote:
Access QOM parent with the proper QOM VIRTIO_SCSI_COMMON() macro.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/scsi/virtio-scsi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/scsi/virtio-scsi.c
On 17/10/2023 15:01, Philippe Mathieu-Daudé wrote:
Access QOM parent with the proper QOM VIRTIO_DEVICE() macro.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/display/virtio-gpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/display/virtio-gpu.c
On 17/10/2023 15:01, Philippe Mathieu-Daudé wrote:
Access QOM parent with the proper QOM [VIRTIO_]DEVICE() macros.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/block/vhost-user-blk.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/block/vhost-user-blk.c
Am 19.09.2023 um 18:57 hat Andrey Drobyshev geschrieben:
> v2 --> v3:
> * Patch 3/8: fixed logic in the if statement, so that we align on blk
>when blk_old_backing == NULL;
> * Patch 4/8: comment fix;
> * Patch 5/8: comment fix; dropped redundant "if (blk_new_backing)"
>statements.
>
>
On 17/10/2023 14:50, Philippe Mathieu-Daudé wrote:
pcspk_init() is a legacy init function, inline and remove it.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/audio/pcspk.h | 10 --
hw/i386/pc.c | 3 ++-
hw/isa/i82378.c | 5 -
hw/mips/jazz.c
On 17/10/2023 14:12, Philippe Mathieu-Daudé wrote:
Access to QemuInputHandlerState::handler are read-only.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/virtio/virtio-input.h | 2 +-
include/ui/input.h | 2 +-
chardev/msmouse.c| 2 +-
On 16/10/2023 23:16, BALATON Zoltan wrote:
On Sun, 15 Oct 2023, Mark Cave-Ayland wrote:
On 14/10/2023 17:13, BALATON Zoltan wrote:
On Sat, 14 Oct 2023, Mark Cave-Ayland wrote:
On 09/10/2023 20:54, BALATON Zoltan wrote:
The initial value for BARs were set in reset method for emulating
legacy
On 2023/10/17 23:05, Fabiano Rosas wrote:
Alex Bennée writes:
From: Akihiko Odaki
An array is a more appropriate data structure than a list for gdb_regs
since it is initialized only with append operation and read-only after
initialization.
Signed-off-by: Akihiko Odaki
Reviewed-by:
Signed-off-by: Tong Ho
---
tests/qtest/meson.build | 2 +-
tests/qtest/xlnx-versal-trng-test.c | 486
2 files changed, 487 insertions(+), 1 deletion(-)
create mode 100644 tests/qtest/xlnx-versal-trng-test.c
diff --git a/tests/qtest/meson.build
This series adds support for the True Random Number Generator
(TRNG) in the AMD/Xilinx Versal family of devices.
The series starts by introducing a non-cryptographic grade model
of the TRNG controller in the Versal family of devices, followed
by instantiating the model in Xilinx Versal machine.
This adds a non-cryptographic grade implementation of the
model for the True Random Number Generator (TRNG) component
in AMD/Xilinx Versal device family.
This implements all 3 modes defined by the actual hardware
specs, all of which selectable by guest software at will
at anytime:
1) PRNG mode,
Connect the support for Versal True Random Number Generator
(TRNG) device.
Warning: unlike the TRNG component in a real device from the
Versal device familiy, the connected TRNG model is not of
cryptographic grade and is not intended for use cases when
cryptograpically strong TRNG is needed.
1 - 100 of 553 matches
Mail list logo
