Signed-off-by: Joelle van Dyne
---
hw/loongarch/virt.c | 7 +++
hw/loongarch/Kconfig | 1 +
2 files changed, 8 insertions(+)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index 4b7dc67a2d..feed0f8bbf 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -1004,6 +1004,13 @@
On Apple Silicon, when Windows performs a LDP on the CRB MMIO space,
the exception is not decoded by hardware and we cannot trap the MMIO
read. This led to the idea from @agraf to use the same mapping type as
ROM devices: namely that reads should be seen as memory type and
writes should trap as MMI
This SysBus variant of the CRB interface supports dynamically locating
the MMIO interface so that Virt machines can use it. This interface
is currently the only one supported by QEMU that works on Windows 11
ARM64 as 'tpm-tis-device' does not work with current Windows drivers.
We largely follow tha
- Factor out common test code from tpm-crb-test.c -> tpm-tests.c
- Store device addr in `tpm_device_base_addr` (unify with TIS tests)
- Add new tests for aarch64
Signed-off-by: Joelle van Dyne
---
tests/qtest/tpm-tests.h | 2 +
tests/qtest/tpm-util.h | 4 +-
Signed-off-by: Joelle van Dyne
---
tests/qtest/bios-tables-test-allowed-diff.h | 4
tests/data/acpi/q35/DSDT.crb.tpm2 | Bin 0 -> 8981 bytes
tests/data/acpi/q35/TPM2.crb.tpm2 | Bin 0 -> 76 bytes
tests/data/acpi/virt/DSDT.crb-device.tpm2 | Bin 0 -> 5276 bytes
tests/d
The register is actually 64-bits but in order to make this more clear
than the specification, we define two 32-bit registers:
CTRL_RSP_LADDR and CTRL_RSP_HADDR to match the CTRL_CMD_* naming. This
deviates from the specs but is way more clear.
Previously, the only CRB device uses a fixed system ad
The impetus for this patch set is to get TPM 2.0 working on Windows 11 ARM64.
Windows' tpm.sys does not seem to work on a TPM TIS device (as verified with
VMWare's implementation). However, the current TPM CRB device uses a fixed
system bus address that is reserved for RAM in ARM64 Virt machines.
Signed-off-by: Joelle van Dyne
---
tests/qtest/bios-tables-test-allowed-diff.h | 4
tests/data/acpi/q35/DSDT.crb.tpm2 | 0
tests/data/acpi/q35/TPM2.crb.tpm2 | 0
tests/data/acpi/virt/DSDT.crb-device.tpm2 | 0
tests/data/acpi/virt/TPM2.crb-device.tpm2 | 0
5 files chan
This reduces redundent code in different machine types with ACPI table
generation. Additionally, this will allow us to support different TPM
interfaces with the same AML logic. Finally, this matches up with the
TPM TIS ISA implementation.
Ideally, we would be able to call `qbus_build_aml` and avoi
In preparation for the SysBus variant, we move common code styled
after the TPM TIS devices.
To maintain compatibility, we do not rename the existing tpm-crb
device.
Signed-off-by: Joelle van Dyne
Reviewed-by: Stefan Berger
---
docs/specs/tpm.rst | 1 +
hw/tpm/tpm_crb.h| 76 +++
This logic is similar to TPM TIS ISA device. Since TPM CRB can only
support TPM 2.0 backends, we check for this in realize.
Signed-off-by: Joelle van Dyne
Reviewed-by: Stefan Berger
---
hw/tpm/tpm_crb.h| 2 ++
hw/i386/acpi-build.c| 23 ---
hw/tpm/tpm_crb.c
Instead of calling `memory_region_add_subregion` directly, we defer to
the caller to do it. This allows us to re-use the code for a SysBus
device.
Signed-off-by: Joelle van Dyne
Reviewed-by: Stefan Berger
---
hw/tpm/tpm_ppi.h| 10 +++---
hw/tpm/tpm_crb.c| 4 ++--
hw/tpm/tpm
TPM needs to know its own base address in order to generate its DSDT
device entry.
Signed-off-by: Joelle van Dyne
---
include/sysemu/tpm.h | 4
hw/tpm/tpm-sysbus.c | 33 +
hw/tpm/meson.build | 1 +
3 files changed, 38 insertions(+)
create mode 100644 hw
Signed-off-by: Joelle van Dyne
---
hw/arm/virt.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 529f1c089c..f1a161b0ea 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -2806,6 +2806,13 @@ static void virt_machine_device_plug_cb(HotplugHandler
*hot
Signed-off-by: Joelle van Dyne
---
tests/qtest/bios-tables-test.c | 43 --
1 file changed, 41 insertions(+), 2 deletions(-)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index 9f4bc15aab..c63bad0205 100644
--- a/tests/qtest/bios-tabl
On Mon, Jul 17, 2023 at 7:23 AM Igor Mammedov wrote:
>
> On Fri, 14 Jul 2023 00:09:26 -0700
> Joelle van Dyne wrote:
>
> > This SysBus variant of the CRB interface supports dynamically locating
> > the MMIO interface so that Virt machines can use it. This interface
> > is currently the only one s
Am 29. Oktober 2023 00:07:00 UTC schrieb BALATON Zoltan :
>On Sat, 28 Oct 2023, Bernhard Beschow wrote:
>> acpi_update_sci() covers everything pm_update_sci() does. It implements
>> common
>> ACPI funtionality in a generic fashion. Note that it agnostic to any
>> Frankenstein usage of the gener
Am 28. Oktober 2023 17:47:15 UTC schrieb BALATON Zoltan :
>On Sat, 28 Oct 2023, Bernhard Beschow wrote:
>> Am 28. Oktober 2023 12:58:32 UTC schrieb BALATON Zoltan :
>>> Hello,
>>>
>>> On Sat, 28 Oct 2023, Bernhard Beschow wrote:
This series is part of my work to bring the VIA south bridges
The CSR register mseccfg is used by multiple extensions: Smepm and Zkr.
Consider this when checking the existence of the register.
Fixes: 77442380ecbe ("target/riscv: rvk: add CSR support for Zkr")
Signed-off-by: Heinrich Schuchardt
---
target/riscv/csr.c | 7 +--
1 file changed, 5 insertio
On Sat, 28 Oct 2023, Bernhard Beschow wrote:
acpi_update_sci() covers everything pm_update_sci() does. It implements common
ACPI funtionality in a generic fashion. Note that it agnostic to any
Frankenstein usage of the general purpose event registers in other device
models. It just implements a g
On Sat, 28 Oct 2023, BALATON Zoltan wrote:
On Sat, 28 Oct 2023, Bernhard Beschow wrote:
Am 28. Oktober 2023 12:58:32 UTC schrieb BALATON Zoltan
:
Hello,
On Sat, 28 Oct 2023, Bernhard Beschow wrote:
This series is part of my work to bring the VIA south bridges to the PC
machine
[1]. It implem
The chip has 4 pins (called PIRQA-D in VT82C686B and PINTA-D in
VT8231) that are meant to be connected to PCI IRQ lines and allow
routing PCI interrupts to the ISA PIC. Route these in
via_isa_set_irq() to make it possible to share them with internal
functions that can also be routed to the same ISA
This device is part of a superio/ISA bridge chip and IRQs from it are
routed to an ISA interrupt. Use via_isa_set_irq() function to implement
this in a vt82c686-uhci-pci specific irq handler.
This reverts commit 422a6e8075752bc5342afd3eace23a4990dd7d98.
Signed-off-by: BALATON Zoltan
---
hw/usb/
Signed-off-by: BALATON Zoltan
---
hw/audio/via-ac97.c | 8
hw/isa/vt82c686.c | 1 +
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/hw/audio/via-ac97.c b/hw/audio/via-ac97.c
index 30095a4c7a..4c127a1def 100644
--- a/hw/audio/via-ac97.c
+++ b/hw/audio/via-ac97.c
@@ -211,1
The VIA intergrated south bridge chips combine several functions and
allow routing their interrupts to any of the ISA IRQs (also allowing
multiple components to share the same ISA IRQ, e.g. pegasos2 firmware
configures USB, sound and PCI to use IRQ 9). Bring back
via_isa_set_irq() that takes the co
This is going back to my otiginal proposal in
https://patchew.org/QEMU/cover.1677004414.git.bala...@eik.bme.hu/
implementing routing of interrupts from device functions and PCI
devices to ISA interrupts. On pegasos2 the firmware sets evertyhing to
share IRQ 9 so the current simpified version worked
On 10/9/23 20:36, Song Gao wrote:
Signed-off-by: Song Gao
---
target/loongarch/insn_trans/trans_vec.c.inc | 12
target/loongarch/internals.h| 2 ++
2 files changed, 14 insertions(+)
diff --git a/target/loongarch/insn_trans/trans_vec.c.inc
b/target/loongarch/in
On 10/9/23 20:37, Song Gao wrote:
Signed-off-by: Song Gao
---
linux-user/loongarch64/signal.c | 107 ++--
1 file changed, 87 insertions(+), 20 deletions(-)
diff --git a/linux-user/loongarch64/signal.c b/linux-user/loongarch64/signal.c
index 277e9f5757..4b09e50a5f
On 10/9/23 20:36, Song Gao wrote:
See:
https://github.com/torvalds/linux/blob/master/arch/loongarch/kernel/signal.c
The kernel setup_sigcontext() set end context size 0.
Signed-off-by: Song Gao
---
linux-user/loongarch64/signal.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Re
On 10/9/23 20:36, Song Gao wrote:
See:
https://github.com/torvalds/linux/blob/master/arch/loongarch/kernel/signal.c
The alloc size is sizeof(struct target_fpu_context).
Signed-off-by: Song Gao
---
linux-user/loongarch64/signal.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Revi
Signed-off-by: Richard Henderson
---
target/alpha/translate.c | 39 ---
1 file changed, 16 insertions(+), 23 deletions(-)
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index 32333081d8..49e6a7b62d 100644
--- a/target/alpha/translate.c
+++ b/
Merge tcg_out_testi into tcg_out_cmp and adjust the two uses.
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.c.inc | 83 ++-
1 file changed, 47 insertions(+), 36 deletions(-)
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 7
... and the inverse, CBZ for TSTEQ.
Suggested-by: Paolo Bonzini
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c.inc | 8
1 file changed, 8 insertions(+)
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index 55225313ad..0c98c48f68 100644
--- a/tcg
Signed-off-by: Richard Henderson
---
tcg/sparc64/tcg-target.c.inc | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc
index 10fb8a1a0d..176c98740b 100644
--- a/tcg/sparc64/tcg-target.c.inc
+++ b/tcg/spar
Signed-off-by: Richard Henderson
---
target/m68k/translate.c | 74 ++---
1 file changed, 33 insertions(+), 41 deletions(-)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index 4a0b0b2703..f30b92f2d4 100644
--- a/target/m68k/translate.c
+++ b/ta
Signed-off-by: Richard Henderson
---
tcg/s390x/tcg-target.c.inc | 139 +
1 file changed, 96 insertions(+), 43 deletions(-)
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
index 86ec737768..cb1693c9cf 100644
--- a/tcg/s390x/tcg-target.c.inc
Better constraint for tcg_out_cmp, based on the comparison.
We can't yet remove the fallback to load constants into a
scratch because of tcg_out_cmp2, but that path should not
be as frequent.
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target-con-set.h | 5 ++--
tcg/ppc/tcg-target-con-str.
Signed-off-by: Richard Henderson
---
tcg/sparc64/tcg-target.c.inc | 21 +++--
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc
index e16b25e309..10fb8a1a0d 100644
--- a/tcg/sparc64/tcg-target.c.inc
+++ b/tc
Use a non-zero value here (an illegal encoding) as a better
condition than is_unsigned_cond for when MOVR/BPR is usable.
Signed-off-by: Richard Henderson
---
tcg/sparc64/tcg-target.c.inc | 25 ++---
1 file changed, 14 insertions(+), 11 deletions(-)
diff --git a/tcg/sparc64/t
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.c.inc | 59 ++--
1 file changed, 44 insertions(+), 15 deletions(-)
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index 0c29a3929b..0fc7273b16 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b
Signed-off-by: Richard Henderson
---
tcg/tci.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/tcg/tci.c b/tcg/tci.c
index 4640902c88..5e1c4a491d 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -228,6 +228,12 @@ static bool tci_compare32(uint32_t u0, uint32_t u1,
TCGCond condition)
Return the x86 condition codes to use after the compare.
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.c.inc | 24 +---
1 file changed, 13 insertions(+), 11 deletions(-)
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 8b1baa8206..7d5ed0d04
Better constraint for tcg_out_cmp, based on the comparison.
Signed-off-by: Richard Henderson
---
tcg/s390x/tcg-target-con-set.h | 6 +--
tcg/s390x/tcg-target-con-str.h | 1 +
tcg/s390x/tcg-target.c.inc | 72 +-
3 files changed, 58 insertions(+), 21 deletions
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 56 ++--
1 file changed, 38 insertions(+), 18 deletions(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index 384d2ba342..7770e1bfa0 100644
--- a/tcg/loongarch6
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target.c.inc | 41 +++
1 file changed, 41 insertions(+)
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index 35eff82bb3..f5680d7b89 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-
Signed 33-bit == signed 32-bit + unsigned 32-bit.
Signed-off-by: Richard Henderson
---
tcg/s390x/tcg-target-con-set.h | 8
tcg/s390x/tcg-target-con-str.h | 2 +-
tcg/s390x/tcg-target.c.inc | 36 +-
3 files changed, 23 insertions(+), 23 deletions(-)
Test the sign bit for LT/GE vs 0, and TSTNE/EQ vs a power of 2.
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c.inc | 100 ---
1 file changed, 81 insertions(+), 19 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
Hoist the tcg_cond_to_jcc index outside the function.
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.c.inc | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index eeb23d3fca..8b1baa8206 100644
---
Build fix for missing symbol.
Cc: qemu-sta...@nongnu.org
Fixes: b8b94ac6753 ("tcg: Split out tcg_out_extrl_i64_i32")
Signed-off-by: Richard Henderson
---
tcg/sparc64/tcg-target.c.inc | 5 +
1 file changed, 5 insertions(+)
diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.
Use "test x,x" when the bit is one of the 4 sign bits.
Use "bt imm,x" otherwise.
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target-con-set.h | 6 ++--
tcg/i386/tcg-target-con-str.h | 1 +
tcg/i386/tcg-target.c.inc | 56 ---
3 files changed, 56 inserti
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.c.inc | 105 ---
1 file changed, 98 insertions(+), 7 deletions(-)
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index b20dbe036d..ef1d959892 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/
Signed-off-by: Richard Henderson
---
target/alpha/translate.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index 49e6a7b62d..c7daf46de7 100644
--- a/target/alpha/translate.c
+++ b/target/alpha/translate.c
@@ -1676,
Using cr0 means we could choose to use rc=1 to compute the condition.
Adjust the tables and tcg_out_cmp that feeds them.
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.c.inc | 68
1 file changed, 34 insertions(+), 34 deletions(-)
diff --git a/tc
Rename the current tcg_out_bc function to tcg_out_bc_lab, and
create a new function that takes an integer displacement + link.
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.c.inc | 28 +---
1 file changed, 17 insertions(+), 11 deletions(-)
diff --git a/tcg/ppc/
Fold constant comparisons.
Canonicalize "tst x,x" to equality vs zero.
Canonicalize "tst x,sign" to sign test vs zero.
Fold double-word comparisons with zero parts.
Fold setcond of "tst x,pow2" to a bit extract.
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 245 ++
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target-con-set.h | 5 +--
tcg/aarch64/tcg-target-con-str.h | 1 +
tcg/aarch64/tcg-target.c.inc | 56 ++--
3 files changed, 43 insertions(+), 19 deletions(-)
diff --git a/tcg/aarch64/tcg-target-con-set.h b/tcg/
Signed-off-by: Richard Henderson
---
tcg/riscv/tcg-target.c.inc | 20 ++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index 639363039b..358579b3fd 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tc
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.c.inc | 27 ---
1 file changed, 16 insertions(+), 11 deletions(-)
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index 1ac11acc7c..13d43ef9ba 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-
Add the enumerators, adjust the helpers to match, and dump.
Not supported anywhere else just yet.
Signed-off-by: Richard Henderson
---
docs/devel/tcg-ops.rst | 2 ++
include/tcg/tcg-cond.h | 49 --
tcg/tcg.c | 4 +++-
3 files changed, 43 ins
Mirror the new do_constant_folding_cond1 by doing all
argument and condition adjustment within one helper.
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 107 ++---
1 file changed, 57 insertions(+), 50 deletions(-)
diff --git a/tcg/optimize.c b
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 38 +++---
1 file changed, 23 insertions(+), 15 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 2db5177c32..e8a13fedb5 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -112,11 +112,22 @@ stat
Signed-off-by: Richard Henderson
---
target/alpha/translate.c | 49 +++-
1 file changed, 23 insertions(+), 26 deletions(-)
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index c7daf46de7..c68c2bcd21 100644
--- a/target/alpha/translate.c
+++ b
Fixes a bug wherein raw uses of tcg_constant_internal
do not have their TempOptInfo initialized.
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 29 ++---
1 file changed, 18 insertions(+), 11 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 76be0fc33
Handle modifications to the arguments and condition
in a single place.
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 57 --
1 file changed, 27 insertions(+), 30 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index e8a13fedb5..89
Fill the new argument from any condition within the opcode.
Not yet used within any backend.
Signed-off-by: Richard Henderson
---
tcg/tcg.c| 34 ++--
tcg/aarch64/tcg-target.c.inc | 3 ++-
tcg/arm/tcg-target.c.inc | 3 ++-
tcg/i386
Expose a pair of comparison operators that map to the "test"
comparison that is available on many architectures.
Changes for v2:
* Add TCGCond to tcg_target_const_match.
This fixes a long-standing issue with ppc and s390x backends,
in that CMPI for signed comparisons has signed immediate
On 10/28/23 03:33, Alex Bennée wrote:
From: Matheus Tavares Bernardino
We duplicate "cmd" as strtok may modify its argument, but we forgot
to free it later. Furthermore, add_semihosting_arg doesn't take
responsibility for this memory either (it strdup's the argument).
Signed-off-by: Matheus Ta
On 10/28/23 03:33, Alex Bennée wrote:
From: Akihiko Odaki
cpu->gdb_regs may be NULL if no coprocessor is registered.
Fixes: 73c392c26b ("gdbstub: Replace gdb_regs with an array")
Signed-off-by: Akihiko Odaki
Message-Id: <20231019101030.128431-2-akihiko.od...@daynix.com>
Signed-off-by: Alex Be
On 10/28/23 03:33, Alex Bennée wrote:
This requires a few more tweaks than usual as:
- the default sources format has changed
- bring in python3-tomli from the repos
- split base install from cross compilers
- also include libclang-rt-dev for sanitiser builds
Signed-off-by: Alex Ben
On 10/28/23 03:33, Alex Bennée wrote:
Maintaining two sets of containers for test building is silly. While
it makes sense for the QEMU cross-compile targets to have their own
fat containers built by lcitool we might as well merge the other
random debian based compilers into the same one used on g
On 10/28/23 03:33, Alex Bennée wrote:
Maintaining two sets of containers for test building is silly. While
it makes sense for the QEMU cross-compile targets to have their own
fat containers built by lcitool we might as well merge the other
random debian based compilers into the same one used on g
On 10/28/23 03:33, Alex Bennée wrote:
Maintaining two sets of containers for test building is silly. While
it makes sense for the QEMU cross-compile targets to have their own
fat containers built by lcitool we might as well merge the other
random debian based compilers into the same one used on g
On 10/28/23 03:33, Alex Bennée wrote:
Maintaining two sets of containers for test building is silly. While
it makes sense for the QEMU cross-compile targets to have their own
fat containers built by lcitool we might as well merge the other
random debian based compilers into the same one used on g
On 10/28/23 03:33, Alex Bennée wrote:
Maintaining two sets of containers for test building is silly. While
it makes sense for the QEMU cross-compile targets to have their own
fat containers built by lcitool we might as well merge the other
random debian based compilers into the same one used on g
On 10/28/23 03:33, Alex Bennée wrote:
Maintaining two sets of containers for test building is silly. While
it makes sense for the QEMU cross-compile targets to have their own
fat containers built by lcitool we might as well merge the other
random debian based compilers into the same one used on g
On 10/28/23 03:33, Alex Bennée wrote:
Maintaining two sets of containers for test building is silly. While
it makes sense for the QEMU cross-compile targets to have their own
fat containers built by lcitool we might as well merge the other
random debian based compilers into the same one used on g
On 10/28/23 03:32, Alex Bennée wrote:
diff --git a/.gitlab-ci.d/buildtest.yml b/.gitlab-ci.d/buildtest.yml
index d670fb42b9..983c95e785 100644
--- a/.gitlab-ci.d/buildtest.yml
+++ b/.gitlab-ci.d/buildtest.yml
@@ -276,7 +276,7 @@ build-user-legacy:
job: amd64-debian-legacy-cross-container
On 10/28/23 03:32, Alex Bennée wrote:
Maintaining two sets of containers for test building is silly. While
it makes sense for the QEMU cross-compile targets to have their own
fat containers built by lcitool we might as well merge the other
random debian based compilers into the same one used on g
On 10/28/23 03:32, Alex Bennée wrote:
@@ -278,6 +291,7 @@ build-user-hexagon:
MAKE_CHECK_ARGS: check-tcg
# Only build the softmmu targets we have check-tcg tests for
+# (skip alpha due to missing compilers, others need their own containers)
build-some-softmmu:
extends: .native_b
On 10/28/23 03:32, Alex Bennée wrote:
From: Akihiko Odaki
A build of GCC 13.2 will have stack protector enabled by default if it
was configured with --enable-default-ssp option. For such a compiler,
it is necessary to explicitly disable stack protector when linking
without standard libraries.
On Sat, 28 Oct 2023, Bernhard Beschow wrote:
Am 27. Oktober 2023 11:54:48 UTC schrieb BALATON Zoltan :
Changes in v7:
- Increase default memory size to 512m to match pegasos2 and sam460ex
and it's a better default for AmigaOS
Changes in v6:
- Dropped patch 1, now it's
Based-on: <20231024224056
On 10/28/23 03:33, Alex Bennée wrote:
From: Akihiko Odaki
copy_call() has an unused parameter so remove it.
Signed-off-by: Akihiko Odaki
Message-Id: <20231019101030.128431-7-akihiko.od...@daynix.com>
Reviewed-by: Richard Henderson
r~
On Sat, 28 Oct 2023, Bernhard Beschow wrote:
Am 28. Oktober 2023 13:03:41 UTC schrieb BALATON Zoltan :
On Sat, 28 Oct 2023, Bernhard Beschow wrote:
If enabled, SMIs can be triggered via software by writing to an IO-mapped port.
SMIs usually trigger execution of BIOS code. If appropriate values
On 10/28/23 06:49, Andrew Jones wrote:
On Sat, Oct 28, 2023 at 05:54:16AM -0300, Daniel Henrique Barboza wrote:
QEMU already implements zicbom (Cache Block Management Operations) and
zicboz (Cache Block Zero Operations). Commit 59cb29d6a5 ("target/riscv:
add Zicbop cbo.prefetch{i, r, m} place
Am 28. Oktober 2023 13:03:41 UTC schrieb BALATON Zoltan :
>On Sat, 28 Oct 2023, Bernhard Beschow wrote:
>> If enabled, SMIs can be triggered via software by writing to an IO-mapped
>> port.
>> SMIs usually trigger execution of BIOS code. If appropriate values are
>> written
>> to the port, the
Am 28. Oktober 2023 12:59:56 UTC schrieb BALATON Zoltan :
>On Sat, 28 Oct 2023, Bernhard Beschow wrote:
>> acpi_update_sci() covers everything pm_update_sci() does. It implements
>> common
>> ACPI funtionality in a generic fashion. Note that it agnostic to any
>> Frankenstein usage of the gener
Am 28. Oktober 2023 12:58:32 UTC schrieb BALATON Zoltan :
>Hello,
>
>On Sat, 28 Oct 2023, Bernhard Beschow wrote:
>> This series is part of my work to bring the VIA south bridges to the PC
>> machine
>> [1]. It implements missing ACPI functionality which ACPI-aware x86 guests
>> expect for a sm
Am 27. Oktober 2023 11:54:48 UTC schrieb BALATON Zoltan :
>Changes in v7:
>- Increase default memory size to 512m to match pegasos2 and sam460ex
>and it's a better default for AmigaOS
>
>Changes in v6:
>- Dropped patch 1, now it's
>
>Based-on: <20231024224056.842607-1-mark.cave-ayl...@ilande.co.
On 2023/10/26 14:54, gaosong wrote:
在 2023/10/26 上午9:38, Jiajie Chen 写道:
On 2023/10/26 03:04, Richard Henderson wrote:
On 10/25/23 10:13, Jiajie Chen wrote:
On 2023/10/24 07:26, Richard Henderson wrote:
See target/arm/tcg/translate-a64.c, gen_store_exclusive,
TCGv_i128 block.
See target/p
On Sat, 28 Oct 2023, Bernhard Beschow wrote:
If enabled, SMIs can be triggered via software by writing to an IO-mapped port.
SMIs usually trigger execution of BIOS code. If appropriate values are written
to the port, the BIOS transitions the system into or out of ACPI mode.
Note that APMState im
On Sat, 28 Oct 2023, Bernhard Beschow wrote:
acpi_update_sci() covers everything pm_update_sci() does. It implements common
ACPI funtionality in a generic fashion. Note that it agnostic to any
Frankenstein usage of the general purpose event registers in other device
models. It just implements a g
Hello,
On Sat, 28 Oct 2023, Bernhard Beschow wrote:
This series is part of my work to bring the VIA south bridges to the PC machine
[1]. It implements missing ACPI functionality which ACPI-aware x86 guests
expect for a smooth experience. The implementation is heavily inspired by PIIX4.
I think
Tracing the host pointer of the accessed MemoryRegion seems to be a debug
feature for developing QEMU itself. When analyzing guest behavior by comparing
traces, these pointers generate a lot of noise since the pointers differ between
QEMU invocations, making this task harder than it needs to be. Mo
Signed-off-by: Bernhard Beschow
---
hw/misc/imx7_snvs.c | 5 +
hw/misc/trace-events | 4
2 files changed, 9 insertions(+)
diff --git a/hw/misc/imx7_snvs.c b/hw/misc/imx7_snvs.c
index ee7698bd9c..a245f96cd4 100644
--- a/hw/misc/imx7_snvs.c
+++ b/hw/misc/imx7_snvs.c
@@ -16,9 +16,12 @@
#
Let the trace messages slightly deviate from the function names
("smb" -> "smbus") being traced in order to avoid conflights with the SMB
protocol.
Signed-off-by: Bernhard Beschow
---
hw/i2c/pm_smbus.c | 18 --
hw/i2c/trace-events | 6 ++
2 files changed, 10 insertions(+),
Signed-off-by: Bernhard Beschow
---
hw/watchdog/wdt_imx2.c | 24 ++--
hw/watchdog/trace-events | 4
2 files changed, 22 insertions(+), 6 deletions(-)
diff --git a/hw/watchdog/wdt_imx2.c b/hw/watchdog/wdt_imx2.c
index e776a2fbd4..885ebd3978 100644
--- a/hw/watchdog/wdt
Signed-off-by: Bernhard Beschow
---
hw/misc/imx6_ccm.c | 41 ++---
hw/misc/trace-events | 15 +++
2 files changed, 29 insertions(+), 27 deletions(-)
diff --git a/hw/misc/imx6_ccm.c b/hw/misc/imx6_ccm.c
index 4c830fd89a..85af466c2b 100644
--- a/hw
Signed-off-by: Bernhard Beschow
---
hw/watchdog/wdt_imx2.c | 4
hw/watchdog/trace-events | 2 ++
2 files changed, 6 insertions(+)
diff --git a/hw/watchdog/wdt_imx2.c b/hw/watchdog/wdt_imx2.c
index 885ebd3978..891d7beb2a 100644
--- a/hw/watchdog/wdt_imx2.c
+++ b/hw/watchdog/wdt_imx2.c
@@ -
This series enhances the tracing experience of some i.MX devices by adding new
trace events and by converting from DPRINTF. SMBus gets also converted from
DPRINTF to trace events. Finally, when tracing memory region operations, host
pointers aren't traced any longer and are substituted by their mem
Anything else needed before this patch can be merged?
Cheers,
Daan
On Wed, 25 Oct 2023 at 19:37, Daniel P. Berrangé wrote:
>
> On Sat, Oct 21, 2023 at 03:40:15PM +0200, Daan De Meyer wrote:
> > This allows passing the KVM device node to use as a file
> > descriptor via /dev/fdset/XX. Passing th
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