Re: [PATCH v2 10/11] tpm_crb_sysbus: introduce TPM CRB SysBus device

On Mon, Jul 17, 2023 at 7:23 AM Igor Mammedov wrote: > > On Fri, 14 Jul 2023 00:09:26 -0700 > Joelle van Dyne wrote: > > > This SysBus variant of the CRB interface supports dynamically locating > > the MMIO interface so that Virt machines can use it. This interface > > is currently the only one

Re: [PATCH v5 3/5] hw/isa/vt82c686: Reuse acpi_update_sci()

Am 29. Oktober 2023 00:07:00 UTC schrieb BALATON Zoltan : >On Sat, 28 Oct 2023, Bernhard Beschow wrote: >> acpi_update_sci() covers everything pm_update_sci() does. It implements >> common >> ACPI funtionality in a generic fashion. Note that it agnostic to any >> Frankenstein usage of the

Re: [PATCH v5 0/5] VIA PM: Implement basic ACPI support

Am 28. Oktober 2023 17:47:15 UTC schrieb BALATON Zoltan : >On Sat, 28 Oct 2023, Bernhard Beschow wrote: >> Am 28. Oktober 2023 12:58:32 UTC schrieb BALATON Zoltan : >>> Hello, >>> >>> On Sat, 28 Oct 2023, Bernhard Beschow wrote: This series is part of my work to bring the VIA south

[PATCH 1/1] target/riscv: correct csr_ops[CSR_MSECCFG]

The CSR register mseccfg is used by multiple extensions: Smepm and Zkr. Consider this when checking the existence of the register. Fixes: 77442380ecbe ("target/riscv: rvk: add CSR support for Zkr") Signed-off-by: Heinrich Schuchardt --- target/riscv/csr.c | 7 +-- 1 file changed, 5

Re: [PATCH v5 3/5] hw/isa/vt82c686: Reuse acpi_update_sci()

On Sat, 28 Oct 2023, Bernhard Beschow wrote: acpi_update_sci() covers everything pm_update_sci() does. It implements common ACPI funtionality in a generic fashion. Note that it agnostic to any Frankenstein usage of the general purpose event registers in other device models. It just implements a

Re: [PATCH v5 0/5] VIA PM: Implement basic ACPI support

On Sat, 28 Oct 2023, BALATON Zoltan wrote: On Sat, 28 Oct 2023, Bernhard Beschow wrote: Am 28. Oktober 2023 12:58:32 UTC schrieb BALATON Zoltan : Hello, On Sat, 28 Oct 2023, Bernhard Beschow wrote: This series is part of my work to bring the VIA south bridges to the PC machine [1]. It

[PATCH 3/4] hw/isa/vt82c686: Route PIRQ inputs using via_isa_set_irq()

The chip has 4 pins (called PIRQA-D in VT82C686B and PINTA-D in VT8231) that are meant to be connected to PCI IRQ lines and allow routing PCI interrupts to the ISA PIC. Route these in via_isa_set_irq() to make it possible to share them with internal functions that can also be routed to the same

[PATCH 2/4] hw/usb/vt82c686-uhci-pci: Use ISA instead of PCI interrupts

This device is part of a superio/ISA bridge chip and IRQs from it are routed to an ISA interrupt. Use via_isa_set_irq() function to implement this in a vt82c686-uhci-pci specific irq handler. This reverts commit 422a6e8075752bc5342afd3eace23a4990dd7d98. Signed-off-by: BALATON Zoltan ---

[PATCH 4/4] hw/audio/via-ac97: Route interrupts using via_isa_set_irq()

Signed-off-by: BALATON Zoltan --- hw/audio/via-ac97.c | 8 hw/isa/vt82c686.c | 1 + 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/hw/audio/via-ac97.c b/hw/audio/via-ac97.c index 30095a4c7a..4c127a1def 100644 --- a/hw/audio/via-ac97.c +++ b/hw/audio/via-ac97.c @@

[PATCH 1/4] hw/isa/vt82c686: Bring back via_isa_set_irq()

The VIA intergrated south bridge chips combine several functions and allow routing their interrupts to any of the ISA IRQs (also allowing multiple components to share the same ISA IRQ, e.g. pegasos2 firmware configures USB, sound and PCI to use IRQ 9). Bring back via_isa_set_irq() that takes the

[PATCH 0/4] Fix IRQ routing in via south bridge

This is going back to my otiginal proposal in https://patchew.org/QEMU/cover.1677004414.git.bala...@eik.bme.hu/ implementing routing of interrupts from device functions and PCI devices to ISA interrupts. On pegasos2 the firmware sets evertyhing to share IRQ 9 so the current simpified version

Re: [PATCH v1 2/6] target/loongarch: Add set_vec_extctx to set LSX/LASX instructions extctx_flags

On 10/9/23 20:36, Song Gao wrote: Signed-off-by: Song Gao --- target/loongarch/insn_trans/trans_vec.c.inc | 12 target/loongarch/internals.h| 2 ++ 2 files changed, 14 insertions(+) diff --git a/target/loongarch/insn_trans/trans_vec.c.inc

Re: [PATCH v1 5/6] linux-user/loongarch64: Add LSX sigcontext save/restore

On 10/9/23 20:37, Song Gao wrote: Signed-off-by: Song Gao --- linux-user/loongarch64/signal.c | 107 ++-- 1 file changed, 87 insertions(+), 20 deletions(-) diff --git a/linux-user/loongarch64/signal.c b/linux-user/loongarch64/signal.c index 277e9f5757..4b09e50a5f

Re: [PATCH v1 4/6] linux-user/loongarch64: setup_sigframe() set 'end' context size 0

On 10/9/23 20:36, Song Gao wrote: See: https://github.com/torvalds/linux/blob/master/arch/loongarch/kernel/signal.c The kernel setup_sigcontext() set end context size 0. Signed-off-by: Song Gao --- linux-user/loongarch64/signal.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

Re: [PATCH v1 3/6] linux-user/loongarch64: Fix setup_extcontext alloc wrong fpu_context size

On 10/9/23 20:36, Song Gao wrote: See: https://github.com/torvalds/linux/blob/master/arch/loongarch/kernel/signal.c The alloc size is sizeof(struct target_fpu_context). Signed-off-by: Song Gao --- linux-user/loongarch64/signal.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

[PATCH v2 32/35] target/alpha: Use TCG_COND_TST{EQ,NE} for BLB{C,S}

Signed-off-by: Richard Henderson --- target/alpha/translate.c | 39 --- 1 file changed, 16 insertions(+), 23 deletions(-) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 32333081d8..49e6a7b62d 100644 --- a/target/alpha/translate.c +++

[PATCH v2 14/35] tcg/i386: Support TCG_COND_TST{EQ,NE}

Merge tcg_out_testi into tcg_out_cmp and adjust the two uses. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 83 ++- 1 file changed, 47 insertions(+), 36 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index

[PATCH v2 10/35] tcg/aarch64: Generate CBNZ for TSTNE of UINT32_MAX

... and the inverse, CBZ for TSTEQ. Suggested-by: Paolo Bonzini Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 8 1 file changed, 8 insertions(+) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 55225313ad..0c98c48f68 100644 ---

[PATCH v2 22/35] tcg/sparc64: Support TCG_COND_TST{EQ,NE}

Signed-off-by: Richard Henderson --- tcg/sparc64/tcg-target.c.inc | 16 ++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index 10fb8a1a0d..176c98740b 100644 --- a/tcg/sparc64/tcg-target.c.inc +++

[PATCH v2 35/35] target/m68k: Use TCG_COND_TST{EQ, NE} in gen_fcc_cond

Signed-off-by: Richard Henderson --- target/m68k/translate.c | 74 ++--- 1 file changed, 33 insertions(+), 41 deletions(-) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 4a0b0b2703..f30b92f2d4 100644 --- a/target/m68k/translate.c +++

[PATCH v2 30/35] tcg/s390x: Support TCG_COND_TST{EQ,NE}

Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 139 + 1 file changed, 96 insertions(+), 43 deletions(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 86ec737768..cb1693c9cf 100644 ---

[PATCH v2 26/35] tcg/ppc: Add TCG_CT_CONST_CMP

Better constraint for tcg_out_cmp, based on the comparison. We can't yet remove the fallback to load constants into a scratch because of tcg_out_cmp2, but that path should not be as frequent. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target-con-set.h | 5 ++--

[PATCH v2 21/35] tcg/sparc64: Pass TCGCond to tcg_out_cmp

Signed-off-by: Richard Henderson --- tcg/sparc64/tcg-target.c.inc | 21 +++-- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index e16b25e309..10fb8a1a0d 100644 --- a/tcg/sparc64/tcg-target.c.inc +++

[PATCH v2 20/35] tcg/sparc64: Hoist read of tcg_cond_to_rcond

Use a non-zero value here (an illegal encoding) as a better condition than is_unsigned_cond for when MOVR/BPR is usable. Signed-off-by: Richard Henderson --- tcg/sparc64/tcg-target.c.inc | 25 ++--- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git

[PATCH v2 11/35] tcg/arm: Support TCG_COND_TST{EQ,NE}

Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 59 ++-- 1 file changed, 44 insertions(+), 15 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 0c29a3929b..0fc7273b16 100644 --- a/tcg/arm/tcg-target.c.inc +++

[PATCH v2 31/35] tcg/tci: Support TCG_COND_TST{EQ,NE}

Signed-off-by: Richard Henderson --- tcg/tci.c | 14 ++ 1 file changed, 14 insertions(+) diff --git a/tcg/tci.c b/tcg/tci.c index 4640902c88..5e1c4a491d 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -228,6 +228,12 @@ static bool tci_compare32(uint32_t u0, uint32_t u1, TCGCond

[PATCH v2 13/35] tcg/i386: Move tcg_cond_to_jcc[] into tcg_out_cmp

Return the x86 condition codes to use after the compare. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 24 +--- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index

[PATCH v2 29/35] tcg/s390x: Add TCG_CT_CONST_CMP

Better constraint for tcg_out_cmp, based on the comparison. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-con-set.h | 6 +-- tcg/s390x/tcg-target-con-str.h | 1 + tcg/s390x/tcg-target.c.inc | 72 +- 3 files changed, 58 insertions(+), 21

[PATCH v2 16/35] tcg/loongarch64: Support TCG_COND_TST{EQ,NE}

Signed-off-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 56 ++-- 1 file changed, 38 insertions(+), 18 deletions(-) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index 384d2ba342..7770e1bfa0 100644 ---

[PATCH v2 17/35] tcg/mips: Support TCG_COND_TST{EQ,NE}

Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 41 +++ 1 file changed, 41 insertions(+) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 35eff82bb3..f5680d7b89 100644 --- a/tcg/mips/tcg-target.c.inc +++

[PATCH v2 28/35] tcg/s390x: Split constraint A into J+U

Signed 33-bit == signed 32-bit + unsigned 32-bit. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-con-set.h | 8 tcg/s390x/tcg-target-con-str.h | 2 +- tcg/s390x/tcg-target.c.inc | 36 +- 3 files changed, 23 insertions(+), 23 deletions(-)

[PATCH v2 09/35] tcg/aarch64: Generate TBZ, TBNZ

Test the sign bit for LT/GE vs 0, and TSTNE/EQ vs a power of 2. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 100 --- 1 file changed, 81 insertions(+), 19 deletions(-) diff --git a/tcg/aarch64/tcg-target.c.inc

[PATCH v2 12/35] tcg/i386: Pass x86 condition codes to tcg_out_cmov

Hoist the tcg_cond_to_jcc index outside the function. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index eeb23d3fca..8b1baa8206 100644 ---

[PATCH v2 19/35] tcg/sparc64: Implement tcg_out_extrl_i64_i32

Build fix for missing symbol. Cc: qemu-sta...@nongnu.org Fixes: b8b94ac6753 ("tcg: Split out tcg_out_extrl_i64_i32") Signed-off-by: Richard Henderson --- tcg/sparc64/tcg-target.c.inc | 5 + 1 file changed, 5 insertions(+) diff --git a/tcg/sparc64/tcg-target.c.inc

[PATCH v2 15/35] tcg/i386: Improve TSTNE/TESTEQ vs powers of two

Use "test x,x" when the bit is one of the 4 sign bits. Use "bt imm,x" otherwise. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target-con-set.h | 6 ++-- tcg/i386/tcg-target-con-str.h | 1 + tcg/i386/tcg-target.c.inc | 56 --- 3 files changed, 56

[PATCH v2 27/35] tcg/ppc: Support TCG_COND_TST{EQ,NE}

Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 105 --- 1 file changed, 98 insertions(+), 7 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index b20dbe036d..ef1d959892 100644 --- a/tcg/ppc/tcg-target.c.inc +++

[PATCH v2 33/35] target/alpha: Use TCG_COND_TST{EQ, NE} for CMOVLB{C, S}

Signed-off-by: Richard Henderson --- target/alpha/translate.c | 8 ++-- 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 49e6a7b62d..c7daf46de7 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@

[PATCH v2 24/35] tcg/ppc: Use cr0 in tcg_to_bc and tcg_to_isel

Using cr0 means we could choose to use rc=1 to compute the condition. Adjust the tables and tcg_out_cmp that feeds them. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 68 1 file changed, 34 insertions(+), 34 deletions(-) diff --git

[PATCH v2 23/35] tcg/ppc: Sink tcg_to_bc usage into tcg_out_bc

Rename the current tcg_out_bc function to tcg_out_bc_lab, and create a new function that takes an integer displacement + link. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 28 +--- 1 file changed, 17 insertions(+), 11 deletions(-) diff --git

[PATCH v2 06/35] tcg/optimize: Handle TCG_COND_TST{EQ,NE}

Fold constant comparisons. Canonicalize "tst x,x" to equality vs zero. Canonicalize "tst x,sign" to sign test vs zero. Fold double-word comparisons with zero parts. Fold setcond of "tst x,pow2" to a bit extract. Signed-off-by: Richard Henderson --- tcg/optimize.c | 245

[PATCH v2 08/35] tcg/aarch64: Support TCG_COND_TST{EQ,NE}

Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-con-set.h | 5 +-- tcg/aarch64/tcg-target-con-str.h | 1 + tcg/aarch64/tcg-target.c.inc | 56 ++-- 3 files changed, 43 insertions(+), 19 deletions(-) diff --git a/tcg/aarch64/tcg-target-con-set.h

[PATCH v2 18/35] tcg/riscv: Support TCG_COND_TST{EQ,NE}

Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 20 ++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 639363039b..358579b3fd 100644 --- a/tcg/riscv/tcg-target.c.inc +++

[PATCH v2 25/35] tcg/ppc: Tidy up tcg_target_const_match

Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 27 --- 1 file changed, 16 insertions(+), 11 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 1ac11acc7c..13d43ef9ba 100644 --- a/tcg/ppc/tcg-target.c.inc +++

[PATCH v2 01/35] tcg: Introduce TCG_COND_TST{EQ,NE}

Add the enumerators, adjust the helpers to match, and dump. Not supported anywhere else just yet. Signed-off-by: Richard Henderson --- docs/devel/tcg-ops.rst | 2 ++ include/tcg/tcg-cond.h | 49 -- tcg/tcg.c | 4 +++- 3 files changed, 43

[PATCH v2 04/35] tcg/optimize: Do swap_commutative2 in do_constant_folding_cond2

Mirror the new do_constant_folding_cond1 by doing all argument and condition adjustment within one helper. Signed-off-by: Richard Henderson --- tcg/optimize.c | 107 ++--- 1 file changed, 57 insertions(+), 50 deletions(-) diff --git a/tcg/optimize.c

[PATCH v2 02/35] tcg/optimize: Split out arg_is_const_val

Signed-off-by: Richard Henderson --- tcg/optimize.c | 38 +++--- 1 file changed, 23 insertions(+), 15 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 2db5177c32..e8a13fedb5 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -112,11 +112,22 @@

[PATCH v2 34/35] target/alpha: Use TCG_COND_TSTNE for gen_fold_mzero

Signed-off-by: Richard Henderson --- target/alpha/translate.c | 49 +++- 1 file changed, 23 insertions(+), 26 deletions(-) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index c7daf46de7..c68c2bcd21 100644 --- a/target/alpha/translate.c +++

[PATCH v2 05/35] tcg/optimize: Split out arg_new_constant

Fixes a bug wherein raw uses of tcg_constant_internal do not have their TempOptInfo initialized. Signed-off-by: Richard Henderson --- tcg/optimize.c | 29 ++--- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index

[PATCH v2 03/35] tcg/optimize: Split out do_constant_folding_cond1

Handle modifications to the arguments and condition in a single place. Signed-off-by: Richard Henderson --- tcg/optimize.c | 57 -- 1 file changed, 27 insertions(+), 30 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index

[PATCH v2 07/35] tcg: Add TCGConst argument to tcg_target_const_match

Fill the new argument from any condition within the opcode. Not yet used within any backend. Signed-off-by: Richard Henderson --- tcg/tcg.c| 34 ++-- tcg/aarch64/tcg-target.c.inc | 3 ++- tcg/arm/tcg-target.c.inc | 3 ++-

[PATCH v2 00/35] tcg: Introduce TCG_COND_TST{EQ,NE}

Expose a pair of comparison operators that map to the "test" comparison that is available on many architectures. Changes for v2: * Add TCGCond to tcg_target_const_match. This fixes a long-standing issue with ppc and s390x backends, in that CMPI for signed comparisons has signed

Re: [PATCH 15/17] semihosting: fix memleak at semihosting_arg_fallback

On 10/28/23 03:33, Alex Bennée wrote: From: Matheus Tavares Bernardino We duplicate "cmd" as strtok may modify its argument, but we forgot to free it later. Furthermore, add_semihosting_arg doesn't take responsibility for this memory either (it strdup's the argument). Signed-off-by: Matheus

Re: [PATCH 14/17] gdbstub: Check if gdb_regs is NULL

On 10/28/23 03:33, Alex Bennée wrote: From: Akihiko Odaki cpu->gdb_regs may be NULL if no coprocessor is registered. Fixes: 73c392c26b ("gdbstub: Replace gdb_regs with an array") Signed-off-by: Akihiko Odaki Message-Id: <20231019101030.128431-2-akihiko.od...@daynix.com> Signed-off-by: Alex

Re: [PATCH 13/17] tests/docker: upgrade debian-all-test-cross to bookworm

On 10/28/23 03:33, Alex Bennée wrote: This requires a few more tweaks than usual as: - the default sources format has changed - bring in python3-tomli from the repos - split base install from cross compilers - also include libclang-rt-dev for sanitiser builds Signed-off-by: Alex

Re: [PATCH 12/17] tests/docker: use debian-all-test-cross for sparc64

On 10/28/23 03:33, Alex Bennée wrote: Maintaining two sets of containers for test building is silly. While it makes sense for the QEMU cross-compile targets to have their own fat containers built by lcitool we might as well merge the other random debian based compilers into the same one used on

Re: [PATCH 11/17] tests/docker: use debian-all-test-cross for riscv64

On 10/28/23 03:33, Alex Bennée wrote: Maintaining two sets of containers for test building is silly. While it makes sense for the QEMU cross-compile targets to have their own fat containers built by lcitool we might as well merge the other random debian based compilers into the same one used on

Re: [PATCH 10/17] tests/docker: use debian-all-test-cross for mips

On 10/28/23 03:33, Alex Bennée wrote: Maintaining two sets of containers for test building is silly. While it makes sense for the QEMU cross-compile targets to have their own fat containers built by lcitool we might as well merge the other random debian based compilers into the same one used on

Re: [PATCH 09/17] tests/docker: use debian-all-test-cross for mips64

On 10/28/23 03:33, Alex Bennée wrote: Maintaining two sets of containers for test building is silly. While it makes sense for the QEMU cross-compile targets to have their own fat containers built by lcitool we might as well merge the other random debian based compilers into the same one used on

Re: [PATCH 08/17] tests/docker: use debian-all-test-cross for m68k

On 10/28/23 03:33, Alex Bennée wrote: Maintaining two sets of containers for test building is silly. While it makes sense for the QEMU cross-compile targets to have their own fat containers built by lcitool we might as well merge the other random debian based compilers into the same one used on

Re: [PATCH 07/17] tests/docker: use debian-all-test-cross for hppa

On 10/28/23 03:33, Alex Bennée wrote: Maintaining two sets of containers for test building is silly. While it makes sense for the QEMU cross-compile targets to have their own fat containers built by lcitool we might as well merge the other random debian based compilers into the same one used on

Re: [PATCH 06/17] tests/docker: use debian-all-test-cross for power

On 10/28/23 03:33, Alex Bennée wrote: Maintaining two sets of containers for test building is silly. While it makes sense for the QEMU cross-compile targets to have their own fat containers built by lcitool we might as well merge the other random debian based compilers into the same one used on

Re: [PATCH 05/17] tests/docker: move sh4 to use debian-legacy-test-cross

On 10/28/23 03:32, Alex Bennée wrote: diff --git a/.gitlab-ci.d/buildtest.yml b/.gitlab-ci.d/buildtest.yml index d670fb42b9..983c95e785 100644 --- a/.gitlab-ci.d/buildtest.yml +++ b/.gitlab-ci.d/buildtest.yml @@ -276,7 +276,7 @@ build-user-legacy: job: amd64-debian-legacy-cross-container

Re: [PATCH 04/17] tests/docker: use debian-legacy-test-cross for alpha

On 10/28/23 03:32, Alex Bennée wrote: Maintaining two sets of containers for test building is silly. While it makes sense for the QEMU cross-compile targets to have their own fat containers built by lcitool we might as well merge the other random debian based compilers into the same one used on

Re: [PATCH 03/17] gitlab: split alpha testing into a legacy container

On 10/28/23 03:32, Alex Bennée wrote: @@ -278,6 +291,7 @@ build-user-hexagon: MAKE_CHECK_ARGS: check-tcg # Only build the softmmu targets we have check-tcg tests for +# (skip alpha due to missing compilers, others need their own containers) build-some-softmmu: extends:

Re: [PATCH 02/17] tests/tcg: Add -fno-stack-protector

On 10/28/23 03:32, Alex Bennée wrote: From: Akihiko Odaki A build of GCC 13.2 will have stack protector enabled by default if it was configured with --enable-default-ssp option. For such a compiler, it is necessary to explicitly disable stack protector when linking without standard libraries.

Re: [PATCH v7 0/3] Add emulation of AmigaOne XE board

On Sat, 28 Oct 2023, Bernhard Beschow wrote: Am 27. Oktober 2023 11:54:48 UTC schrieb BALATON Zoltan : Changes in v7: - Increase default memory size to 512m to match pegasos2 and sam460ex and it's a better default for AmigaOS Changes in v6: - Dropped patch 1, now it's Based-on:

Re: [PATCH 16/17] plugins: Remove an extra parameter

On 10/28/23 03:33, Alex Bennée wrote: From: Akihiko Odaki copy_call() has an unused parameter so remove it. Signed-off-by: Akihiko Odaki Message-Id: <20231019101030.128431-7-akihiko.od...@daynix.com> Reviewed-by: Richard Henderson r~

Re: [PATCH v5 5/5] hw/isa/vt82c686: Implement software-based SMI triggering

On Sat, 28 Oct 2023, Bernhard Beschow wrote: Am 28. Oktober 2023 13:03:41 UTC schrieb BALATON Zoltan : On Sat, 28 Oct 2023, Bernhard Beschow wrote: If enabled, SMIs can be triggered via software by writing to an IO-mapped port. SMIs usually trigger execution of BIOS code. If appropriate values

Re: [PATCH v6 01/12] target/riscv: add zicbop extension flag

On 10/28/23 06:49, Andrew Jones wrote: On Sat, Oct 28, 2023 at 05:54:16AM -0300, Daniel Henrique Barboza wrote: QEMU already implements zicbom (Cache Block Management Operations) and zicboz (Cache Block Zero Operations). Commit 59cb29d6a5 ("target/riscv: add Zicbop cbo.prefetch{i, r, m}

Re: [PATCH v5 5/5] hw/isa/vt82c686: Implement software-based SMI triggering

Am 28. Oktober 2023 13:03:41 UTC schrieb BALATON Zoltan : >On Sat, 28 Oct 2023, Bernhard Beschow wrote: >> If enabled, SMIs can be triggered via software by writing to an IO-mapped >> port. >> SMIs usually trigger execution of BIOS code. If appropriate values are >> written >> to the port,

Re: [PATCH v5 3/5] hw/isa/vt82c686: Reuse acpi_update_sci()

Am 28. Oktober 2023 12:59:56 UTC schrieb BALATON Zoltan : >On Sat, 28 Oct 2023, Bernhard Beschow wrote: >> acpi_update_sci() covers everything pm_update_sci() does. It implements >> common >> ACPI funtionality in a generic fashion. Note that it agnostic to any >> Frankenstein usage of the

Re: [PATCH v5 0/5] VIA PM: Implement basic ACPI support

Am 28. Oktober 2023 12:58:32 UTC schrieb BALATON Zoltan : >Hello, > >On Sat, 28 Oct 2023, Bernhard Beschow wrote: >> This series is part of my work to bring the VIA south bridges to the PC >> machine >> [1]. It implements missing ACPI functionality which ACPI-aware x86 guests >> expect for a

Re: [PATCH v7 0/3] Add emulation of AmigaOne XE board

Am 27. Oktober 2023 11:54:48 UTC schrieb BALATON Zoltan : >Changes in v7: >- Increase default memory size to 512m to match pegasos2 and sam460ex >and it's a better default for AmigaOS > >Changes in v6: >- Dropped patch 1, now it's > >Based-on:

Re: [PATCH 0/5] Add LoongArch v1.1 instructions

On 2023/10/26 14:54, gaosong wrote: 在 2023/10/26 上午9:38, Jiajie Chen 写道: On 2023/10/26 03:04, Richard Henderson wrote: On 10/25/23 10:13, Jiajie Chen wrote: On 2023/10/24 07:26, Richard Henderson wrote: See target/arm/tcg/translate-a64.c, gen_store_exclusive, TCGv_i128 block. See

Re: [PATCH v5 5/5] hw/isa/vt82c686: Implement software-based SMI triggering

On Sat, 28 Oct 2023, Bernhard Beschow wrote: If enabled, SMIs can be triggered via software by writing to an IO-mapped port. SMIs usually trigger execution of BIOS code. If appropriate values are written to the port, the BIOS transitions the system into or out of ACPI mode. Note that APMState

Re: [PATCH v5 3/5] hw/isa/vt82c686: Reuse acpi_update_sci()

On Sat, 28 Oct 2023, Bernhard Beschow wrote: acpi_update_sci() covers everything pm_update_sci() does. It implements common ACPI funtionality in a generic fashion. Note that it agnostic to any Frankenstein usage of the general purpose event registers in other device models. It just implements a

Re: [PATCH v5 0/5] VIA PM: Implement basic ACPI support

Hello, On Sat, 28 Oct 2023, Bernhard Beschow wrote: This series is part of my work to bring the VIA south bridges to the PC machine [1]. It implements missing ACPI functionality which ACPI-aware x86 guests expect for a smooth experience. The implementation is heavily inspired by PIIX4. I

[PATCH 6/6] system/memory: Trace names of MemoryRegions rather than host pointers

Tracing the host pointer of the accessed MemoryRegion seems to be a debug feature for developing QEMU itself. When analyzing guest behavior by comparing traces, these pointers generate a lot of noise since the pointers differ between QEMU invocations, making this task harder than it needs to be.

[PATCH 3/6] hw/misc/imx7_snvs: Trace MMIO access

Signed-off-by: Bernhard Beschow --- hw/misc/imx7_snvs.c | 5 + hw/misc/trace-events | 4 2 files changed, 9 insertions(+) diff --git a/hw/misc/imx7_snvs.c b/hw/misc/imx7_snvs.c index ee7698bd9c..a245f96cd4 100644 --- a/hw/misc/imx7_snvs.c +++ b/hw/misc/imx7_snvs.c @@ -16,9 +16,12 @@

[PATCH 5/6] hw/i2c/pm_smbus: Convert DPRINTF to trace events

Let the trace messages slightly deviate from the function names ("smb" -> "smbus") being traced in order to avoid conflights with the SMB protocol. Signed-off-by: Bernhard Beschow --- hw/i2c/pm_smbus.c | 18 -- hw/i2c/trace-events | 6 ++ 2 files changed, 10

[PATCH 1/6] hw/watchdog/wdt_imx2: Trace MMIO access

Signed-off-by: Bernhard Beschow --- hw/watchdog/wdt_imx2.c | 24 ++-- hw/watchdog/trace-events | 4 2 files changed, 22 insertions(+), 6 deletions(-) diff --git a/hw/watchdog/wdt_imx2.c b/hw/watchdog/wdt_imx2.c index e776a2fbd4..885ebd3978 100644 ---

[PATCH 4/6] hw/misc/imx6_ccm: Convert DPRINTF to trace events

Signed-off-by: Bernhard Beschow --- hw/misc/imx6_ccm.c | 41 ++--- hw/misc/trace-events | 15 +++ 2 files changed, 29 insertions(+), 27 deletions(-) diff --git a/hw/misc/imx6_ccm.c b/hw/misc/imx6_ccm.c index 4c830fd89a..85af466c2b 100644 ---

[PATCH 2/6] hw/watchdog/wdt_imx2: Trace timer activity

Signed-off-by: Bernhard Beschow --- hw/watchdog/wdt_imx2.c | 4 hw/watchdog/trace-events | 2 ++ 2 files changed, 6 insertions(+) diff --git a/hw/watchdog/wdt_imx2.c b/hw/watchdog/wdt_imx2.c index 885ebd3978..891d7beb2a 100644 --- a/hw/watchdog/wdt_imx2.c +++ b/hw/watchdog/wdt_imx2.c @@

[PATCH 0/6] Various tracing patches

This series enhances the tracing experience of some i.MX devices by adding new trace events and by converting from DPRINTF. SMBus gets also converted from DPRINTF to trace events. Finally, when tracing memory region operations, host pointers aren't traced any longer and are substituted by their

Re: [PATCH] Add class property to configure KVM device node to use

Anything else needed before this patch can be merged? Cheers, Daan On Wed, 25 Oct 2023 at 19:37, Daniel P. Berrangé wrote: > > On Sat, Oct 21, 2023 at 03:40:15PM +0200, Daan De Meyer wrote: > > This allows passing the KVM device node to use as a file > > descriptor via /dev/fdset/XX. Passing

[PATCH v3 2/3] hw/ppc: Add nest1 chiplet model

The nest1 chiplet handle the high speed i/o traffic over PCIe and others. The nest1 chiplet consists of PowerBus Fabric controller, nest Memory Management Unit, chiplet control unit and more. This commit creates a nest1 chiplet model and initialize and realize the pervasive chiplet model where

[PATCH v3 0/3] pnv nest1 chiplet model

Hello, For modularity reasons the P10 processor chip is split into multiple chiplets individually controlled and managed by the pervasive logic. The boundaries of these chiplets are defined based on physical design parameters like clock grids, the nature of the functional units as well as their

[PATCH v3 1/3] hw/ppc: Add pnv pervasive common chiplet units

This part of the patchset creates a common pervasive chiplet model where it houses the common units of a chiplets. The chiplet control unit is common across chiplets and this commit implements the pervasive chiplet model with chiplet control registers. Signed-off-by: Chalapathi V ---

[PATCH v3 3/3] hw/ppc: Nest1 chiplet wiring

This part of the patchset connects the nest1 chiplet model to p10 chip. Signed-off-by: Chalapathi V --- hw/ppc/pnv.c | 11 +++ include/hw/ppc/pnv_chip.h | 2 ++ 2 files changed, 13 insertions(+) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index eb54f93986..a5abaf5608 100644

Re: [PATCH v6 06/12] target/riscv/tcg: add user flag for profile support

On Sat, Oct 28, 2023 at 05:54:21AM -0300, Daniel Henrique Barboza wrote: > The TCG emulation implements all the extensions described in the > RVA22U64 profile, both mandatory and optional. The mandatory extensions > will be enabled via the profile flag. We'll leave the optional > extensions to be

[PATCH 16/17] plugins: Remove an extra parameter

From: Akihiko Odaki copy_call() has an unused parameter so remove it. Signed-off-by: Akihiko Odaki Message-Id: <20231019101030.128431-7-akihiko.od...@daynix.com> --- accel/tcg/plugin-gen.c | 9 +++-- 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/accel/tcg/plugin-gen.c

[PATCH 17/17] contrib/plugins: Close file descriptor on error return

From: Cong Liu This patch closes the file descriptor fd on error return to avoid resource leak. Fixes: ec7ee95db909 ("contrib/plugins: fix coverity warning in lockstep") Signed-off-by: Cong Liu Message-Id: <20231018025225.1640122-1-liuco...@kylinos.cn> Signed-off-by: Alex Bennée ---

[PATCH 00/17] Maintainer updates for testing, gdb, semihosting and plugins

This collects up a number of fixes across my various maintainer trees. There will be a longer plugins related one coming later but I wanted to turn these around first. The update to bookworm was delayed from the last release but I've now "solved" that by moving sh4 and alpha into a legacy

[PATCH 14/17] gdbstub: Check if gdb_regs is NULL

From: Akihiko Odaki cpu->gdb_regs may be NULL if no coprocessor is registered. Fixes: 73c392c26b ("gdbstub: Replace gdb_regs with an array") Signed-off-by: Akihiko Odaki Message-Id: <20231019101030.128431-2-akihiko.od...@daynix.com> Signed-off-by: Alex Bennée Tested-by: Fabiano Rosas ---

[PATCH 15/17] semihosting: fix memleak at semihosting_arg_fallback

From: Matheus Tavares Bernardino We duplicate "cmd" as strtok may modify its argument, but we forgot to free it later. Furthermore, add_semihosting_arg doesn't take responsibility for this memory either (it strdup's the argument). Signed-off-by: Matheus Tavares Bernardino Reviewed-by: Philippe

[PATCH 03/17] gitlab: split alpha testing into a legacy container

The current bookworm compiler doesn't build the static binaries due to bug #1054412 and it might be awhile before it gets fixes. The problem of keeping older architecture compilers running isn't going to go away so lets prepare the ground. Create a legacy container and move some tests around so

[PATCH 07/17] tests/docker: use debian-all-test-cross for hppa

Maintaining two sets of containers for test building is silly. While it makes sense for the QEMU cross-compile targets to have their own fat containers built by lcitool we might as well merge the other random debian based compilers into the same one used on gitlab. Signed-off-by: Alex Bennée ---

[PATCH 05/17] tests/docker: move sh4 to use debian-legacy-test-cross

sh4 is another target which doesn't work with bookworm compilers. To keep on buster move across to the debian-legacy-test-cross image and update accordingly. Signed-off-by: Alex Bennée --- configure | 4 .gitlab-ci.d/buildtest.yml|

[PATCH 02/17] tests/tcg: Add -fno-stack-protector

From: Akihiko Odaki A build of GCC 13.2 will have stack protector enabled by default if it was configured with --enable-default-ssp option. For such a compiler, it is necessary to explicitly disable stack protector when linking without standard libraries. Signed-off-by: Akihiko Odaki

[PATCH 12/17] tests/docker: use debian-all-test-cross for sparc64

Maintaining two sets of containers for test building is silly. While it makes sense for the QEMU cross-compile targets to have their own fat containers built by lcitool we might as well merge the other random debian based compilers into the same one used on gitlab. Signed-off-by: Alex Bennée ---

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