Re: [PATCH-for-9.0 04/10] hw/xen: Factor xen_arch_align_ioreq_data() out of handle_ioreq()

On 13/11/23 18:11, David Woodhouse wrote: On Mon, 2023-11-13 at 17:09 +0100, Philippe Mathieu-Daudé wrote: On 13/11/23 16:58, Woodhouse, David wrote: On 13 Nov 2023 10:22, Philippe Mathieu-Daudé wrote:     Per commit f17068c1c7 ("xen-hvm: reorganize xen-hvm and move common     function to

Re: [PATCH-for-9.0 08/10] system/physmem: Only include 'hw/xen/xen.h' when Xen is available

On 13/11/23 21:03, David Woodhouse wrote: On Mon, 2023-11-13 at 16:21 +0100, Philippe Mathieu-Daudé wrote: "hw/xen/xen.h" contains declarations for Xen hardware. There is no point including it when Xen is not available. ... if even when Xen *is* available, AFAICT. Can you just remove the

Re: [PATCH-for-9.0 04/10] hw/xen: Factor xen_arch_align_ioreq_data() out of handle_ioreq()

On 13/11/23 19:16, Richard Henderson wrote: On 11/13/23 07:21, Philippe Mathieu-Daudé wrote: diff --git a/hw/xen/xen-hvm-common.c b/hw/xen/xen-hvm-common.c index c028c1b541..03f9417e7e 100644 --- a/hw/xen/xen-hvm-common.c +++ b/hw/xen/xen-hvm-common.c @@ -426,10 +426,7 @@ static void

Re: [PATCH 0/2] Replace anti-social QOM type names (again)

Cc: the other QOM maintainers Daniel P. Berrangé writes: > On Mon, Nov 13, 2023 at 02:43:42PM +0100, Markus Armbruster wrote: >> We got rid of QOM type names containing ',' in 6.0, but some have >> crept back in. Replace them just like we did in 6.0. > > It is practical to add > >

Re: Configuring migration

Cc: Paolo for QOM expertise. Peter Xu writes: > On Thu, Nov 02, 2023 at 03:25:25PM +0100, Markus Armbruster wrote: [...] >> Migration has its own idiosyncratic configuration interface, even though >> its configuration needs are not special at all. This is due to a long >> history of

Re: [PATCH v6 11/21] virtio-net: Return an error when vhost cannot enable RSS

On 2023/11/14 2:26, Yuri Benditovich wrote: On Mon, Nov 13, 2023 at 2:44 PM Akihiko Odaki > wrote: On 2023/11/13 20:44, Yuri Benditovich wrote: > > > On Sat, Nov 11, 2023 at 5:28 PM Akihiko Odaki mailto:akihiko.od...@daynix.com> >

Re: [PATCH v2] test/qtest: Add API functions to capture IRQ toggling

On 14/11/2023 00.01, Gustavo Romero wrote: Currently, the QTest API does not provide a function to capture when an IRQ line is raised or lowered, although the QTest Protocol already reports such IRQ transitions. As a consequence, it is also not possible to capture when an IRQ line is toggled.

RE: [PATCH v1] target/i386/host-cpu: Use IOMMU addr width for passthrough devices on Intel platforms

Hi Laszlo, > > On 11/13/23 08:32, Vivek Kasireddy wrote: > > A recent OVMF update has resulted in MMIO regions being placed at > > the upper end of the physical address space. As a result, when a > > Host device is passthrough'd to the Guest via VFIO, the following > > mapping failures occur

Re: [QEMU][PATCHv2 0/8] Xen: support grant mappings.

On 13.11.23 21:24, David Woodhouse wrote: On Fri, 2023-10-27 at 07:27 +0200, Juergen Gross wrote: On 26.10.23 22:56, Stefano Stabellini wrote: On Thu, 26 Oct 2023, David Woodhouse wrote: On Thu, 2023-10-26 at 13:36 -0700, Stefano Stabellini wrote: This seems like a lot of code to replace

[PATCH v2 15/20] migration/multifd: Add test hook to set normal page ratio.

Multifd sender thread performs zero page checking. If a page is a zero page, only the page's metadata is sent to the receiver. If a page is a normal page, the entire page's content is sent to the receiver. This change adds a test hook to set the normal page ratio. A zero page will be forced to be

[PATCH v2 16/20] migration/multifd: Enable set normal page ratio test hook in multifd.

Test hook is disabled by default. To set it, a normal page ratio between 0 and 100 are valid. If the ratio is set to 50, it means at least 50% of all pages are sent as normal pages. Set the option: migrate_set_parameter multifd-normal-page-ratio 60 Signed-off-by: Hao Xiang ---

[PATCH v2 17/20] migration/multifd: Add migration option set packet size.

The current multifd packet size is 128 * 4kb. This change adds an option to set the packet size. Both sender and receiver needs to set the same packet size for things to work. Signed-off-by: Hao Xiang --- migration/options.c | 34 ++ migration/options.h | 1 +

[PATCH v2 02/20] multifd: Support for zero pages transmission

From: Juan Quintela This patch adds counters and similar. Logic will be added on the following patch. Signed-off-by: Juan Quintela --- migration/multifd.c| 37 ++--- migration/multifd.h| 17 - migration/trace-events | 8 3

[PATCH v2 20/20] migration/multifd: Add integration tests for multifd with Intel DSA offloading.

* Add test case to start and complete multifd live migration with DSA offloading enabled. * Add test case to start and cancel multifd live migration with DSA offloading enabled. Signed-off-by: Bryan Zhang Signed-off-by: Hao Xiang --- tests/qtest/migration-test.c | 77

[PATCH v2 05/20] meson: Introduce new instruction set enqcmd to the build system.

Enable instruction set enqcmd in build. Signed-off-by: Hao Xiang --- meson.build | 2 ++ meson_options.txt | 2 ++ scripts/meson-buildoptions.sh | 3 +++ 3 files changed, 7 insertions(+) diff --git a/meson.build b/meson.build index ec01f8b138..1292ab78a3 100644

[PATCH v2 10/20] util/dsa: Implement zero page checking in DSA task.

Create DSA task with operation code DSA_OPCODE_COMPVAL. Here we create two types of DSA tasks, a single DSA task and a batch DSA task. Batch DSA task reduces task submission overhead and hence should be the default option. However, due to the way DSA hardware works, a DSA batch task must contain

[PATCH v2 18/20] migration/multifd: Enable set packet size migration option.

During live migration, if the latency between sender and receiver is high but bandwidth is high (a long and fat pipe), using a bigger packet size can help reduce migration total time. In addition, Intel DSA offloading performs better with a large batch task. Providing an option to set the packet

[PATCH v2 07/20] util/dsa: Implement DSA device start and stop logic.

* DSA device open and close. * DSA group contains multiple DSA devices. * DSA group configure/start/stop/clean. Signed-off-by: Hao Xiang Signed-off-by: Bryan Zhang --- include/qemu/dsa.h | 49 +++ util/dsa.c | 338 + util/meson.build |

[PATCH v2 14/20] migration/multifd: Enable DSA offloading in multifd sender path.

Multifd sender path gets an array of pages queued by the migration thread. It performs zero page checking on every page in the array. The pages are classfied as either a zero page or a normal page. This change uses Intel DSA to offload the zero page checking from CPU to the DSA accelerator. The

[PATCH v2 04/20] So we use multifd to transmit zero pages.

From: Juan Quintela Signed-off-by: Juan Quintela Reviewed-by: Leonardo Bras --- migration/multifd.c | 7 --- migration/options.c | 13 +++-- migration/ram.c | 45 ++--- qapi/migration.json | 1 - 4 files changed, 49 insertions(+), 17

[PATCH v2 06/20] util/dsa: Add dependency idxd.

Idxd is the device driver for DSA (Intel Data Streaming Accelerator). The driver is fully functioning since Linux kernel 5.19. This change adds the driver's header file used for userspace development. Signed-off-by: Hao Xiang --- linux-headers/linux/idxd.h | 356

[PATCH v2 09/20] util/dsa: Implement DSA task asynchronous completion thread model.

* Create a dedicated thread for DSA task completion. * DSA completion thread runs a loop and poll for completed tasks. * Start and stop DSA completion thread during DSA device start stop. User space application can directly submit task to Intel DSA accelerator by writing to DSA's device memory

[PATCH v2 08/20] util/dsa: Implement DSA task enqueue and dequeue.

* Use a safe thread queue for DSA task enqueue/dequeue. * Implement DSA task submission. * Implement DSA batch task submission. Signed-off-by: Hao Xiang --- include/qemu/dsa.h | 35 util/dsa.c | 196 + 2 files changed, 231

[PATCH v2 19/20] util/dsa: Add unit test coverage for Intel DSA task submission and completion.

* Test DSA start and stop path. * Test DSA configure and cleanup path. * Test DSA task submission and completion path. Signed-off-by: Bryan Zhang Signed-off-by: Hao Xiang --- tests/unit/meson.build | 6 + tests/unit/test-dsa.c | 466 + 2 files

[PATCH v2 11/20] util/dsa: Implement DSA task asynchronous submission and wait for completion.

* Add a DSA task completion callback. * DSA completion thread will call the tasks's completion callback on every task/batch task completion. * DSA submission path to wait for completion. * Implement CPU fallback if DSA is not able to complete the task. Signed-off-by: Hao Xiang Signed-off-by:

[PATCH v2 13/20] migration/multifd: Prepare to introduce DSA acceleration on the multifd path.

1. Refactor multifd_send_thread function. 2. Implement buffer_is_zero_use_cpu to handle CPU based zero page checking. 3. Introduce the batch task structure in MultiFDSendParams. Signed-off-by: Hao Xiang --- migration/multifd.c | 82 -

[PATCH v2 01/20] multifd: Add capability to enable/disable zero_page

From: Juan Quintela We have to enable it by default until we introduce the new code. Signed-off-by: Juan Quintela --- migration/options.c | 13 + migration/options.h | 1 + qapi/migration.json | 8 +++- 3 files changed, 21 insertions(+), 1 deletion(-) diff --git

[PATCH v2 12/20] migration/multifd: Add new migration option for multifd DSA offloading.

Intel DSA offloading is an optional feature that turns on if proper hardware and software stack is available. To turn on DSA offloading in multifd live migration: multifd-dsa-accel="[dsa_dev_path1] ] [dsa_dev_path2] ... [dsa_dev_pathX]" This feature is turned off by default. Signed-off-by: Hao

[PATCH v2 03/20] multifd: Zero pages transmission

From: Juan Quintela This implements the zero page dection and handling. Signed-off-by: Juan Quintela --- migration/multifd.c | 41 +++-- migration/multifd.h | 5 + 2 files changed, 44 insertions(+), 2 deletions(-) diff --git a/migration/multifd.c

[PATCH v2 00/20] Use Intel DSA accelerator to offload zero page checking in multifd live migration.

v2 * Rebase on top of 3e01f1147a16ca566694b97eafc941d62fa1e8d8. * Leave Juan's changes in their original form instead of squashing them. * Add a new commit to refactor the multifd_send_thread function to prepare for introducing the DSA offload functionality. * Use page count to configure

Re: [PATCH v2 0/2] net: Update MemReentrancyGuard for NIC

On Thu, Sep 21, 2023 at 3:16 PM Akihiko Odaki wrote: > > On 2023/06/01 12:18, Akihiko Odaki wrote: > > Recently MemReentrancyGuard was added to DeviceState to record that the > > device is engaging in I/O. The network device backend needs to update it > > when delivering a packet to a device. > >

RE: [PATCH v5 04/11] hw/net: Add NPCMXXX GMAC device

-Original Message- From: Nabih Estefan Sent: Saturday, October 28, 2023 1:55 AM To: peter.mayd...@linaro.org Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org; CS20 KFTing ; wuhao...@google.com; jasonw...@redhat.com; IS20 Avi Fishman ; nabiheste...@google.com; CS20 KWLiu ; IS20 Tomer

[PULL 2/2] igb: Add Function Level Reset to PF and VF

From: Cédric Le Goater The Intel 82576EB GbE Controller say that the Physical and Virtual Functions support Function Level Reset. Add the capability to the PF device model using device property "x-pcie-flr-init" which is "on" by default and "off" for machines <= 8.1 to preserve compatibility.

[PULL 0/2] Net patches

The following changes since commit 69680740eafa1838527c90155a7432d51b8ff203: Merge tag 'qdev-array-prop' of https://repo.or.cz/qemu/kevin into staging (2023-11-11 11:23:25 +0800) are available in the git repository at: https://github.com/jasowang/qemu.git tags/net-pull-request for you to

[PULL 1/2] igb: Add a VF reset handler

From: Cédric Le Goater Export the igb_vf_reset() helper routine from the PF model to let the IGBVF model implement its own device reset. Cc: Akihiko Odaki Suggested-by: Sriram Yagnaraman Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Cédric Le Goater Signed-off-by: Jason Wang ---

RE: [PATCH v5 10/20] vfio/pci: Make vfio cdev pre-openable by passing a file handle

>-Original Message- >From: Cédric Le Goater >Sent: Monday, November 13, 2023 7:08 PM >Subject: Re: [PATCH v5 10/20] vfio/pci: Make vfio cdev pre-openable by passing >a >file handle > >On 11/13/23 04:00, Duan, Zhenzhong wrote: >> >> >>> -Original Message- >>> From: Cédric Le

RE: [PATCH v5 03/20] vfio/iommufd: Implement the iommufd backend

>-Original Message- >From: Cédric Le Goater >Sent: Monday, November 13, 2023 7:05 PM >Subject: Re: [PATCH v5 03/20] vfio/iommufd: Implement the iommufd backend > >On 11/10/23 11:18, Duan, Zhenzhong wrote: >> >> >>> -Original Message- >>> From: Cédric Le Goater >>> Sent: Friday,

[PATCH v5] target/riscv: update checks on writing pmpcfg for Smepmp to version 1.0

Current checks on writing pmpcfg for Smepmp follows Smepmp version 0.9.1. However, Smepmp specification has already been ratified, and there are some differences between version 0.9.1 and 1.0. In this commit we update the checks of writing pmpcfg to follow Smepmp version 1.0. When mseccfg.MML is

[PATCH v5 06/14] tpm-sysbus: add plug handler for TPM on SysBus

TPM needs to know its own base address in order to generate its DSDT device entry. Signed-off-by: Joelle van Dyne Reviewed-by: Stefan Berger --- include/sysemu/tpm.h | 4 hw/tpm/tpm-sysbus.c | 47 hw/tpm/meson.build | 1 + 3 files changed,

[PATCH] linux-headers: Synchronize linux headers from linux v6.7.0-rc1

Use the scripts/update-linux-headers.sh to synchronize linux headers from linux v6.7.0-rc1. We mainly want to add the loongarch linux headers and then add the loongarch kvm support based on it. Signed-off-by: Tianrui Zhao --- include/standard-headers/drm/drm_fourcc.h | 2 +

[PATCH v5 11/14] tpm_crb_sysbus: introduce TPM CRB SysBus device

This SysBus variant of the CRB interface supports dynamically locating the MMIO interface so that Virt machines can use it. This interface is currently the only one supported by QEMU that works on Windows 11 ARM64 as 'tpm-tis-device' does not work with current Windows drivers. We largely follow

[PATCH v5 04/14] tpm_crb: use a single read-as-mem/write-as-mmio mapping

On Apple Silicon, when Windows performs a LDP on the CRB MMIO space, the exception is not decoded by hardware and we cannot trap the MMIO read. This led to the idea from @agraf to use the same mapping type as ROM devices: namely that reads should be seen as memory type and writes should trap as

[PATCH v5 02/14] tpm_crb: CTRL_RSP_ADDR is 64-bits wide

The register is actually 64-bits but in order to make this more clear than the specification, we define two 32-bit registers: CTRL_RSP_LADDR and CTRL_RSP_HADDR to match the CTRL_CMD_* naming. This deviates from the specs but is way more clear. Previously, the only CRB device uses a fixed system

[PATCH v5 08/14] hw/loongarch/virt: connect TPM to platform bus

Signed-off-by: Joelle van Dyne Reviewed-by: Stefan Berger --- hw/loongarch/virt.c | 7 +++ hw/loongarch/Kconfig | 1 + 2 files changed, 8 insertions(+) diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index 4b7dc67a2d..feed0f8bbf 100644 --- a/hw/loongarch/virt.c +++

[PATCH v5 03/14] tpm_ppi: refactor memory space initialization

Instead of calling `memory_region_add_subregion` directly, we defer to the caller to do it. This allows us to re-use the code for a SysBus device. Signed-off-by: Joelle van Dyne Reviewed-by: Stefan Berger --- hw/tpm/tpm_ppi.h| 10 +++--- hw/tpm/tpm_crb.c| 4 ++--

[PATCH v5 12/14] tests: acpi: implement TPM CRB tests for ARM virt

Signed-off-by: Joelle van Dyne Reviewed-by: Stefan Berger --- tests/qtest/bios-tables-test.c | 43 -- 1 file changed, 41 insertions(+), 2 deletions(-) diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index 71af5cf69f..bb4ebf00c1

[PATCH v5 01/14] tpm_crb: refactor common code

In preparation for the SysBus variant, we move common code styled after the TPM TIS devices. To maintain compatibility, we do not rename the existing tpm-crb device. Signed-off-by: Joelle van Dyne Reviewed-by: Stefan Berger --- docs/specs/tpm.rst | 1 + hw/tpm/tpm_crb.h| 76

[PATCH v5 05/14] tpm_crb: move ACPI table building to device interface

This logic is similar to TPM TIS ISA device. Since TPM CRB can only support TPM 2.0 backends, we check for this in realize. Signed-off-by: Joelle van Dyne --- hw/tpm/tpm_crb.h| 2 ++ hw/i386/acpi-build.c| 16 +--- hw/tpm/tpm_crb.c| 16

[PATCH v5 10/14] tests: acpi: prepare for TPM CRB tests

Signed-off-by: Joelle van Dyne Reviewed-by: Stefan Berger --- tests/qtest/bios-tables-test-allowed-diff.h | 4 tests/data/acpi/q35/DSDT.crb.tpm2 | 0 tests/data/acpi/q35/TPM2.crb.tpm2 | 0 tests/data/acpi/virt/DSDT.crb-device.tpm2 | 0

[PATCH v5 13/14] tests: acpi: updated expected blobs for TPM CRB

Signed-off-by: Joelle van Dyne Tested-by: Stefan Berger --- tests/qtest/bios-tables-test-allowed-diff.h | 4 tests/data/acpi/q35/DSDT.crb.tpm2 | Bin 0 -> 8355 bytes tests/data/acpi/q35/TPM2.crb.tpm2 | Bin 0 -> 76 bytes tests/data/acpi/virt/DSDT.crb-device.tpm2 |

[PATCH v5 14/14] tests: add TPM-CRB sysbus tests for aarch64

- Factor out common test code from tpm-crb-test.c -> tpm-tests.c - Store device addr in `tpm_device_base_addr` (unify with TIS tests) - Add new tests for aarch64 Signed-off-by: Joelle van Dyne Reviewed-by: Stefan Berger --- tests/qtest/tpm-tests.h | 2 +

[PATCH v5 09/14] tpm_tis_sysbus: move DSDT AML generation to device

This reduces redundant code in different machine types with ACPI table generation. Additionally, this will allow us to support different TPM interfaces with the same AML logic. Finally, this matches up with the TPM TIS ISA implementation. Ideally, we would be able to call `qbus_build_aml` and

[PATCH v5 00/14] tpm: introduce TPM CRB SysBus device

The impetus for this patch set is to get TPM 2.0 working on Windows 11 ARM64. Windows' tpm.sys does not seem to work on a TPM TIS device (as verified with VMWare's implementation). However, the current TPM CRB device uses a fixed system bus address that is reserved for RAM in ARM64 Virt machines.

[PATCH v5 07/14] hw/arm/virt: connect TPM to platform bus

Signed-off-by: Joelle van Dyne Reviewed-by: Stefan Berger --- hw/arm/virt.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 85e3c5ba9d..36e2506420 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -2811,6 +2811,13 @@ static void

Re: [RFC PATCH 1/2] migration: Report error in incoming migration

Peter Xu writes: > On Fri, Nov 10, 2023 at 07:58:00AM -0300, Fabiano Rosas wrote: >> Peter Xu writes: >> >> > On Thu, Nov 09, 2023 at 01:58:55PM -0300, Fabiano Rosas wrote: >> >> We're not currently reporting the errors set with migrate_set_error() >> >> when incoming migration fails. >> >>

Re: [RFC PATCH 2/2] migration/multifd: Move semaphore release into main thread

Peter Xu writes: > On Fri, Nov 10, 2023 at 09:05:41AM -0300, Fabiano Rosas wrote: > > [...] > >> > Then assuming we have a clear model with all these threads issue fixed (no >> > matter whether we'd shrink 2N threads into N threads), then what we need to >> > do, IMHO, is making sure to join()

Re: [PATCH v4 04/14] tpm_crb: use a single read-as-mem/write-as-mmio mapping

On Wed, Nov 1, 2023 at 2:25 PM Stefan Berger wrote: > > > > On 10/31/23 00:00, Joelle van Dyne wrote: > > On Apple Silicon, when Windows performs a LDP on the CRB MMIO space, > > the exception is not decoded by hardware and we cannot trap the MMIO > > read. This led to the idea from @agraf to use

RE: [PATCH v5 03/11] hw/misc: Add qtest for NPCM7xx PCI Mailbox

-Original Message- From: Nabih Estefan Sent: Saturday, October 28, 2023 1:55 AM To: peter.mayd...@linaro.org Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org; CS20 KFTing ; wuhao...@google.com; jasonw...@redhat.com; IS20 Avi Fishman ; nabiheste...@google.com; CS20 KWLiu ; IS20 Tomer

[PATCH 1/2] vhost: Add worker backend callouts

This adds the vhost backend callouts for the worker ioctls added in the 6.4 linux kernel commit: c1ecd8e95007 ("vhost: allow userspace to create workers") Signed-off-by: Mike Christie --- hw/virtio/vhost-backend.c | 28 include/hw/virtio/vhost-backend.h |

[PATCH 0/2] vhost-scsi: Support worker ioctls

The following patches allow users to configure the vhost worker threads for vhost-scsi. With vhost-net we get a worker thread per rx/tx virtqueue pair, but for vhost-scsi we get one worker for all workqueues. This becomes a bottlneck after 2 queues are used. In the upstream linux kernel commit:

[PATCH 2/2] vhost-scsi: Add support for a worker thread per virtqueue

This adds support for vhost-scsi to be able to create a worker thread per virtqueue. Right now for vhost-net we get a worker thread per tx/rx virtqueue pair which scales nicely as we add more virtqueues and CPUs, but for scsi we get the single worker thread that's shared by all virtqueues. When

Add new qmp json is not setting command errp

I am attempting to add a new json file for qmp. My issue is that errp is null so when I call error_setg qemu crashes. Specifically QEMU: F 00:00:1699907518.054094 2802908 logging.cc:57] assert.h assertion failed at qemu/util/error.c:59 in void error_setv(Error **, const char *, int, const

Re: [PATCH v2 3/3] hw/ide/via: implement legacy/native mode switching

On Mon, 13 Nov 2023, Mark Cave-Ayland wrote: On 07/11/2023 10:43, Kevin Wolf wrote: Am 06.11.2023 um 17:13 hat BALATON Zoltan geschrieben: On Mon, 6 Nov 2023, Kevin Wolf wrote: Am 25.10.2023 um 00:40 hat Mark Cave-Ayland geschrieben: Allow the VIA IDE controller to switch between both legacy

Re: [PATCH v2 1/3] ide/pci.c: introduce pci_ide_update_mode() function

On Mon, 13 Nov 2023, Mark Cave-Ayland wrote: On 07/11/2023 11:11, Kevin Wolf wrote: Am 06.11.2023 um 23:41 hat Mark Cave-Ayland geschrieben: On 06/11/2023 14:12, Kevin Wolf wrote: Hi Kevin, Thanks for taking the time to review this. I'll reply inline below. Am 25.10.2023 um 00:40 hat Mark

Re: [PATCH v4 02/33] hw/cpu: Call object_class_is_abstract() once in cpu_class_by_name()

On 11/7/23 00:40, Igor Mammedov wrote: On Thu, 2 Nov 2023 10:24:29 +1000 Gavin Shan wrote: From: Philippe Mathieu-Daudé Let CPUClass::class_by_name() handlers to return abstract classes, and filter them once in the public cpu_class_by_name() method. Signed-off-by: Philippe Mathieu-Daudé

Re: [PATCH v4 01/33] target/alpha: Tidy up alpha_cpu_class_by_name()

On 11/7/23 00:22, Igor Mammedov wrote: On Thu, 2 Nov 2023 10:24:28 +1000 Gavin Shan wrote: From: Philippe Mathieu-Daudé For target/alpha, the default CPU model name is "ev67". The default CPU model is used when no matching CPU model is found. The conditions to fall back to the default CPU

Re: [PATCH v2 13/17] hw/cxl: Add support for device sanitation

On Tue, Oct 24, 2023 at 1:14 AM Jonathan Cameron wrote: > > From: Davidlohr Bueso > > Make use of the background operations through the sanitize command, per CXL > 3.0 specs. Traditionally run times can be rather long, depending on the > size of the media. > > Estimate times based on: >

[PATCH v2] test/qtest: Add API functions to capture IRQ toggling

Currently, the QTest API does not provide a function to capture when an IRQ line is raised or lowered, although the QTest Protocol already reports such IRQ transitions. As a consequence, it is also not possible to capture when an IRQ line is toggled. Functions like qtest_get_irq() only read the

Re: [RFC PATCH v2 1/4] migration/multifd: Stop setting p->ioc before connecting

On Fri, Nov 10, 2023 at 05:02:38PM -0300, Fabiano Rosas wrote: > This is being shadowed but the assignments at > multifd_channel_connect() and multifd_tls_channel_connect() . > > Signed-off-by: Fabiano Rosas Reviewed-by: Peter Xu -- Peter Xu

Re: [PATCH] spelling: hw/audio/virtio-snd.c: initalize

On 13/11/23 22:20, Michael Tokarev wrote: Fixes: eb9ad377bb94 "virtio-sound: handle control messages and streams" Signed-off-by: Michael Tokarev --- hw/audio/virtio-snd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH v2 2/2] s390x/pci: only limit DMA aperture if vfio DMA limit reported

On 11/13/23 4:24 PM, Michael Tokarev wrote: > 10.11.2023 20:51, Matthew Rosato wrote: >> If the host kernel lacks vfio DMA limit reporting, do not attempt >> to shrink the guest DMA aperture. >> >> Fixes: df202e3ff3 ("s390x/pci: shrink DMA aperture to be bound by vfio DMA >> limit") >>

[PATCH for-9.0 2/6] target/riscv/tcg: do not use "!generic" CPU checks

Our current logic in get/setters of MISA and multi-letter extensions works because we have only 2 CPU types, generic and vendor, and by using "!generic" we're implying that we're talking about vendor CPUs. When adding a third CPU type this logic will break so let's handle it beforehand. In

[PATCH for-9.0 3/6] target/riscv/tcg: update priv_ver on user_set extensions

We'll add a new bare CPU type that won't have any default priv_ver. This means that the CPU will default to priv_ver = 0, i.e. 1.10.0. At the same we'll allow these CPUs to enable extensions at will, but then, if the extension has a priv_ver newer than 1.10, we'll end up disabling it. Users will

[PATCH for-9.0 5/6] target/riscv: add rv32i CPU

Add a bare bones 32 bit CPU, like we already did with rv64i, to ease the pain of users trying to build a CPU from scratch and having to disable the defaults we have with the regular rv32 CPU. See: https://lore.kernel.org/qemu-riscv/258be47f-97be-4308-bed5-dc34ef7ff954@Spark/ For a use case

[PATCH for-9.0 6/6] target/riscv: add rv32e/rv64e CPUs

In our internals we'll never allow RVI and RVE to be enabled at the same time, and we require either RVI or RVE to be enabled to proceed with machine boot. And all CPUs we have enables RVI by default. This means that if one wants to create an embedded CPU he'll need to disable RVI first then

[PATCH for-9.0 4/6] target/riscv: add rv64i CPU

We don't have any form of a 'bare bones' CPU. rv64, our default CPUs, comes with a lot of defaults. This is fine for most regular uses but it's not suitable when more control of what is actually loaded in the CPU is required. A bare-bones CPU would be annoying to deal with if not by profile

[PATCH for-9.0 0/6] riscv: rv32i,rv32e,rv64i and rv64e CPUs

Hi, This series adds canonical/bare bones RISC-V CPUs in QEMU. The idea is to allow users to create a CPU from scratch without having to deal/disable existing defaults. A bare-bones CPU will avoid scenarios like the one described here:

[PATCH for-9.0 1/6] target/riscv: create TYPE_RISCV_VENDOR_CPU

We want to add a new CPU type for bare CPUs that will inherit specific traits of the 2 existing types: - it will allow for extensions to be enabled/disabled, like generic CPUs; - it will NOT inherit defaults, like vendor CPUs. We can make this conditions met by adding an explicit type for the

Re: [PATCH] spelling: hw/audio/virtio-snd.c: initalize

Am 13.11.23 um 22:20 schrieb Michael Tokarev: Fixes: eb9ad377bb94 "virtio-sound: handle control messages and streams" Signed-off-by: Michael Tokarev --- hw/audio/virtio-snd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/audio/virtio-snd.c b/hw/audio/virtio-snd.c

Re: [PATCH v2 1/3] ide/pci.c: introduce pci_ide_update_mode() function

On 07/11/2023 11:11, Kevin Wolf wrote: Am 06.11.2023 um 23:41 hat Mark Cave-Ayland geschrieben: On 06/11/2023 14:12, Kevin Wolf wrote: Hi Kevin, Thanks for taking the time to review this. I'll reply inline below. Am 25.10.2023 um 00:40 hat Mark Cave-Ayland geschrieben: This function reads

Re: [PATCH v2 2/2] s390x/pci: only limit DMA aperture if vfio DMA limit reported

10.11.2023 20:51, Matthew Rosato wrote: If the host kernel lacks vfio DMA limit reporting, do not attempt to shrink the guest DMA aperture. Fixes: df202e3ff3 ("s390x/pci: shrink DMA aperture to be bound by vfio DMA limit") Signed-off-by: Matthew Rosato Is this stable-8.1 material? Thanks,

[PATCH] spelling: hw/audio/virtio-snd.c: initalize

Fixes: eb9ad377bb94 "virtio-sound: handle control messages and streams" Signed-off-by: Michael Tokarev --- hw/audio/virtio-snd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/audio/virtio-snd.c b/hw/audio/virtio-snd.c index a18a9949a7..2fe966e311 100644 ---

[PATCH] spelling: qapi/migration.json: transfering

Fixes: 074dbce5fcce "migration: New migrate and migrate-incoming argument 'channels'" Signed-off-by: Michael Tokarev --- qapi/migration.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qapi/migration.json b/qapi/migration.json index 975761eebd..eb2f883513 100644 ---

Re: Instruction virtual address in TCG Plugins

Mikhail Tyutin writes: > Greetings, > > What is the right way to get virtual address of either translation block or > instruction inside of TCG plugin? Does > plugin API allow that or it needs some extension? > > So far I use qemu_plugin_tb_vaddr() inside of my block translation callback > to

Re: [PATCH v2 3/3] hw/ide/via: implement legacy/native mode switching

On 07/11/2023 10:43, Kevin Wolf wrote: Am 06.11.2023 um 17:13 hat BALATON Zoltan geschrieben: On Mon, 6 Nov 2023, Kevin Wolf wrote: Am 25.10.2023 um 00:40 hat Mark Cave-Ayland geschrieben: Allow the VIA IDE controller to switch between both legacy and native modes by calling

Re: [PATCH] MAINTAINERS: update virtio-fs mailing list address

Applied. Stefan

Re: [QEMU][PATCHv2 0/8] Xen: support grant mappings.

On Fri, 2023-10-27 at 07:27 +0200, Juergen Gross wrote: > On 26.10.23 22:56, Stefano Stabellini wrote: > > On Thu, 26 Oct 2023, David Woodhouse wrote: > > > On Thu, 2023-10-26 at 13:36 -0700, Stefano Stabellini wrote: > > > > > > > > > This seems like a lot of code to replace that simpler

[PATCH] migration: fix coverity migrate_mode finding

Coverity diagnoses a possible out-of-range array index here ... static GSList *migration_blockers[MIG_MODE__MAX]; fill_source_migration_info() { GSList *cur_blocker = migration_blockers[migrate_mode()]; ... because it does not know that MIG_MODE__MAX will never be returned as a

[PATCH V7 7/8] gdbstub: Add helper function to unregister GDB register space

Add common function to help unregister the GDB register space. This shall be done in context to the CPU unrealization. Signed-off-by: Salil Mehta Tested-by: Vishnu Pajjuri Reviewed-by: Gavin Shan Tested-by: Xianglai Li Tested-by: Miguel Luis Reviewed-by: Shaoqin Huang --- gdbstub/gdbstub.c

[PATCH V7 8/8] docs/specs/acpi_hw_reduced_hotplug: Add the CPU Hotplug Event Bit

GED interface is used by many hotplug events like memory hotplug, NVDIMM hotplug and non-hotplug events like system power down event. Each of these can be selected using a bit in the 32 bit GED IO interface. A bit has been reserved for the CPU hotplug event. Signed-off-by: Salil Mehta ---

[PATCH V7 6/8] physmem: Add helper function to destroy CPU AddressSpace

Virtual CPU Hot-unplug leads to unrealization of a CPU object. This also involves destruction of the CPU AddressSpace. Add common function to help destroy the CPU AddressSpace. Signed-off-by: Salil Mehta Tested-by: Vishnu Pajjuri Reviewed-by: Gavin Shan Tested-by: Xianglai Li Tested-by:

[PATCH V7 5/8] hw/acpi: Update CPUs AML with cpu-(ctrl)dev change

CPUs Control device(\\_SB.PCI0) register interface for the x86 arch is IO port based and existing CPUs AML code assumes _CRS objects would evaluate to a system resource which describes IO Port address. But on ARM arch CPUs control device(\\_SB.PRES) register interface is memory-mapped hence _CRS

[PATCH V7 4/8] hw/acpi: Update GED _EVT method AML with CPU scan

OSPM evaluates _EVT method to map the event. The CPU hotplug event eventually results in start of the CPU scan. Scan figures out the CPU and the kind of event(plug/unplug) and notifies it back to the guest. Update the GED AML _EVT method with the call to \\_SB.CPUS.CSCN Also, macro

[PATCH V7 3/8] hw/acpi: Update ACPI GED framework to support vCPU Hotplug

ACPI GED (as described in the ACPI 6.4 spec) uses an interrupt listed in the _CRS object of GED to intimate OSPM about an event. Later then demultiplexes the notified event by evaluating ACPI _EVT method to know the type of event. Use ACPI GED to also notify the guest kernel about any CPU

[PATCH V7 2/8] hw/acpi: Move CPU ctrl-dev MMIO region len macro to common header file

CPU ctrl-dev MMIO region length could be used in ACPI GED and various other architecture specific places. Move ACPI_CPU_HOTPLUG_REG_LEN macro to more appropriate common header file. Signed-off-by: Salil Mehta Reviewed-by: Alex Bennée Reviewed-by: Jonathan Cameron Reviewed-by: Gavin Shan

Re: [PATCH-for-9.0 01/10] sysemu/xen: Forbid using Xen headers in user emulation

On Mon, 2023-11-13 at 16:21 +0100, Philippe Mathieu-Daudé wrote: > Xen is a system specific accelerator, it makes no sense > to include its headers in user emulation. > > Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: David Woodhouse smime.p7s Description: S/MIME cryptographic

[PATCH V7 1/8] accel/kvm: Extract common KVM vCPU {creation, parking} code

KVM vCPU creation is done once during the vCPU realization when Qemu vCPU thread is spawned. This is common to all the architectures as of now. Hot-unplug of vCPU results in destruction of the vCPU object in QOM but the corresponding KVM vCPU object in the Host KVM is not destroyed as KVM doesn't

[PATCH V7 0/8] Add architecture agnostic code to support vCPU Hotplug

Virtual CPU hotplug support is being added across various architectures[1][3]. This series adds various code bits common across all architectures: 1. vCPU creation and Parking code refactor [Patch 1] 2. Update ACPI GED framework to support vCPU Hotplug [Patch 2,3] 3. ACPI CPUs AML code change

Re: [PATCH-for-9.0 10/10] hw/xen: Have most of Xen files become target-agnostic

On Mon, 2023-11-13 at 16:21 +0100, Philippe Mathieu-Daudé wrote: > Previous commits re-organized the target-specific bits > from Xen files. We can now build the common files once > instead of per-target. > > Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: David Woodhouse smime.p7s

Re: [PATCH-for-9.0 09/10] hw/xen: Extract 'xen_igd.h' from 'xen_pt.h'

On Mon, 2023-11-13 at 16:21 +0100, Philippe Mathieu-Daudé wrote: > "hw/xen/xen_pt.h" requires "hw/xen/xen_native.h" which is target > specific. It also declares IGD methods, which are not target > specific. > > Target-agnostic code can use IGD methods. To allow that, extract > these methos into a

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