On 2023/12/17 20:39, BALATON Zoltan wrote:
On Sun, 17 Dec 2023, Akihiko Odaki wrote:
This change brings two new features:
- The window will be resizable if "Zoom To Fit" is eanbled
- The window can be made full screen by clicking full screen button
provided by the platform. (The left-top green
Evaluate [normalWindow styleMask] & NSWindowStyleMaskResizable instead.
Signed-off-by: Akihiko Odaki
---
ui/cocoa.m | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/ui/cocoa.m b/ui/cocoa.m
index 1357690e50ca..05f7854f9819 100644
--- a/ui/cocoa.m
+++ b/ui/cocoa.m
@@ -103
This change brings two new features:
- The window will be resizable if "Zoom To Fit" is eanbled
- The window can be made full screen by clicking full screen button
provided by the platform. (The left-top green button.)
Signed-off-by: Akihiko Odaki
Tested-by: Rene Engel
---
ui/cocoa.m | 458 ++
ui/cocoa used to release all mouse buttons when it sees
NSEventTypeLeftMouseUp, NSEventTypeRightMouseUp, or
NSEventTypeOtherMouseUp, but it can instead release specific one
according to the delivered event.
Signed-off-by: Akihiko Odaki
---
ui/cocoa.m | 132 ++-
V5 -> V6:
Rebased.
Signed-off-by: Akihiko Odaki
---
Changes in v8:
- Split into three patches. (BALATON Zoltan)
- Removed negative full-screen conditions. (BALATON Zoltan)
- Converted a C++-style comment to C style.
- Link to v7:
https://lore.kernel.org/r/20231217-cocoa-v7-1-6af21e
Generate SMBIOS tables for the RISC-V mach-virt.
Add CONFIG_SMBIOS=y to the RISC-V default config.
The implementation is based on the corresponding ARM and Loongson code.
With the patch the following firmware tables are provided:
etc/smbios/smbios-anchor
etc/smbios/smbios-tables
Booting
Hello Stefan,
Am 15.12.23 um 16:21 schrieb Stefan Hajnoczi:
Am 05.12.23 um 15:44 schrieb Stefan Hajnoczi:
On Tue, 5 Dec 2023 at 04:53, Philipp Hahn wrote:
>
by accident I stumbled over "VMware Instant Clone" ¹, which allows
cloning of running VMs by copy-on-write-sharing the disk images an
Peter Maydell writes:
> On Thu, 14 Dec 2023 at 17:14, Philippe Mathieu-Daudé
> wrote:
>>
>> QOM properties are added on the ARM vCPU object when a
>> feature is present. Rather than checking the property
>> is present, check the feature.
>>
>> Suggested-by: Markus Armbruster
>> Signed-off-by:
On 2023/12/18 16:06, Marc-André Lureau wrote:
Hi
On Sun, Dec 17, 2023 at 10:14 AM Akihiko Odaki wrote:
ui/dbusaudio.c does not depend on ui/dbus.h
It uses dbus_win32_import_socket()
Oops. I withdraw this patch. Please dismiss it and review only the first
one.
Hi
On Sun, Dec 17, 2023 at 10:14 AM Akihiko Odaki wrote:
>
> ui/dbusaudio.c does not depend on ui/dbus.h
>
It uses dbus_win32_import_socket()
> Signed-off-by: Akihiko Odaki
> ---
> audio/dbusaudio.c | 1 -
> audio/meson.build | 2 +-
> 2 files changed, 1 insertion(+), 2 deletions(-)
>
> diff
Could this go via qemu-trivial?
Akihiko Odaki writes:
> For the context, see:
> https://lore.kernel.org/all/e3839467-6d4c-e8e6-9247-a71fafe55...@eik.bme.hu/
>
> Signed-off-by: Akihiko Odaki
> ---
> Akihiko Odaki (2):
> qemu-options: Unify the help entries for cocoa
> qemu-options: T
misa_mxl_max is now a class member and initialized only once for each
class. This also moves the initialization of gdb_core_xml_file which
will be referenced before realization in the future.
Signed-off-by: Akihiko Odaki
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 21
It is initialized with a simple assignment and there is little room for
error. In fact, the validation is even more complex.
Signed-off-by: Akihiko Odaki
Acked-by: LIU Zhiwei
Reviewed-by: Daniel Henrique Barboza
Acked-by: Alistair Francis
---
target/riscv/tcg/tcg-cpu.c | 15 +++
1
misa_mxl_max is common for all instances of a RISC-V CPU class so they
are better put into class.
Signed-off-by: Akihiko Odaki
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h | 4 +-
target/riscv/cpu.c | 118 +++--
target/riscv/gdbs
A later commit requires one extra step to retrieve misa_mxl_max. As
misa_mxl is semantically more correct and does not need such a extra
step, refer to misa_mxl instead. Below is the explanation why misa_mxl
is more semantically correct to refer to than misa_mxl_max in this case.
Currently misa_mx
This series extracts fixes and refactorings that can be applied
independently from "[PATCH v9 00/23] plugins: Allow to read registers".
The patch "target/riscv: Move MISA limits to class" was replaced with
patch "target/riscv: Move misa_mxl_max to class" since I found instances
may have different
On Wed, Dec 13, 2023 at 10:35:33AM -0500, Steven Sistare wrote:
> Hi Peter, all have RB's, with all i's dotted and t's crossed - steve
Yes this seems to be more migration related so maybe good candidate for a
pull from migration submodule.
But since this is still solving a generic issue, I'm copy
> -Original Message-
> From: Alistair Francis
> Sent: Monday, December 18, 2023 12:46 PM
> To: Alvin Che-Chia Chang(張哲嘉)
> Cc: qemu-ri...@nongnu.org; qemu-devel@nongnu.org;
> alistair.fran...@wdc.com; bin.m...@windriver.com; liwei1...@gmail.com;
> dbarb...@ventanamicro.com; zhiwei_...@lin
On Sun, Dec 17, 2023 at 5:17 PM Alvin Chang via wrote:
>
> The debug Sdtrig extension defines an optional CSR "mcontext". Since it
> is optional, this commit adds new CPU configuration
> "ext_sdtrig_mcontext" and uses property "sdtrig_mcontext" to control
> whether it is implemented or not. Its pr
On Fri, Dec 8, 2023 at 10:09 PM Conor Dooley wrote:
>
> From: Conor Dooley
>
> A few months ago I submitted a patch to various lists, deprecating
> "riscv,isa" with a lengthy commit message [0] that is now commit
> aeb71e42caae ("dt-bindings: riscv: deprecate riscv,isa") in the Linux
> kernel tre
On Wed, Nov 22, 2023 at 3:36 PM Ethan Chen via wrote:
>
> This series implements IOPMP specification v1.0.0-draft4 rapid-k model.
> The specification url:
> https://github.com/riscv-non-isa/iopmp-spec/blob/main/riscv_iopmp_specification.pdf
>
> When IOPMP is enabled, a DMA device ATCDMAC300 is add
On Wed, Nov 22, 2023 at 3:36 PM Ethan Chen via wrote:
>
> If a source device is connected to the IOPMP device, its memory access will be
> checked by the IOPMP rule.
>
> - Add 'iopmp=on' option to add an iopmp device and a dma device which is
> connected to the iopmp to machine. This option is a
On Wed, Nov 22, 2023 at 3:35 PM Ethan Chen via wrote:
>
> ATCDMAC300 is a direct memory access controller (DMAC) which transfers data
> efficiently between devices on the AMBA AXI4 bus.
>
> ATCDMAC300 supports up to 8 DMA channels. Each DMA channel provides a set of
> registers to describe the int
On Wed, Nov 22, 2023 at 3:35 PM Ethan Chen via wrote:
>
> Support specification Version 1.0.0-draft4 rapid-k model.
> The specification url:
> https://github.com/riscv-non-isa/iopmp-spec/blob/main/riscv_iopmp_specification.pdf
>
> IOPMP check memory access from deivce is valid or not. This impleme
On Wed, Nov 22, 2023 at 3:36 PM Ethan Chen via wrote:
>
> Make other device can use /hw/core/stream.c by select this config.
Ensure other devices can use /hw/core/stream.c by selecting this config.
>
> Signed-off-by: Ethan Chen
Otherwise:
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/
On Mon, Dec 11, 2023 at 5:06 AM ~inesvarhol wrote:
>
> From: Inès Varhol
>
> Signed-off-by: Arnaud Minier
> Signed-off-by: Inès Varhol
> ---
> hw/arm/Kconfig | 1 +
> hw/arm/stm32l4x5_soc.c | 24
> include/hw/arm/stm32l4x5_soc.h | 2 ++
> 3 fi
On Mon, Dec 11, 2023 at 5:07 AM ~inesvarhol wrote:
>
> From: Inès Varhol
>
> Signed-off-by: Arnaud Minier
> Signed-off-by: Inès Varhol
Acked-by: Alistair Francis
Alistair
> ---
> tests/qtest/meson.build | 3 +-
> tests/qtest/stm32l4xx_syscfg-test.c | 408 +
On Mon, Dec 11, 2023 at 5:06 AM ~inesvarhol wrote:
>
> From: Inès Varhol
>
> Signed-off-by: Arnaud Minier
> Signed-off-by: Inès Varhol
> ---
> hw/misc/Kconfig| 3 +
> hw/misc/meson.build| 1 +
> hw/misc/stm32l4xx_syscfg.c | 277 ++
On 11/14/2023 13:40, Hao Xiang wrote:> 1. Refactor multifd_send_thread function.
> 2. Implement buffer_is_zero_use_cpu to handle CPU based zero page
> checking.
> 3. Introduce the batch task structure in MultiFDSendParams.
>
> Signed-off-by: Hao Xiang
> ---
> migration/multifd.c | 82 +++
On Fri, Dec 1, 2023 at 4:29 AM Daniel Henrique Barboza
wrote:
>
> Hi,
>
> This series adds RVV, vstart, vl and vtype regs to the KVM driver.
>
> But first we need a couple of things done. We need 'ptrace.h' RISC-V
> linux-header to be able to read/write RVV CSRs. This is done in patch 2.
> Patch 1
On Fri, Dec 15, 2023 at 4:34 PM Akihiko Odaki wrote:
>
> On 2023/12/15 14:34, Alistair Francis wrote:
> > On Thu, Nov 23, 2023 at 5:24 PM Akihiko Odaki
> > wrote:
> >>
> >> On 2023/11/23 12:04, Alistair Francis wrote:
> >>> On Mon, Oct 30, 2023 at 3:50 PM Akihiko Odaki
> >>> wrote:
>
> >>
On Sat, Dec 16, 2023 at 11:52 PM Alexey Baturo wrote:
>
> From: Alexey Baturo
>
> Hi all,
>
> It looks like Zjpm v0.8 is almost frozen and we don't expect it change
> drastically anymore.
> Compared to the original implementation with explicit base and mask CSRs, we
> now only have
> several fi
On 11/14/2023 13:40, Hao Xiang wrote:
> Intel DSA offloading is an optional feature that turns on if
> proper hardware and software stack is available. To turn on
> DSA offloading in multifd live migration:
>
> multifd-dsa-accel="[dsa_dev_path1] ] [dsa_dev_path2] ... [dsa_dev_pathX]"
Nit: a redun
On Sat, Dec 16, 2023 at 11:52 PM Alexey Baturo wrote:
>
> From: Alexey Baturo
>
> Zjpm v0.8 is almost frozen and it's much simplier compared to the existing
> one:
> The newer version doesn't allow to specify custom mask or base for masking.
> Instead it allows only certain options for masking t
On 11/14/2023 13:40, Hao Xiang wrote:> * Create a dedicated thread for DSA task
completion.
> * DSA completion thread runs a loop and poll for completed tasks.
> * Start and stop DSA completion thread during DSA device start stop.
>
> User space application can directly submit task to Intel DSA
>
On Fri, Dec 8, 2023 at 3:07 AM Rob Bradford wrote:
>
> Signed-off-by: Rob Bradford
Reviewed-by: Alistair Francis
Alistair
> ---
> disas/riscv.c | 9 +
> 1 file changed, 9 insertions(+)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index e9458e574b..8a546d5ea5 100644
> --- a/disas/
On Fri, Dec 8, 2023 at 1:40 AM Rob Bradford wrote:
>
> From: Weiwei Li
>
> Add support for amocas.w/d/q instructions which are part of the ratified
> Zacas extension: https://github.com/riscv/riscv-zacas
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
> Signed-off-by: Rob Bradford
On Thu, Dec 14, 2023 at 6:18 PM Yuri Benditovich
wrote:
>
> Hi Jason,
> As we anyway missed the timeframe of 8.2 please remove this v7 series from
> the pull, we will send v8 in which we want to take in account most of Akihiko
> comments (especially DEFINE_PROP_ARRAY and naming of the properties
On 11/14/2023 13:40, Hao Xiang wrote:> From: Juan Quintela
>
> This implements the zero page dection and handling.
s/dection/detection
>
> Signed-off-by: Juan Quintela
> ---
> migration/multifd.c | 41 +++--
> migration/multifd.h | 5 +
[...]
> +
On Wed, Dec 13, 2023 at 5:49 PM Akihiko Odaki wrote:
>
> This function is no longer used.
>
> Signed-off-by: Akihiko Odaki
> Reviewed-by: Alex Bennée
Acked-by: Alistair Francis
Alistair
> ---
> include/hw/core/cpu.h | 4
> target/arm/cpu.h | 6 --
> target/ppc/cpu.h |
On Wed, Dec 13, 2023 at 4:44 PM Akihiko Odaki wrote:
>
> GDBFeature has the num_regs member so use it where applicable to
> remove magic numbers.
>
> Signed-off-by: Akihiko Odaki
Acked-by: Alistair Francis
Alistair
> ---
> include/hw/core/cpu.h | 3 ++-
> target/s390x/cpu.h | 2 --
>
On Wed, Dec 13, 2023 at 5:47 PM Akihiko Odaki wrote:
>
> Align the parameters of gdb_get_reg_cb and gdb_set_reg_cb with the
> gdb_read_register and gdb_write_register members of CPUClass to allow
> to unify the logic to access registers of the core and coprocessors
> in the future.
>
> Signed-off-
On Wed, Dec 13, 2023 at 4:42 PM Akihiko Odaki wrote:
>
> This is a tree-wide change to introduce GDBFeature parameter to
> gdb_register_coprocessor(). The new parameter just replaces num_regs
> and xml parameters for now. GDBFeature will be utilized to simplify XML
> lookup in a following change.
On Wed, Dec 13, 2023 at 4:43 PM Akihiko Odaki wrote:
>
> In preparation for a change to use GDBFeature as a parameter of
> gdb_register_coprocessor(), convert the internal representation of
> dynamic feature from plain XML to GDBFeature.
>
> Signed-off-by: Akihiko Odaki
Acked-by: Alistair Franci
On Sat, Dec 9, 2023 at 4:40 AM Daniel Henrique Barboza
wrote:
>
> Hi,
>
> While working in a follow-up for the Vector KVM regs, where we would
> read 'vlenb' and then all other vregs [1], Drew noticed that we're using
> kvm_riscv_reg_id() in registers that are u32 and u64.
>
> The helper is return
Am 17. Dezember 2023 15:47:33 UTC schrieb BALATON Zoltan :
>On Sun, 17 Dec 2023, Bernhard Beschow wrote:
>> Exposing the internal header allows for exposing struct FDCtrlISABus which is
>> encuraged by qdev guidelines.
>
>Hopefully the guidelines don't encourage this as object orientation indeed
On Tue, Dec 12, 2023 at 3:08 AM Daniel Henrique Barboza
wrote:
>
> mvendorid is an uint32 property, mimpid/marchid are uint64 properties.
> But their getters are returning bools. The reason this went under the
> radar for this long is because we have no code using the getters.
>
> The problem can
On Tue, Dec 12, 2023 at 3:08 AM Daniel Henrique Barboza
wrote:
>
> mvendorid is an uint32 property, mimpid/marchid are uint64 properties.
> But their getters are returning bools. The reason this went under the
> radar for this long is because we have no code using the getters.
>
> The problem can
On Thu, Nov 23, 2023 at 7:13 PM Ivan Klokov wrote:
>
> The Sv32 page-based virtual-memory scheme described in RISCV privileged
> spec Section 5.3 supports 34-bit physical addresses for RV32, so the
> PMP scheme must support addresses wider than XLEN for RV32. However,
> PMP address register format
On Fri, Dec 15, 2023 at 12:34 PM LIU Zhiwei
wrote:
>
> If CPU does not implement the Vector extension, it usually means
> mstatus vs hardwire to zero. So we should not allow write a
> non-zero value to this field.
>
> Signed-off-by: LIU Zhiwei
Thanks!
Applied to riscv-to-apply.next
Alistair
>
On Fri, Dec 15, 2023 at 12:34 PM LIU Zhiwei
wrote:
>
> If CPU does not implement the Vector extension, it usually means
> mstatus vs hardwire to zero. So we should not allow write a
> non-zero value to this field.
>
> Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Alistair
> ---
> t
From: Joe Berthels
"info mem" now correctly displays virtual address map instead of hanging
and displaying nothing.
Signed-off-by: Joe Berthels (joe21...@gmail.com)
---
'l0' should have been shifted 48 bits to form 'end', instead of 47 bits
target/i386/monitor.c | 136 +
Hi,
I am working on qemu 6.2.0 for isa serial char device in
hw/char/serial-isa.c.
It once creates 2 ports with "1" and "2" literally. But with the
following commit
commit dcdbfaafe90a5e6e172368b2aa5500a9ca192e49
Author: Gerd Hoffmann
Date: Fri May 15 17:04:10 2020 +0200
acpi: move a
From: Joe Berthels
"info mem" now correctly displays virtual address map instead of hanging
and displaying nothing.
Signed-off-by: Joe Berthels (joe21...@gmail.com)
---
target/i386/monitor.c | 138 +-
1 file changed, 70 insertions(+), 68 deletions(-)
dif
On Sun, 17 Dec 2023, Bernhard Beschow wrote:
Exposing the internal header allows for exposing struct FDCtrlISABus which is
encuraged by qdev guidelines.
Hopefully the guidelines don't encourage this as object orientation indeed
encourages object encapsulation so only the object itseld should p
On Sun, 17 Dec 2023, Bernhard Beschow wrote:
The VIA south bridges are able to relocate and enable or disable their SuperI/O
functions. So far this is hardcoded such that all functions are always enabled
and are located at fixed addresses.
Some PC BIOSes seem to probe for I/O occupancy before ac
The VIA south bridges are able to relocate and enable or disable their SuperI/O
functions. So far this is hardcoded such that all functions are always enabled
and are located at fixed addresses.
Some PC BIOSes seem to probe for I/O occupancy before activating such a function
and issue an error in
Some SuperI/O devices such as the VIA south bridges or the PC87312 controller
are able to relocate their SuperI/O functions. Add a convenience function for
implementing this in the VIA south bridges.
This convenience function relies on previous simplifications in exec/ioport
which avoids some dupl
Rename the header which allows for exposing fdc-internal.h (dropping the
-internal suffix) which in turn allows for exposing struct FDCtrlISABus.
Exposing a device struct is in line with OOM/qdev guidelines.
Signed-off-by: Bernhard Beschow
---
MAINTAINERS | 2 +-
hw/blo
Exposing device structs in headers is encuraged by qdev guidelines.
Signed-off-by: Bernhard Beschow
---
include/hw/block/fdc-isa.h | 15 +++
hw/block/fdc-isa.c | 17 -
2 files changed, 15 insertions(+), 17 deletions(-)
diff --git a/include/hw/block/fdc-isa.h
Some SuperI/O devices such as the VIA south bridges or the PC87312 controller
allow to enable or disable their SuperI/O functions. Add a convenience function
for implementing this in the VIA south bridges.
The naming of the functions is inspired by its memory_region_set_enabled()
pendant.
Signed-
This series implements relocation of the SuperI/O functions of the VIA south
bridges which resolves some FIXME's. It is part of my via-apollo-pro-133t
branch [1] which is an extension of bringing the VIA south bridges to the PC
machine [2]. This branch is able to run some real-world X86 BIOSes in t
Exposing the internal header allows for exposing struct FDCtrlISABus which is
encuraged by qdev guidelines.
Signed-off-by: Bernhard Beschow
---
MAINTAINERS | 2 +-
hw/block/fdc-internal.h => include/hw/block/fdc.h | 4 ++--
hw/block/fdc-isa.c
portio_list_add_1() creates a MemoryRegionPortioList instance which holds a
MemoryRegion `mr` and an array of MemoryRegionPortio elements named `ports`.
Each element in the array gets assigned the same value for its .base attribute.
The same value also ends up as the .addr attribute of `mr` due to
Results running grep:
`grep -i -e "fdc" hw/ppc/prep.c`
(no output)
`grep -i -e "fdc" hw/m68k/next-cube.c`
DPRINTF("FDCSR Write: %x\n", value);
This indicates that hw/block/fdc.h isn't used there.
Signed-off-by: Bernhard Beschow
---
hw/m68k/next-cube.c | 1 -
hw/ppc/prep.c | 1 -
The MAX_FD is a limitation of struct FDCtrl which is defined in fdc.h. Now that
this header is exposed the definition can be moved there.
Signed-off-by: Bernhard Beschow
---
include/hw/block/fdc-isa.h | 3 ---
include/hw/block/fdc.h | 3 ++-
hw/block/fdc.c | 1 -
hw/i386/pc.c
Exposing device structs in headers is encuraged by qdev guidelines.
Signed-off-by: Bernhard Beschow
---
include/hw/char/serial-isa.h | 50
include/hw/char/serial.h | 7 -
hw/char/serial-isa.c | 14 +-
hw/i386/microvm-dt.c | 2
The source files are already in this section. Add the headers, too.
Signed-off-by: Bernhard Beschow
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 939f518701..69135a45b4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1827,6 +1827,7 @@ F: hw/wa
Only the source file uses fdc.h but not the header, so remove it from the public
interface.
Signed-off-by: Bernhard Beschow
---
include/hw/i386/pc.h | 1 -
hw/i386/pc.c | 1 +
2 files changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index a
On Sun, 17 Dec 2023, Akihiko Odaki wrote:
This change brings two new features:
- The window will be resizable if "Zoom To Fit" is eanbled
- The window can be made full screen by clicking full screen button
provided by the platform. (The left-top green button.)
Signed-off-by: Akihiko Odaki
Test
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