[PATCH] tcg/tci: Fix TCI on hppa host and update TCI test matrix

Update the TCI interpreter test matrix for big-endian hosts with big- (hppa, hppa64) and little-endian (x86,x96-64) targets. I used native ppc64 and hppa hosts for those tests. Starting TCI on a hppa host crashed immediately, because hppa is the only archive left where the stack grows upwards. Wri

Re: [PATCH 1/1] Leaving Migration

Bin Meng wrote: > On Wed, Jan 3, 2024 at 4:20 AM Juan Quintela wrote: >> >> I am leaving Red Hat, and as part of that I am leaving Migration >> maintenarship. > > maintainership? You are right, as usual O:-) >> >> You are left in good hands with Peter and Fabiano. >> >> Thanks for all the fish.

[PATCH] net/vmnet: Pad short Ethernet frames

At least on macOS 12.7.2, vmnet doesn't pad Ethernet frames, such as the host's ARP replies, to the minimum size (60 bytes before the frame check sequence) defined in IEEE Std 802.3-2022, so guests' Ethernet device drivers may drop them with "frame too short" errors. This patch calls eth_pad_short

Re: [PATCH v2 12/12] hw/isa/vt82c686: Implement relocation and toggling of SuperI/O functions

Am 3. Januar 2024 12:26:07 UTC schrieb BALATON Zoltan : >On Tue, 2 Jan 2024, Bernhard Beschow wrote: >> Am 24. Dezember 2023 00:51:53 UTC schrieb BALATON Zoltan >> : >>> On Tue, 19 Dec 2023, Bernhard Beschow wrote: Am 19. Dezember 2023 00:26:15 UTC schrieb BALATON Zoltan : > On M

[PATCH v4 06/11] exec/ioport: Add portio_list_set_enabled()

Some SuperI/O devices such as the VIA south bridges or the PC87312 controller allow to enable or disable their SuperI/O functions. Add a convenience function for implementing this in the VIA south bridges. The naming of the functions is inspired by its memory_region_set_enabled() pendant. Signed-

[PATCH v4 01/11] hw/block/fdc-isa: Move portio_list from FDCtrl to FDCtrlISABus

FDCtrl::portio_list isn't used inside FDCtrl context but only inside FDCtrlISABus context, so move it there. Signed-off-by: Bernhard Beschow Reviewed-by: BALATON Zoltan --- hw/block/fdc-internal.h | 2 -- hw/block/fdc-isa.c | 4 +++- 2 files changed, 3 insertions(+), 3 deletions(-) diff -

[PATCH v4 00/11] hw/isa/vt82c686: Implement relocation and toggling of SuperI/O functions

This series implements relocation of the SuperI/O functions of the VIA south bridges which resolves some FIXME's. It is part of my via-apollo-pro-133t branch [1] which is an extension of bringing the VIA south bridges to the PC machine [2]. This branch is able to run some real-world X86 BIOSes in t

[PATCH v4 03/11] hw/char/parallel: Move portio_list from ParallelState to ISAParallelState

ParallelState::portio_list isn't used inside ParallelState context but only inside ISAParallelState context, so move it there. Signed-off-by: Bernhard Beschow Reviewed-by: BALATON Zoltan --- include/hw/char/parallel-isa.h | 2 ++ include/hw/char/parallel.h | 2 -- hw/char/parallel.c

[PATCH v4 07/11] hw/block/fdc-isa: Implement relocation and enabling/disabling for TYPE_ISA_FDC

The real SuperI/O chips emulated by QEMU allow for relocating and enabling or disabling their SuperI/O functions via software. So far this is not implemented. Prepare for that by adding isa_fdc_set_{enabled,iobase}. Signed-off-by: Bernhard Beschow --- include/hw/block/fdc.h | 3 +++ hw/block/fd

[PATCH v4 10/11] hw/ppc/pegasos2: Let pegasos2 machine configure SuperI/O functions

This is a preparation for implementing relocation and toggling of SuperI/O functions in the VT8231 device model. Upon reset, all SuperI/O functions will be deactivated, so in case if no -bios is given, let the machine configure those functions the same way Pegasos II firmware would do. Signed-off-

[PATCH v4 04/11] exec/ioport: Resolve redundant .base attribute in struct MemoryRegionPortio

portio_list_add_1() creates a MemoryRegionPortioList instance which holds a MemoryRegion `mr` and an array of MemoryRegionPortio elements named `ports`. Each element in the array gets assigned the same value for its .base attribute. The same value also ends up as the .addr attribute of `mr` due to

[PATCH v4 08/11] hw/char/serial-isa: Implement relocation and enabling/disabling for TYPE_ISA_SERIAL

The real SuperI/O chips emulated by QEMU allow for relocating and enabling or disabling their SuperI/O functions via software. So far this is not implemented. Prepare for that by adding isa_serial_set_{enabled,iobase}. Signed-off-by: Bernhard Beschow --- include/hw/char/serial.h | 2 ++ hw/char

[PATCH v4 05/11] exec/ioport: Add portio_list_set_address()

Some SuperI/O devices such as the VIA south bridges or the PC87312 controller are able to relocate their SuperI/O functions. Add a convenience function for implementing this in the VIA south bridges. This convenience function relies on previous simplifications in exec/ioport which avoids some dupl

[PATCH v4 11/11] hw/isa/vt82c686: Implement relocation and toggling of SuperI/O functions

The VIA south bridges are able to relocate and toggle (enable or disable) their SuperI/O functions. So far this is hardcoded such that all functions are always enabled and are located at fixed addresses. Some PC BIOSes seem to probe for I/O occupancy before activating such a function and issue an

[PATCH v4 09/11] hw/char/parallel-isa: Implement relocation and enabling/disabling for TYPE_ISA_PARALLEL

The real SuperI/O chips emulated by QEMU allow for relocating and enabling or disabling their SuperI/O functions via software. So far this is not implemented. Prepare for that by adding isa_parallel_set_{enabled,iobase}. Signed-off-by: Bernhard Beschow --- include/hw/char/parallel-isa.h | 3 +++

[PATCH v4 02/11] hw/block/fdc-sysbus: Move iomem from FDCtrl to FDCtrlSysBus

FDCtrl::iomem isn't used inside FDCtrl context but only inside FDCtrlSysBus context, so move it there. Signed-off-by: Bernhard Beschow Reviewed-by: BALATON Zoltan --- hw/block/fdc-internal.h | 2 -- hw/block/fdc-sysbus.c | 6 -- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git

[PATCH v3 2/3] hw/arm/armv7m: alias the NVIC "num-prio-bits" property

A SoC will not have a direct access to the NVIC embedded in its ARM core. By aliasing the "num-prio-bits" property similarly to what is done for the "num-irq" one, a SoC can easily configure it on its armv7m instance. Signed-off-by: Samuel Tardieu Reviewed-by: Peter Maydell --- hw/arm/armv7m.c

[PATCH v3 1/3] hw/intc/armv7m_nvic: add "num-prio-bits" property

Cortex-M NVIC can have a different number of priority bits. Cortex-M0/M0+/M1 devices must use 2 or more bits, while devices based on ARMv7m and up must use 3 or more bits. This adds a "num-prio-bits" property which will get sensible default values if unset (2 or 8 depending on the device). Unless

[PATCH v3 0/3] Add "num-prio-bits" property for Cortex-M devices

This patch series builds on a discussion initiated by Anton Kochkov on this list in 2022. It allows setting the appropriate number of priority bits for Cortex-M devices. For example, FreeRTOS checks at startup that the right number of priority bits is available in order to guarantee its runtime str

[PATCH v3 3/3] hw/arm/socs: configure priority bits for existing SOCs

Update the number of priority bits for a number of existing SoCs according to their technical documentation: - STM32F100/F205/F405/L4x5: 4 bits - Stellaris (Sandstorm/Fury): 3 bits Signed-off-by: Samuel Tardieu Reviewed-by: Peter Maydell --- hw/arm/stellaris.c | 2 ++ hw/arm/stm32f100_soc.

Re: [PATCH v2 00/35] tcg: Introduce TCG_COND_TST{EQ,NE}

On Sat, Oct 28, 2023 at 9:45 PM Richard Henderson wrote: > > Expose a pair of comparison operators that map to the "test" > comparison that is available on many architectures. > > Changes for v2: > * Add TCGCond to tcg_target_const_match. > This fixes a long-standing issue with ppc and s390x

[PATCH v5 0/2] Add minimal support for the B-L475E-IOT01A board

This patch adds a new STM32L4x5 SoC, it is necessary to add support for the B-L475E-IOT01A board. The implementation is derived from the STM32F405 SoC and NetduinoPlus2 board. The implementation contains no peripherals, only memory regions are implemented. Changes from v5 to v4: - in `b-l475e-iot0

[PATCH v5 1/2] hw/arm: Add minimal support for the STM32L4x5 SoC

This patch adds a new STM32L4x5 SoC, it is necessary to add support for the B-L475E-IOT01A board. The implementation is derived from the STM32F405 SoC. The implementation contains no peripherals, only memory regions are implemented. Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-

[PATCH v5 2/2] hw/arm: Add minimal support for the B-L475E-IOT01A board

This commit adds a new B-L475E-IOT01A board using the STM32L475VG SoC as well as a dedicated documentation file. The implementation is derived from the Netduino Plus 2 machine. There are no peripherals implemented yet, only memory regions. Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe M

Re: [PATCH v11 0/7] Support x2APIC mode with TCG accelerator

On 12/28/23 22:44, Bui Quang Minh wrote: On 12/26/23 16:21, Michael S. Tsirkin wrote: On Mon, Dec 25, 2023 at 11:40:54PM +0700, Bui Quang Minh wrote: Hi everyone, This series implements x2APIC mode in userspace local APIC and the RDMSR/WRMSR helper to access x2APIC registers in x2APIC mode. In

Re: [PATCH] tests/qtest/virtio-ccw: Fix device presence checking

On 6/1/24 14:01, Samuel Tardieu wrote: An apparent copy-paste error tests for the presence of the virtio-rng-ccw device in order to perform tests on the virtio-scsi-ccw device. Fixes: 65331bf5d1 ("tests/qtest: Check for virtio-ccw devices before using them") Reviewed-by: Philippe Mathieu-Da

[PATCH v2 3/3] target/i386/cpu: Fix typo in comment

Signed-off-by: Bernhard Beschow Reviewed-by: Alex Bennée --- target/i386/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 2524881ce2..7d11edf4fa 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2178,7 +2178,7 @@ stati

[PATCH v2 0/3] Fix PIC interrupt handling of x86 CPUs if APIC is globally disabled

This series is part of my work emulating the VIA Apollo Pro 133T chipset in QEMU [1] and testing it by running real-world BIOSes on it. The first two patches fix an issue regarding PIC interrupt handling, the third one just fixes a typo in a comment. During testing, I've found that the boot proces

[PATCH v2 1/3] hw/i386/x86: Reverse if statement

The if statement currently uses double negation when executing the else branch. So swap the branches and simplify the condition to make the code more comprehensible. Signed-off-by: Bernhard Beschow --- hw/i386/x86.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/i38

[PATCH v2 2/3] hw/i386/x86: Fix PIC interrupt handling if APIC is globally disabled

QEMU populates the apic_state attribute of x86 CPUs if supported by real hardware or if SMP is active. When handling interrupts, it just checks whether apic_state is populated to route the interrupt to the PIC or to the APIC. However, chapter 10.4.3 of [1] requires that: When IA32_APIC_BASE[11]

[PATCH] tests/qtest/virtio-ccw: Fix device presence checking

An apparent copy-paste error tests for the presence of the virtio-rng-ccw device in order to perform tests on the virtio-scsi-ccw device. Signed-off-by: Samuel Tardieu --- tests/qtest/virtio-ccw-test.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/qtest/virtio-ccw-tes

Re: [PATCH 02/10] hw/audio/virtio-sound: allocate all streams in advance

Am 05.01.24 um 11:54 schrieb Marc-André Lureau: > Hi > > On Fri, Jan 5, 2024 at 12:34 AM Volker Rümelin wrote: >> It is much easier to migrate an array of structs than individual >> structs that are accessed via a pointer to a pointer to an array >> of pointers to struct, where some pointers can a

Re: acpiBitsTest.test_acpi_smbios_bits test intermittently times out

On Sat, 6 Jan 2024 at 05:41, Ani Sinha wrote: > > On Sat, Jan 6, 2024 at 10:05 AM Ani Sinha wrote: > > > > On Sat, Jan 6, 2024 at 12:11 AM Peter Maydell > > wrote: > > > > > > The avocado test acpiBitsTest.test_acpi_smbios_bits seems to be > > > flaky in CI -- sometimes it appears to time out.