On 15/1/24 10:48, Zhao Liu wrote:
From: Zhao Liu
The hw/core/cpu.c was split as hw/core/cpu-common.c and
hw/core/cpu-sysemu.c in the commit df4fd7d5c8a3 ("cpu: Split as
cpu-common / cpu-sysemu").
Update the related entry.
Signed-off-by: Zhao Liu
---
MAINTAINERS | 3 ++-
1 file changed, 2
On 15/1/24 08:02, Thomas Huth wrote:
The test_prescaler() part in the npcm7xx_watchdog_timer test is quite
repetive, testing all possible combinations of the WTCLK and WTIS
bitfields. Since each test spins up a new instance of QEMU, this is
rather an expensive test, especially on loaded host
On 15/1/24 05:34, Bin Meng wrote:
At present we expect struct arm_boot_info::get_dtb() to return the
device tree pointer as well as the device tree size. However, this
is not necessary as we can get the device tree size via the device
tree header directly. Change get_dtb() signature to drop the
Hi,
On 12/21/23 14:45, Eric Auger wrote:
> We used to set default page_size_mask to qemu_target_page_mask() but
> with VFIO assignment it makes more sense to use the actual host page mask
> instead.
>
> So from now on qemu_real_host_page_mask() will be used as a default.
> To be able to migrate
On 13/1/24 20:16, Guenter Roeck wrote:
Allwinner R40 supports an AHCI compliant SATA controller.
Add support for it.
Signed-off-by: Guenter Roeck
---
docs/system/arm/bananapi_m2u.rst | 1 +
hw/arm/Kconfig | 1 +
hw/arm/allwinner-r40.c | 12 +++-
Hi,
On 13/1/24 20:16, Guenter Roeck wrote:
Allwinner R40 supports two USB host ports shared between a USB 2.0 EHCI
host controller and a USB 1.1 OHCI host controller. Add support for both
of them.
If machine USB support is not enabled, create unimplemented devices
for the USB memory ranges to
On 15.01.24 11:48, David Hildenbrand wrote:
On 12.01.24 16:04, Steve Sistare wrote:
Allow cpr-reboot for vfio if the guest is in the suspended runstate. The
guest drivers' suspend methods flush outstanding requests and re-initialize
the devices, and thus there is no device state to save and
On 12.01.24 16:04, Steve Sistare wrote:
Allow cpr-reboot for vfio if the guest is in the suspended runstate. The
guest drivers' suspend methods flush outstanding requests and re-initialize
the devices, and thus there is no device state to save and restore. The
user is responsible for
Am 14.01.24 um 14:51 schrieb Marc-André Lureau:
>>
>> diff --git a/ui/clipboard.c b/ui/clipboard.c
>> index 3d14bffaf8..c13b54d2e9 100644
>> --- a/ui/clipboard.c
>> +++ b/ui/clipboard.c
>> @@ -129,7 +129,8 @@ void qemu_clipboard_request(QemuClipboardInfo *info,
>> if (info->types[type].data
From: Yi Liu
PASID-based iotlb (piotlb) is used during walking Intel
VT-d stage-1 page table.
This adds the basic framework for piotlb invalidation,
detailed handling will be added in next patch.
Signed-off-by: Yi Liu
Signed-off-by: Zhenzhong Duan
---
hw/i386/intel_iommu_internal.h | 13
Hi,
This series enables stage-1 translation support in intel iommu which
we called "modern" mode. In this mode, we don't do shadowing of
guest page table for passthrough device but pass stage-1 page table
to host side to construct a nested domain; we also support emulated
device by translating
On Mon, 15 Jan 2024 at 09:37, Zhao Liu wrote:
>
> From: Zhao Liu
>
> Remove unused headers in cpu-common.c:
> * qemu/notify.h
> * qemu/log.h
> * qemu/main-loop.h
> * exec/cpu-common.h
> * qemu/error-report.h
> * qemu/qemu-print.h
>
> Though hw/core/cpu.h has been included by sysemu/hw_accel.h,
From: Yi Sun
When bind/unbind emulated devices, we should invalidate QEMU
piotlb. Host will flush piotlb for passthrough devices so we
don't handle passthrough devices.
Signed-off-by: Yi Sun
Signed-off-by: Zhenzhong Duan
---
hw/i386/intel_iommu.c | 27 +--
1 file
From: Yi Liu
This adds PASID cache invalidation handling. When guest updated
a pasid entry in scalable mode, guest software should issue a proper
PASID cache invalidation when caching-mode is exposed. This can happen
even when pasid is disabled as rid_pasid will still be used.
This only adds a
From: Yi Liu
Because we support both FST and SST translation, rename slpte in iotlb_entry
to pte to make it generic.
Signed-off-by: Yi Liu
Signed-off-by: Yi Sun
Signed-off-by: Zhenzhong Duan
---
include/hw/i386/intel_iommu.h | 2 +-
hw/i386/intel_iommu.c | 10 +-
2 files
From: Yi Liu
This traps the guest PASID-based iotlb invalidation request
and propagate it to host.
Intel VT-d 3.0 supports nested translation in PASID granular.
Guest SVA support could be implemented by configuring nested
translation on specific PASID. This is also known as dual stage
DMA
From: Yi Liu
This adds a PASID cache management infrastructure based on
new added structure VTDPASIDAddressSpace, which is used to track
the PASID usage and future PASID tagged DMA address translation
support in vIOMMU.
struct VTDPASIDAddressSpace {
PCIBus *bus;
uint8_t
Repo: https://github.com/yiliu1765/iommufd/tree/iommufd_nesting
commit id: 7c22f835c4c9b
Placeholder, not for upstream.
Signed-off-by: Zhenzhong Duan
---
include/standard-headers/drm/drm_fourcc.h | 2 +
include/standard-headers/linux/fuse.h | 10 +-
From: Yu Zhang
Currently we use only VTD_FR_PASID_TABLE_INV as
fault reaon. Fix this with correct fault reasons
listed in VT-d spec 7.2.3.
Signed-off-by: Yu Zhang
Signed-off-by: Zhenzhong Duan
---
hw/i386/intel_iommu_internal.h | 8 ++-
hw/i386/intel_iommu.c | 42
From: Yi Liu
This adds an empty handling for PASID-based Device-TLB invalidation.
For now it is enough as it is not necessary to propagate it to host
for passthrough device.
The reason for an empty device tlb invalidation handling is that
iommufd's intel vt-d cache invalidation uapi indicates
From: Yi Liu
To accelerate stage-1 translation, introduce pasid iotlb cache.
Signed-off-by: Yi Liu
Signed-off-by: Yi Sun
Signed-off-by: Zhenzhong Duan
---
hw/i386/intel_iommu_internal.h | 1 +
include/hw/i386/intel_iommu.h | 1 +
hw/i386/intel_iommu.c | 126
From: Yi Liu
The force reset clears the vtd_pasid_as and also unbinds the pasid on
host side. This is bad when the reset is triggered after some pasid
binding is setup. e.g. gcmd.TE enabling will reset cache, but wishes
to keep the pasid #0 (gIOVA) binding. So needs to refresh the pasid
bind per
From: Yi Liu
This replays guest pasid attachments after context cache
invalidation. This is a behavior to ensure safety. Actually,
programmer should issue pasid cache invalidation with proper
granularity after issuing a context cache invalidation.
Signed-off-by: Yi Liu
Signed-off-by: Yi Sun
On a system influenced by ERRATA_772415, IOMMU_HW_INFO_VTD_ERRATA_772415_SPR17
is repored by IOMMU_DEVICE_GET_HW_INFO. Due to this errata, even the readonly
range mapped on stage-2 page table could still be written.
Reference from 4th Gen Intel Xeon Processor Scalable Family Specification
Update,
From: Yi Liu
This adds stage-1 page table walking to support stage-1 only
transltion in scalable mode.
Signed-off-by: Yi Liu
Signed-off-by: Yi Sun
Signed-off-by: Zhenzhong Duan
---
hw/i386/intel_iommu_internal.h | 16 +++
hw/i386/intel_iommu.c | 242
From: Yi Liu
Intel VT-d 3.0 introduces scalable mode, and it has a bunch of capabilities
related to scalable mode translation, thus there are multiple combinations.
While this vIOMMU implementation wants to simplify it for user by providing
typical combinations. User could config it by
From: Yi Sun
This is used by some emulated devices which caches address
translation result. When piotlb invalidation issued in guest,
those caches should be refreshed.
Signed-off-by: Yi Sun
Signed-off-by: Zhenzhong Duan
---
hw/i386/intel_iommu.c | 56
Implement IOMMUFDDevice interface callbacks attach_hwpt/detach_hwpt
for vIOMMU usage. vIOMMU utilizes them to attach to or detach from
hwpt on host side.
Signed-off-by: Yi Liu
Signed-off-by: Zhenzhong Duan
---
hw/vfio/iommufd.c | 36 +++-
1 file changed, 35
Include helper to allocate user-managed hwpt and helper for cache
invalidation as user-managed HWPT needs to sync cache per modifications.
Signed-off-by: Nicolin Chen
Signed-off-by: Zhenzhong Duan
---
include/sysemu/iommufd.h | 7 +
backends/iommufd.c | 61
When vIOMMU is configured in scalable modern mode, stage-1 page table is
supported. We need to check and sync host side cap/ecap with vIOMMU
cap/ecap.
This happens when PCIe device (i.e., VFIO case) sets IOMMUFDDevice to vIOMMU.
Some of the bits in cap/ecap is user controllable, then user setting
Sometimes vIOMMU needs to re-attach device to ioas id of vfio,
i.e., when vIOMMU is disabled by guest.
This is a prerequisite patch for following one.
Signed-off-by: Zhenzhong Duan
---
include/sysemu/iommufd_device.h | 3 ++-
backends/iommufd_device.c | 3 ++-
hw/vfio/iommufd.c
This captures the guest PASID table entry modifications and
propagates the changes to host to attach a hwpt with type determined
per guest PGTT configuration.
When PGTT is Pass-through(100b), the hwpt on host side is a stage-2
page table(GPA->HPA). When PGTT is First-stage Translation only(001b),
Add an new element scalable_mode in IntelIOMMUState to mark scalable
modern mode, this element will be exposed as an intel_iommu property
finally.
For now, it's only a placehholder and used for cap/ecap initialization,
parameter compatibility check, etc.
No need to zero this element separately
With IOMMUFDDevice passed to vIOMMU, we can query hw IOMMU information
and allocate hwpt for a device, but still need an extensible interface
for vIOMMU usage.
This introduces an IOMMUFDDevice targeted interface for vIOMMU.
Currently this interface includes two callbacks attach_hwpt/detach_hwpt
On Mon, 15 Jan 2024 at 05:58, Shlomo Pongratz wrote:
>
> Thank you.
> Please see comments inline.
>
> On Fri, Jan 12, 2024 at 7:03 PM Peter Maydell
> wrote:
> >
> > On Tue, 9 Jan 2024 at 12:45, Shlomo Pongratz
> > wrote:
> >
> > Hi; thanks for this patch.
> >
> > > Hanlde wrap around caused
Hi,
> PS: when are we likely to be able to update to a proper released
> EDK2 ? Running with a git snapshot isn't ideal, so if we can
> move to an EDK2 release version within this QEMU cycle that would
> be nice.
Next release should be tagged by end of February, so if the qemu 9.0
schedule is
On Mon, 15 Jan 2024 at 02:37, Jason Wang wrote:
>
> On Fri, Jan 5, 2024 at 12:45 AM Stefan Hajnoczi wrote:
> >
> > On Thu, 4 Jan 2024 at 11:30, Daniel P. Berrangé wrote:
> > >
> > > We've previously bumped up the timeouts in the netdev-socket qtest
> > > to supposedly fix non-deterministic
This is a prerequisite for host cap/ecap sync.
No functional change intended.
Signed-off-by: Zhenzhong Duan
---
hw/i386/intel_iommu.c | 92 +++
1 file changed, 50 insertions(+), 42 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
From: Yi Liu
Add a framework to check and synchronize host IOMMU cap/ecap with
vIOMMU cap/ecap.
Currently only stage-2 translation is supported which is backed by
shadow page table on host side. So we don't need exact matching of
each bit of cap/ecap between vIOMMU and host. However, we can
Initialize IOMMUFDDevice in vfio and pass to vIOMMU, so that vIOMMU
could get hw IOMMU information.
In VFIO legacy backend mode, we still pass a NULL IOMMUFDDevice to vIOMMU,
in case vIOMMU needs some processing for VFIO legacy backend mode.
Originally-by: Yi Liu
Signed-off-by: Nicolin Chen
From: Yi Liu
This adds set/unset_iommu_device() implementation in Intel vIOMMU.
In set call, IOMMUFDDevice is recorded in hash table indexed by
PCI BDF.
Signed-off-by: Yi Liu
Signed-off-by: Yi Sun
Signed-off-by: Zhenzhong Duan
---
include/hw/i386/intel_iommu.h | 10 +
IOMMUFDDevice represents a device in iommufd and can be used as
a communication interface between devices (i.e., VFIO, VDPA) and
vIOMMU.
Currently it includes iommufd handler and device id information
which could be used by vIOMMU to get hw IOMMU information.
In future nested translation
From: Yi Liu
This adds pci_device_set/unset_iommu_device() to set/unset
IOMMUFDDevice for a given PCIe device. Caller of set
should fail if set operation fails.
Extract out pci_device_get_iommu_bus_devfn() to facilitate
implementation of pci_device_set/unset_iommu_device().
Signed-off-by: Yi
Hi,
This introduces a framework for vIOMMU to get hw IOMMU cap/ecap information
through IOMMUFD interface and check or sync with vIOMMU's own cap/ecap
config.
This framework works by having device side, i.e. VFIO, register a
IOMMUFDDevice to vIOMMU, IOMMUFDDevice includes necessary data to
在 2024/1/12 下午5:52, gaosong 写道:
在 2024/1/11 下午4:26, Thomas Huth 写道:
On 11/01/2024 08.25, gaosong wrote:
Hi,
在 2024/1/11 下午3:08, Thomas Huth 写道:
On 02/01/2024 18.22, Philippe Mathieu-Daudé wrote:
Full build config to run CI tests on a Loongarch64 host.
Forks might enable this by setting
On Mon, Jan 15, 2024 at 1:52 PM Daniel P. Berrangé wrote:
>
> The extended clipboard message protocol requires that the client
> activate the extension by requesting a psuedo encoding. If this
> is not done, then any extended clipboard messages from the client
> should be considered invalid and
On Mon, Nov 27, 2023 at 05:25:52PM -0300, Fabiano Rosas wrote:
> From: Nikolay Borisov
>
> Add basic tests for 'fixed-ram' migration.
>
> Signed-off-by: Nikolay Borisov
> Signed-off-by: Fabiano Rosas
Reviewed-by: Peter Xu
--
Peter Xu
This functionality turns out to have already been added by commit
40336d5b1d4c6b8b8b38c77fda254457d44fe90b
Vadim
От: Alistair Francis
Отправлено: 4 января 2024 г. 6:54:27
Кому: Vadim Shakirov
Копия: qemu-devel@nongnu.org; Palmer Dabbelt; Alistair Francis; Bin
On 12/1/24 23:03, Richard Henderson wrote:
Fixes: 468c1bb5ca ("linux-user/riscv: Add vdso")
Reported-by: Vineet Gupta
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
---
linux-user/riscv/vdso-32.so | Bin 2900 -> 2900 bytes
linux-user/riscv/vdso-64.so | Bin 3856
The extended clipboard message protocol requires that the client
activate the extension by requesting a psuedo encoding. If this
is not done, then any extended clipboard messages from the client
should be considered invalid and the client dropped.
Signed-off-by: Daniel P. Berrangé
---
The need
On Mon, Nov 27, 2023 at 05:25:51PM -0300, Fabiano Rosas wrote:
> Add the necessary code to parse the format changes for the 'fixed-ram'
> capability.
>
> One of the more notable changes in behavior is that in the 'fixed-ram'
> case ram pages are restored in one go rather than constantly looping
>
From: Zhao Liu
Remove unused header in cpu-common.c:
* qapi/error.h
Tested by "./configure" and then "make".
Signed-off-by: Zhao Liu
---
hw/core/machine.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/core/machine.c b/hw/core/machine.c
index
From: Zhao Liu
Reorder the header files (except qemu/osdep.h) in alphabetical order.
Tested by "./configure" and then "make".
Signed-off-by: Zhao Liu
---
hw/core/null-machine.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/core/null-machine.c
From: Zhao Liu
Reorder the header files (except qemu/osdep.h) in alphabetical order.
Tested by "./configure" and then "make".
Signed-off-by: Zhao Liu
---
hw/core/cpu-common.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/hw/core/cpu-common.c
From: Zhao Liu
Remove the unnecessary header (hw/core/cpu.h) since the hw/boards.h
has already included that header.
Signed-off-by: Zhao Liu
---
hw/core/null-machine.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/core/null-machine.c b/hw/core/null-machine.c
index
From: Zhao Liu
Reorder the header files (except qemu/osdep.h) in alphabetical order.
Tested by "./configure" and then "make".
Signed-off-by: Zhao Liu
---
hw/core/numa.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/core/numa.c b/hw/core/numa.c
index
From: Zhao Liu
Remove unused headers in cpu-common.c:
* qemu/notify.h
* qemu/log.h
* qemu/main-loop.h
* exec/cpu-common.h
* qemu/error-report.h
* qemu/qemu-print.h
Though hw/core/cpu.h has been included by sysemu/hw_accel.h, to keep
the dependency clear, still directly include hw/core/cpu.h in
From: Zhao Liu
Reorder the header files (except qemu/osdep.h) in alphabetical order.
Tested by "./configure" and then "make".
Signed-off-by: Zhao Liu
---
hw/core/cpu-sysemu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/core/cpu-sysemu.c b/hw/core/cpu-sysemu.c
From: Zhao Liu
Remove unused headers in machine-qmp-cmds.c:
* qemu/main-loop.h
* qemu/uuid.h
* sysemu/hostmem.h
Tested by "./configure" and then "make".
Signed-off-by: Zhao Liu
---
hw/core/machine-qmp-cmds.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git
From: Zhao Liu
Reorder the header files (except qemu/osdep.h) in alphabetical order.
Tested by "./configure" and then "make".
Signed-off-by: Zhao Liu
---
hw/core/machine.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/hw/core/machine.c
From: Zhao Liu
The hw/core/cpu.c was split as hw/core/cpu-common.c and
hw/core/cpu-sysemu.c in the commit df4fd7d5c8a3 ("cpu: Split as
cpu-common / cpu-sysemu").
Update the related entry.
Signed-off-by: Zhao Liu
---
MAINTAINERS | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff
From: Zhao Liu
Identify unused headers by full compilation (tested by "./configure" and
then "make") and reorder headers in alphabetical order.
In addition, update a file entry in MAINTAINERS file.
Zhao Liu (11):
MAINTAINERS: Update hw/core/cpu.c entry
hw/core: Cleanup unused included
From: Zhao Liu
Remove unused header in numa.c:
* sysemu/hostmem.h
* exec/cpu-common.h
* exec/ramlist.h
* qemu/bitmap.h
* hw/core/cpu.h
* hw/mem/pc-dimm.h
* migration/vmstate.h
Though sysemu/numa.h has been included by sysemu/hostmem.h which is
included by hw/boards.h, to keep the dependency
On Mon, Jan 15, 2024 at 09:03:20AM +, Daniel P. Berrangé wrote:
> On Mon, Jan 15, 2024 at 04:57:42PM +0800, Peter Xu wrote:
> > On Thu, Jan 11, 2024 at 03:46:02PM -0300, Fabiano Rosas wrote:
> > > > (2) Why metadata doesn't matter (v.s. fsync(), when CONFIG_FDATASYNC=y)?
> > >
> > > Syncing
On Mon, Nov 27, 2023 at 05:25:50PM -0300, Fabiano Rosas wrote:
> From: Nikolay Borisov
>
> Implement the outgoing migration side for the 'fixed-ram' capability.
>
> A bitmap is introduced to track which pages have been written in the
> migration file. Pages are written at a fixed location for
j is used while loading an ELF file to byteswap segments'
data. If data is larger than 2GB an overflow may happen.
So j should be elf_word.
This commit fixes a minor bug, maybe even a typo.
Found by Linux Verification Center (linuxtesting.org) with SVACE.
Fixes: 7ef295ea5b ("loader: Add data
The value of FEAT_XSAVE_XCR0_HI leaf and FEAT_XSAVE_XSS_HI leaf also
need to be masked by XCR0 and XSS mask respectively, to make it
logically correct.
Fixes: 301e90675c3f ("target/i386: Enable support for XSAVES based features")
Signed-off-by: Xiaoyao Li
---
target/i386/cpu.c | 4 ++--
1 file
Leaf FEAT_XSAVE_XSS_LO and FEAT_XSAVE_XSS_HI also need to be cleared
when CPUID_EXT_XSAVE is not set.
Fixes: 301e90675c3f ("target/i386: Enable support for XSAVES based features")
Signed-off-by: Xiaoyao Li
---
target/i386/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git
The two bugs were introduced when xsaves feature was added by commit
301e90675c3f ("target/i386: Enable support for XSAVES based features").
Xiaoyao Li (2):
i386/cpu: Clear FEAT_XSAVE_XSS_LO/HI leafs when CPUID_EXT_XSAVE is not
available
i386/cpu: Mask with XCR0/XSS mask for
On 1/12/24 20:54, Fabiano Rosas wrote:
Cédric Le Goater writes:
On 1/10/24 14:19, Fabiano Rosas wrote:
Markus Armbruster writes:
Peter Xu writes:
On Tue, Jan 09, 2024 at 10:22:31PM +0100, Philippe Mathieu-Daudé wrote:
Hi Fabiano,
On 9/1/24 21:21, Fabiano Rosas wrote:
Cédric Le
Pierrick Bouvier writes:
> On 1/13/24 21:16, Alex Bennée wrote:
>> Pierrick Bouvier writes:
>>
>>> On 1/12/24 21:20, Alex Bennée wrote:
Pierrick Bouvier writes:
> On 1/11/24 19:57, Philippe Mathieu-Daudé wrote:
>> Hi Pierrick,
>> On 11/1/24 15:23, Pierrick Bouvier wrote:
On Mon, Jan 15, 2024 at 03:20:37PM +0800, Zhao Liu wrote:
> On Mon, Jan 15, 2024 at 02:57:30PM +0800, Yuan Yao wrote:
> > Date: Mon, 15 Jan 2024 14:57:30 +0800
> > From: Yuan Yao
> > Subject: Re: [PATCH v7 08/16] i386: Expose module level in CPUID[0x1F]
> >
> > On Mon, Jan 15, 2024 at 02:20:20PM
On Mon, Jan 15, 2024 at 04:57:42PM +0800, Peter Xu wrote:
> On Thu, Jan 11, 2024 at 03:46:02PM -0300, Fabiano Rosas wrote:
> > > (2) Why metadata doesn't matter (v.s. fsync(), when CONFIG_FDATASYNC=y)?
> >
> > Syncing the inode information is not critical, it's mostly timestamp
> > information
On Mon, Nov 27, 2023 at 05:25:49PM -0300, Fabiano Rosas wrote:
> The fixed-ram migration format needs a channel that supports seeking
> to be able to write each page to an arbitrary offset in the migration
> stream.
>
> Signed-off-by: Fabiano Rosas
> Reviewed-by: Daniel P. Berrangé
> ---
> -
On Thu, Jan 11, 2024 at 03:46:02PM -0300, Fabiano Rosas wrote:
> > (2) Why metadata doesn't matter (v.s. fsync(), when CONFIG_FDATASYNC=y)?
>
> Syncing the inode information is not critical, it's mostly timestamp
> information (man inode). And fdatasync makes sure to sync any metadata
> that
CSR cpuid register is used for routing irq to different vcpus, its
value is kept unchanged since poweron. So it is not necessary to
set CSR cpuid register after system resets, and it is only set at
vm creation stage.
Signed-off-by: Bibo Mao
---
target/loongarch/kvm/kvm.c | 9 ++---
1 file
On Mon, Jan 15, 2024 at 08:11:40AM +, Daniel P. Berrangé wrote:
> On Mon, Jan 15, 2024 at 02:22:47PM +0800, Peter Xu wrote:
> > On Thu, Jan 11, 2024 at 03:38:31PM -0300, Fabiano Rosas wrote:
> > > Peter Xu writes:
> > >
> > > > On Mon, Nov 27, 2023 at 05:25:42PM -0300, Fabiano Rosas wrote:
>
Hi Stephen and Cedric,
This issue haven't been found in real platform but sometime happens in
emulator, e.g. Simic.
> Adding Aspeed Engineers. This reminds me of a discussion a while ago.
>
> On 1/11/24 18:38, Stephen Longfield wrote:
> > We’ve noticed inconsistent behavior when running a
On Mon, Jan 15, 2024 at 08:11:46AM +0100, Thomas Huth wrote:
> When running with TCI, the boot-serial-test can take longer than 3 minutes:
>
> https://gitlab.com/qemu-project/qemu/-/jobs/5890481086#L4774
>
> Bump the timeout to 4 minutes to avoid CI failures here.
>
> Signed-off-by: Thomas
On Mon, Jan 15, 2024 at 02:22:47PM +0800, Peter Xu wrote:
> On Thu, Jan 11, 2024 at 03:38:31PM -0300, Fabiano Rosas wrote:
> > Peter Xu writes:
> >
> > > On Mon, Nov 27, 2023 at 05:25:42PM -0300, Fabiano Rosas wrote:
> > >> Hi,
> > >>
> > >> In this v3:
> > >>
> > >> Added support for the
The KVM_ARM_VCPU_PMU_V3_FILTER provides the ability to let the VMM decide
which PMU events are provided to the guest. Add a new option
`kvm-pmu-filter` as -cpu sub-option to set the PMU Event Filtering.
Without the filter, all PMU events are exposed from host to guest by
default. The usage of the
201 - 281 of 281 matches
Mail list logo
