On Thu, 15 Feb 2024 03:23, Lukas Stockner wrote:
This patch extends the PCIe link speed option so that slots can be
configured as supporting 32GT/s (Gen5) or 64GT/s (Gen5) speeds.
This is as simple as setting the appropriate bit in LnkCap2 and
the appropriate value in LnkCap and LnkCtl2.
On 2/15/24 22:16, Richard Henderson wrote:
On 2/15/24 19:34, Guenter Roeck wrote:
- env->psw = psw & ~(PSW_N | PSW_V | PSW_CB);
+ if (hppa_is_pa20(env)) {
+ env->psw = psw & ~(PSW_N | PSW_V | PSW_CB | 0xffull);
+ } else {
+ env->psw = psw & ~(PSW_N | PSW_V |
Roman Khapov writes:
> This commit adds the optional field reason for the events, which
> contains the string, describing reason of status changing.
> For example: reason of migration fail.
>
> Function migrate_set_state now accepts 4th argument: the reason to
> pass to event. Every call of this
On 2/15/24 19:34, Guenter Roeck wrote:
-env->psw = psw & ~(PSW_N | PSW_V | PSW_CB);
+if (hppa_is_pa20(env)) {
+env->psw = psw & ~(PSW_N | PSW_V | PSW_CB | 0xffull);
+} else {
+env->psw = psw & ~(PSW_N | PSW_V | PSW_CB);
+}
There are never any bits above
The RISC-V debug specification defines the following operation for CSR
tcontrol when "mret" is executed:
- tcontrol.MTE is set to the value of tcontrol.MPTE
This commit implements the above operation into helper_mret().
Note that from tech-debug mailing list:
The RISC-V debug specification defines an optional CSR "tcontrol" within
the trigger module. This commit adds its read/write operations and
related bit-field definitions.
Signed-off-by: Alvin Chang
---
target/riscv/cpu.h | 1 +
target/riscv/cpu_bits.h | 3 +++
target/riscv/csr.c |
>From the RISC-V debug specification, it defines the following operations
for CSR tcontrol when any trap into M-mode is taken:
1. tcontrol.MPTE is set to the value of tcontrol.MTE
2. tcontrol.MTE is set to 0
This commit implements the above operations into
riscv_cpu_do_interrupt().
The RISC-V Debug specification defines CSR "tcontrol" in the trigger
module:
https://github.com/riscv/riscv-debug-spec
This series implements it and the related operations.
Alvin Chang (4):
target/riscv: Add CSR tcontrol of debug trigger module
target/riscv: Reset CSR tcontrol when the
When the trigger module resets, reset the value of CSR tcontrol as zero.
Signed-off-by: Alvin Chang
---
target/riscv/debug.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index e30d99cc2f..e3832a643e 100644
--- a/target/riscv/debug.c
+++
On 2/16/24 06:58, Charlie Jenkins wrote:
On Thu, Feb 15, 2024 at 09:34:15PM -0800, Guenter Roeck wrote:
Unaligned 64-bit accesses were found in Linux to clobber carry bits,
resulting in bad results if an arithmetic operation involving a
carry bit was executed after an unaligned 64-bit
Unaligned 64-bit accesses were found in Linux to clobber carry bits,
resulting in bad results if an arithmetic operation involving a
carry bit was executed after an unaligned 64-bit operation.
hppa 2.0 defines additional carry bits in PSW register bits 32..39.
When restoring PSW after executing
On Wed, Feb 14, 2024 at 11:34:55AM -0300, Daniel Henrique Barboza wrote:
>
>
> On 2/7/24 06:34, Ethan Chen wrote:
> > Support specification Version 1.0.0-draft4 rapid-k model.
> > The specification url:
> > https://github.com/riscv-non-isa/iopmp-spec/blob/main/riscv_iopmp_specification.pdf
> >
>
On Wed, Jan 10, 2024 at 2:07 AM Irina Ryapolova
wrote:
>
> Added xATP_MODE validation for vsatp/hgatp CSRs.
> The xATP register is an SXLEN-bit read/write WARL register, so
> the legal value must be returned (See riscv-privileged-20211203,
> SATP/VSATP/HGATP CSRs).
>
> Signed-off-by: Irina
On Fri, Feb 16, 2024 at 6:00 AM Conor Dooley wrote:
>
> On Thu, Feb 15, 2024 at 08:11:45PM +0100, Andrew Jones wrote:
> > On Thu, Feb 15, 2024 at 04:34:32PM +, Conor Dooley wrote:
> > > On Thu, Feb 15, 2024 at 03:26:18PM +0100, Andrew Jones wrote:
> > > > On Thu, Feb 15, 2024 at 01:33:47PM
Documentation on how to run Linux on the amigaone, pegasos2 and
sam460ex machines is currently burried in the depths of the qemu-devel
mailing list and in the source code. Let's collect the information in
the QEMU handbook for a one stop solution.
Co-authored-by: Bernhard Beschow
Signed-off-by:
On Fri, Feb 16, 2024 at 8:41 AM Daniel Henrique Barboza
wrote:
>
> Hi,
>
> This new version is rebased with alistair/riscv-to-apply.next and with
> more acks added.
>
> No other changes made.
>
> Changes from v3:
> - rebased with alistair/riscv-to-apply.next @ c93c42a273
> - v3 link:
>
On Thu, 15 Feb 2024, Richard Henderson wrote:
> > Converting a 4.4 GiB Windows 10 image to qcow2. It was mentioned in v1 and
> > v2,
> > are you saying they did not reach your inbox?
> > https://lore.kernel.org/qemu-devel/20231013155856.21475-1-mmroma...@ispras.ru/
> >
From: Andrew Jones
Named features are extensions which don't make sense for users to
control and are therefore not exposed on the command line. However,
svade is an extension which makes sense for users to control, so treat
it like a "normal" extension. The default is false, even for the max
cpu
Hi,
This new version is rebased with alistair/riscv-to-apply.next and with
more acks added.
No other changes made.
Changes from v3:
- rebased with alistair/riscv-to-apply.next @ c93c42a273
- v3 link:
https://lore.kernel.org/qemu-riscv/20240202152154.773253-1-dbarb...@ventanamicro.com/
Andrew
From: Andrew Jones
Gate hardware A/D PTE bit updating on {m,h}envcfg.ADUE and only
enable menvcfg.ADUE on reset if svade has not been selected. Now
that we also consider svade, we have four possible configurations:
1) !svade && !svadu
use hardware updating and there's no way to disable it
Further discussions after the introduction of rva22 support in QEMU
revealed that what we've been calling 'named features' are actually
regular extensions, with their respective riscv,isa DTs. This is
clarified in [1]. [2] is a bug tracker asking for the profile spec to be
less cryptic about it.
From: Andrew Jones
The hypervisor should decide what it wants to enable. Zero all
configuration enable bits on reset.
Also, commit ed67d63798f2 ("target/riscv: Update CSR bits name for
svadu extension") missed one reference to 'hade'. Change it now.
Fixes: 0af3f115e68e ("target/riscv: Add
Recent changes in options handling removed the 'mmu' default the bare
CPUs had, meaning that we must enable 'mmu' by hand when using the
rva22s64 profile CPU.
Given that this profile is setting a satp mode, it already implies that
we need a 'mmu'. Enable the 'mmu' in this case.
Signed-off-by:
The RVA22U64 and RVA22S64 profiles mandates certain extensions that,
until now, we were implying that they were available.
We can't do this anymore since named features also has a riscv,isa
entry. Let's add them to riscv_cpu_named_features[].
Instead of adding one bool for each named feature
On 2/15/24 11:36, Alexander Monakov wrote:
On Thu, 15 Feb 2024, Richard Henderson wrote:
On 2/14/24 22:57, Alexander Monakov wrote:
On Wed, 14 Feb 2024, Richard Henderson wrote:
v3: https://patchew.org/QEMU/20240206204809.9859-1-amona...@ispras.ru/
Changes for v4:
- Keep separate >=
On Thu, 15 Feb 2024 at 21:47, Richard Henderson
wrote:
>
> On 2/15/24 06:02, Ard Biesheuvel wrote:
> > From: Ard Biesheuvel
> >
> > The Cortex-A53 r0p4 revision that QEMU emulates is affected by a CatA
> > erratum #843419 (i.e., the most severe), which requires workarounds in
> > the toolchain
On Thu, 15 Feb 2024, Richard Henderson wrote:
> On 2/14/24 22:57, Alexander Monakov wrote:
> >
> > On Wed, 14 Feb 2024, Richard Henderson wrote:
> >
> >> v3: https://patchew.org/QEMU/20240206204809.9859-1-amona...@ispras.ru/
> >>
> >> Changes for v4:
> >>- Keep separate >= 256 entry
On 2/15/24 06:52, Alistair Francis wrote:
On Sat, Feb 3, 2024 at 1:23 AM Daniel Henrique Barboza
wrote:
Hi,
In this new version we changed patch 3 as suggested by Alistair in v1
[1]. Instead of creating individual always-true bool for each named
feature, create a bool flag will be always
On 2/14/24 22:57, Alexander Monakov wrote:
On Wed, 14 Feb 2024, Richard Henderson wrote:
v3: https://patchew.org/QEMU/20240206204809.9859-1-amona...@ispras.ru/
Changes for v4:
- Keep separate >= 256 entry point, but only keep constant length
check inline. This allows the indirect
On 2/15/24 08:46, Alexander Monakov wrote:
Right, so we can pick the cheapest reduction method, and if I'm reading
Neoverse-N1 SOG right, SHRN is marginally cheaper than ADDV (latency 2
instead of 3), and it should be generally preferable on other cores, no?
Fair.
For that matter, cannot
On 2/15/24 16:28, Max Chou wrote:
In the vector unit-stride load/store helper functions. the vext_ldst_us
function corresponding most of the execution time. Inline the functions
can avoid the function call overhead to imperove the helper function
performance.
Signed-off-by: Max Chou
---
On Fri, 24 Nov 2023, shiju.j...@huawei.com wrote:
From: Shiju Jose
CXL spec 3.1 section 8.2.9.9.11.1 describes the device patrol scrub control
feature. The device patrol scrub proactively locates and makes corrections
to errors in regular cycle. The patrol scrub control allows the request to
Hi,
I have a situation when I need to use third-party 32-bit RISC-V CPU when rest
is all 64-bit RISC-V CPUs. I have seen that some steps were already made in the
direction to enable such configuration
On 2/15/24 06:02, Ard Biesheuvel wrote:
From: Ard Biesheuvel
The Cortex-A53 r0p4 revision that QEMU emulates is affected by a CatA
erratum #843419 (i.e., the most severe), which requires workarounds in
the toolchain as well as the OS.
Since the emulation is obviously not affected in the same
On 2/15/24 09:28, Max Chou wrote:
Hi all,
When glibc with RVV support [1], the memcpy benchmark will run 2x to 60x
slower than the scalar equivalent on QEMU and it hurts developer
productivity.
From the performance analysis result, we can observe that the glibc
memcpy spends most of the time
On 2/15/24 16:28, Max Chou wrote:
If there are not any QEMU plugin memory callback functions, checking
before calling the qemu_plugin_vcpu_mem_cb function can reduce the
function call overhead.
Signed-off-by: Max Chou
---
This was in my TODO list for some time. Thanks for looking it up.
Am 13. Februar 2024 16:00:26 UTC schrieb "Philippe Mathieu-Daudé"
:
>On 13/2/24 16:55, Michael S. Tsirkin wrote:
>> On Tue, Feb 13, 2024 at 01:01:45PM +0100, Philippe Mathieu-Daudé wrote:
>>> Trivial patches removing uses of "hw/i386/pc.h".
>>
>> How did you test that it's indeed unused?
>
>I
On 2/15/24 09:28, Max Chou wrote:
Signed-off-by: Max Chou
---
accel/tcg/user-exec.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index c5453810eee..803c271df11 100644
--- a/accel/tcg/user-exec.c
+++
On 2/15/24 09:28, Max Chou wrote:
Signed-off-by: Max Chou
---
accel/tcg/user-exec.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 68b252cb8e8..c5453810eee 100644
--- a/accel/tcg/user-exec.c
+++
On 2/15/24 09:28, Max Chou wrote:
/* unmasked unit-stride load and store operation */
-static void
+static inline QEMU_ALWAYS_INLINE void
vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
vext_ldst_elem_fn *ldst_elem, uint32_t log2_esz, uint32_t evl,
On 15/2/24 19:40, Alex Bennée wrote:
My default header template is GPLv3 but for QEMU code we really should
stick to GPLv2-or-later (allowing others to up-license it if they
wish). While this is test code we should still be consistent on the
source distribution.
I wrote all of this code so its
On 2/15/24 09:28, Max Chou wrote:
If there are not any QEMU plugin memory callback functions, checking
before calling the qemu_plugin_vcpu_mem_cb function can reduce the
function call overhead.
Signed-off-by: Max Chou
---
accel/tcg/ldst_common.c.inc | 40 +++--
On Thu, Feb 15, 2024 at 08:11:45PM +0100, Andrew Jones wrote:
> On Thu, Feb 15, 2024 at 04:34:32PM +, Conor Dooley wrote:
> > On Thu, Feb 15, 2024 at 03:26:18PM +0100, Andrew Jones wrote:
> > > On Thu, Feb 15, 2024 at 01:33:47PM +, Conor Dooley wrote:
> > > > On Fri, Feb 02, 2024 at
On 2/15/24 07:15, Nicholas Piggin wrote:
diff --git a/target/ppc/machine.c b/target/ppc/machine.c
index 731dd8df35..3541cd83cd 100644
--- a/target/ppc/machine.c
+++ b/target/ppc/machine.c
@@ -724,7 +724,7 @@ static const VMStateDescription vmstate_bhrb = {
.minimum_version_id = 1,
On 2/15/24 09:21, Richard Henderson wrote:
On 2/15/24 05:01, Jonathan Cameron wrote:
-static bool ptw_translate(PTETranslate *inout, hwaddr addr)
+static bool ptw_translate(PTETranslate *inout, hwaddr addr, uint64_t ra)
You do not need to pass in 'ra' here...
flags =
On 2/15/24 05:01, Jonathan Cameron wrote:
On i386, after fixing the page walking code to work with pages in
MMIO memory (specifically CXL emulated interleaved memory),
a crash was seen in an interrupt handling path.
Useful part of bt
Peter identified this as being due to the BQL already being
Signed-off-by: Max Chou
---
accel/tcg/user-exec.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 803c271df11..9ef35a22279 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -1050,8 +1050,9 @@ static
If there are not any QEMU plugin memory callback functions, checking
before calling the qemu_plugin_vcpu_mem_cb function can reduce the
function call overhead.
Signed-off-by: Max Chou
---
accel/tcg/ldst_common.c.inc | 40 +++--
1 file changed, 30 insertions(+),
In the vector unit-stride load/store helper functions. the vext_ldst_us
function corresponding most of the execution time. Inline the functions
can avoid the function call overhead to imperove the helper function
performance.
Signed-off-by: Max Chou
---
target/riscv/vector_helper.c | 30
Signed-off-by: Max Chou
---
accel/tcg/user-exec.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 68b252cb8e8..c5453810eee 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -942,8 +942,11 @@ void
Signed-off-by: Max Chou
---
accel/tcg/user-exec.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index c5453810eee..803c271df11 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -963,8 +963,9 @@ static inline
This commit seperate the helper function implementations of vector
segment load/store instructions from other vector load/store
instructions.
This can improve performance by avoiding unnecessary segment operation
when NF = 1.
Signed-off-by: Max Chou
---
target/riscv/helper.h |
Hi all,
When glibc with RVV support [1], the memcpy benchmark will run 2x to 60x
slower than the scalar equivalent on QEMU and it hurts developer
productivity.
>From the performance analysis result, we can observe that the glibc
memcpy spends most of the time in the vector unit-stride load/store
On 2/15/24 05:01, Jonathan Cameron wrote:
-static bool ptw_translate(PTETranslate *inout, hwaddr addr)
+static bool ptw_translate(PTETranslate *inout, hwaddr addr, uint64_t ra)
You do not need to pass in 'ra' here...
flags = probe_access_full(inout->env, addr, 0, MMU_DATA_STORE,
-
On Thu, Feb 15, 2024 at 04:34:32PM +, Conor Dooley wrote:
> On Thu, Feb 15, 2024 at 03:26:18PM +0100, Andrew Jones wrote:
> > On Thu, Feb 15, 2024 at 01:33:47PM +, Conor Dooley wrote:
> > > On Fri, Feb 02, 2024 at 12:21:51PM -0300, Daniel Henrique Barboza wrote:
> > > > The RVA22U64 and
On 2/15/24 05:01, Jonathan Cameron wrote:
From: Peter Maydell
Peter posted this in the thread trying to fix x86 TCG handling
of page tables in MMIO space (specifically emulated CXL interleaved memory)
On Fri, Nov 24, 2023 at 09:53:37PM +0800, shiju.j...@huawei.com wrote:
> From: Shiju Jose
>
> CXL spec 3.1 section 8.2.9.9.11.2 describes the DDR5 Error Check Scrub (ECS)
> control feature.
>
> The Error Check Scrub (ECS) is a feature defined in JEDEC DDR5 SDRAM
> Specification (JESD79-5) and
On Thu, 15 Feb 2024 at 18:40, Alex Bennée wrote:
>
> My default header template is GPLv3 but for QEMU code we really should
> stick to GPLv2-or-later (allowing others to up-license it if they
> wish). While this is test code we should still be consistent on the
> source distribution.
Test code,
15.02.2024 18:50, Peter Maydell пишет:
When msys2 updated their libusb packages to libusb 1.0.27, they
dropped support for building them for mingw32, leaving only mingw64
packages. This broke our CI job, as the 'pacman' package install now
fails with:
error: target not found:
On Fri, Nov 24, 2023 at 09:53:36PM +0800, shiju.j...@huawei.com wrote:
> From: Shiju Jose
>
> CXL spec 3.1 section 8.2.9.9.11.1 describes the device patrol scrub control
> feature. The device patrol scrub proactively locates and makes corrections
> to errors in regular cycle. The patrol scrub
On Thu, 15 Feb 2024, Richard Henderson wrote:
> On 2/14/24 22:47, Alexander Monakov wrote:
> >
> > On Wed, 14 Feb 2024, Richard Henderson wrote:
> >
> >> Because non-embedded aarch64 is expected to have AdvSIMD enabled, merely
> >> double-check with the compiler flags for __ARM_NEON and don't
My default header template is GPLv3 but for QEMU code we really should
stick to GPLv2-or-later (allowing others to up-license it if they
wish). While this is test code we should still be consistent on the
source distribution.
I wrote all of this code so its not a problem. However there remains
We should not wire IRQs on unrealized device.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
Reviewed-by: Mark Cave-Ayland
Reviewed-by: Richard Henderson
Message-Id: <20240213130341.1793-6-phi...@linaro.org>
---
hw/ppc/prep.c | 2 +-
1 file changed, 1 insertion(+), 1
On Fri, Nov 24, 2023 at 09:53:34PM +0800, shiju.j...@huawei.com wrote:
> From: Shiju Jose
>
> Add support for the feature commands, device patrol scrub control and
> DDR5 ECS control features.
>
> CXL spec 3.0 section 8.2.9.6 describes optional device specific features.
> CXL spec 3.1 section
From: Clément Chigot
Split out the headers for each peripherals and move them in their
right hardware directory.
Update Copyright and add SPDX-License-Identifier at the same time.
Co-developed-by: Frederic Konrad
Signed-off-by: Clément Chigot
Reviewed-by: Philippe Mathieu-Daudé
Message-ID:
Remove the unused CP0_SAARI register.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20240209090513.9401-10-phi...@linaro.org>
---
target/mips/cpu.h| 1 -
target/mips/sysemu/machine.c | 2 +-
2 files changed, 1 insertion(+), 2 deletions(-)
diff
From: Clément Chigot
Now there is an ncpus property, use it in order to deliver the IRQ to
multiple CPU.
Co-developed-by: Frederic Konrad
Signed-off-by: Clément Chigot
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <20240131085047.18458-5-chi...@adacore.com>
Signed-off-by: Philippe
We should not wire IRQs on unrealized device.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Damien Hedde
Reviewed-by: BALATON Zoltan
Reviewed-by: Richard Henderson
Message-Id: <20240213130341.1793-5-phi...@linaro.org>
---
hw/i386/pc_q35.c | 6 +++---
1 file changed, 3 insertions(+), 3
From: Pierrick Bouvier
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Pierrick Bouvier
Message-ID: <20240118032400.3762658-14-pierrick.bouv...@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
We can not create the Q35 machine without PCI, so simplify
pc_q35_init() removing pointless checks.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20240213041952.58840-1-phi...@linaro.org>
---
hw/i386/pc_q35.c | 32 ++--
1 file
Keep "hw/ide/ahci.h" AHCI-generic.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Leif Lindholm
Reviewed-by: Michael S. Tsirkin
Message-Id: <20240213081201.78951-10-phi...@linaro.org>
---
include/hw/arm/allwinner-a10.h | 2 +-
include/hw/arm/allwinner-r40.h | 2 +-
From: Clément Chigot
This allows the guest program to know its cpu id.
Co-developed-by: Frederic Konrad
Signed-off-by: Clément Chigot
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <20240131085047.18458-6-chi...@adacore.com>
Signed-off-by: Philippe
No need to duplicate AHCIState::ports, directly access it.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Michael S. Tsirkin
Reviewed-by: Richard Henderson
Message-Id: <20240213081201.78951-9-phi...@linaro.org>
---
include/hw/ide/ahci.h | 1 -
hw/ide/ahci.c | 3 +--
2 files
On Fri, Nov 24, 2023 at 09:53:35PM +0800, shiju.j...@huawei.com wrote:
> From: Shiju Jose
>
> CXL spec 3.0 section 8.2.9.6 describes optional device specific features.
> CXL devices supports features with changeable attributes.
> Get Supported Features retrieves the list of supported device
Explicitly set AHCIState::ports before calling ahci_realize().
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Michael S. Tsirkin
Reviewed-by: Richard Henderson
Message-Id: <20240213081201.78951-8-phi...@linaro.org>
---
hw/ide/ahci_internal.h | 2 +-
hw/ide/ahci.c | 9 +
Inline cpu_create() in order to call qdev_init_gpio_in_named()
before the CPU is realized.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
Reviewed-by: Mark Cave-Ayland
Message-Id: <20240215144623.76233-4-phi...@linaro.org>
---
hw/sparc/leon3.c | 7 ---
1 file changed, 4
QDev API provides the DEVICE() macro to access the
'qdev' parent field of the PCIDevice structure.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Michael S. Tsirkin
Reviewed-by: Richard Henderson
Message-Id: <20240213081201.78951-2-phi...@linaro.org>
---
hw/i386/pc_q35.c | 4 ++--
1 file
QEMU coding style recommend using structure typedefs:
https://www.qemu.org/docs/master/devel/style.html#typedefs
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-Id: <20240208181245.96617-2-phi...@linaro.org>
---
hw/ide/ich.c | 6 +++---
Since ahci_ide_create_devs() is not PCI specific, pass
it an AHCIState argument instead of PCIDevice.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Michael S. Tsirkin
Reviewed-by: Richard Henderson
Message-Id: <20240213081201.78951-6-phi...@linaro.org>
---
include/hw/ide/ahci.h | 2 +-
By passing a DeviceState context to a QDev IRQ handler,
we can simplify and use qdev_init_gpio_in_named() instead
of qdev_init_gpio_in_named_with_opaque().
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Mark Cave-Ayland
Message-Id: <20240215144623.76233-3-phi...@linaro.org>
---
Set I8257 instances parent (migration isn't affected).
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20240213114426.87836-1-phi...@linaro.org>
---
include/hw/dma/i8257.h | 2 +-
hw/dma/i82374.c| 2 +-
hw/dma/i8257.c | 4 +++-
From: Clément Chigot
CC: Fabien Chouteau
Signed-off-by: Clément Chigot
Reviewed-by: Fabien Chouteau
Message-ID: <20240131085047.18458-10-chi...@adacore.com>
Signed-off-by: Philippe Mathieu-Daudé
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS
In order to be able to QOM-embed a structure, we need
its full definition. Move it from "ahci_internal.h"
to the new "hw/ide/ahci-pci.h" header.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Michael S. Tsirkin
Reviewed-by: Richard Henderson
Message-Id:
From: Paolo Bonzini
ISA_SUPERIO does not provide an ISA bus, so it should not select the symbol:
instead it requires one. Among its users, VT82C686 is the only one that
is a PCI-ISA bridge and does not already select ISA_BUS.
Reviewed-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
From: Clément Chigot
Now that SMP is possible, the asr17 must be checked in the little boot
code or the secondary CPU will reinitialize the Timer and the Uart.
Co-developed-by: Frederic Konrad
Signed-off-by: Clément Chigot
Reviewed-by: Philippe Mathieu-Daudé
Message-ID:
Introduce the 'ich9' variable and inline ahci_get_num_ports().
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Michael S. Tsirkin
Reviewed-by: Richard Henderson
Message-Id: <20240213081201.78951-5-phi...@linaro.org>
---
include/hw/ide/ahci.h | 1 -
hw/i386/pc_q35.c | 6 --
DisasContext::saar is not used, remove it.
Reported-by: Paolo Bonzini
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20240209090513.9401-11-phi...@linaro.org>
---
target/mips/tcg/translate.h | 1 -
1 file changed, 1 deletion(-)
diff --git
From: Clément Chigot
This allows to register more than one CPU on the leon3_generic machine.
Co-developed-by: Frederic Konrad
Signed-off-by: Clément Chigot
Message-ID: <20240131085047.18458-8-chi...@adacore.com>
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sparc/leon3.c | 93
We want to access AHCIPCIState::ahci field. In order to keep
the code simple (avoiding >ahci), rename the current
'ahci' variable as 'pdev'
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Michael S. Tsirkin
Reviewed-by: Richard Henderson
Message-Id:
From: Paolo Bonzini
All users of ISA_SUPERIO include a floppy disk controller, serial port
and parallel port via the automatic creation mechanism of isa-superio.c.
Select the symbol and remove it from the dependents.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
Message-ID:
Previous commits removed the MT*C0(SAAR) helpers which
were using CPUMIPSState::itu, we can now remove it too.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20240209090513.9401-4-phi...@linaro.org>
---
target/mips/cpu.h | 1 -
hw/mips/cps.c | 1 -
2
AHCIState::ports should be unsigned. Besides, we never
check it for negative value. It is unlikely it was ever
used with more than INT32_MAX ports, so it is safe to
convert it to unsigned.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Michael S. Tsirkin
Reviewed-by: Richard Henderson
From: Clément Chigot
This adds a "ncpus" property to the "grlib-irqmp" device to be used
later, this required a little refactoring of how we initialize the
device (ie: use realize instead of init).
Co-developed-by: Frederic Konrad
Signed-off-by: Clément Chigot
Reviewed-by: Philippe
We should not wire IRQs on unrealized device.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
Reviewed-by: Mark Cave-Ayland
Reviewed-by: Richard Henderson
Message-Id: <20240213130341.1793-9-phi...@linaro.org>
---
hw/sparc/sun4m.c | 7 +--
1 file changed, 5 insertions(+),
From: Clément Chigot
According to the doc (see §4.2.15 in [1]), the reset operation should
not impact %SP.
[1] https://gaisler.com/doc/gr712rc-usermanual.pdf
Signed-off-by: Clément Chigot
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <20240131085047.18458-7-chi...@adacore.com>
Directly use the void pointer argument returned
by memory_region_get_ram_ptr().
Reviewed-by: Peter Maydell
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20240215132824.67363-3-phi...@linaro.org>
---
hw/sparc/leon3.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff
Instead of filling an array of all the possible IRQs, only call
qdev_get_gpio_in() when an IRQ is used. Remove the array from
RX62NState. Doing so we avoid calling qdev_get_gpio_in() on an
unrealized device.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
Reviewed-by: Yoshinori
By passing a DeviceState context to a QDev IRQ handler,
we can simplify and use qdev_init_gpio_in_named() instead
of qdev_init_gpio_in_named_with_opaque().
Suggested-by: Mark Cave-Ayland
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Mark Cave-Ayland
Message-Id:
From: Paolo Bonzini
isa-superio.c currently defines a SuperIO chip that is not used
by any other user of the file. Extract the chip to a separate file.
Reviewed-by: Bernhard Beschow
Signed-off-by: Paolo Bonzini
Message-ID: <20240213155005.109954-7-pbonz...@redhat.com>
[PMD: Update
'CPUSPARCState *env' argument is unused, remove it.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
Message-Id: <20240215132824.67363-2-phi...@linaro.org>
---
hw/sparc/leon3.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/hw/sparc/leon3.c
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