On 2/16/24 12:39, Hao Xiang wrote:
+void multifd_zero_page_check_recv(MultiFDRecvParams *p)
+{
+for (int i = 0; i < p->zero_num; i++) {
+void *page = p->host + p->zero[i];
+if (!buffer_is_zero(page, p->page_size)) {
+memset(page, 0, p->page_size);
+}
+
On 2024/2/6 下午5:20, Thomas Huth wrote:
On 06/02/2024 03.29, maobibo wrote:
Hi Philippe,
On 2024/2/5 下午8:58, Philippe Mathieu-Daudé wrote:
Hi Bibo,
On 5/2/24 03:13, Bibo Mao wrote:
The cdrom test skips to execute on LoongArch system with command
"make check", this patch enables cdrom test
On Fri, Jun 18, 2021 at 09:54:14AM +0100, Alex Bennée wrote:
>
> Marek Marczykowski-Górecki writes:
>
> > Kernel on Xen is loaded via fw_cfg. Previously it used non-DMA version,
> > which loaded the kernel (and initramfs) byte by byte. Change this
> > to DMA, to load in bigger chunks.
> > This
On 2/16/24 20:41, Richard Henderson wrote:
On 2/16/24 12:40, Daniel Henrique Barboza wrote:
After reading the reviews of patches 1 and 3 what I'm considering here is:
1 - drop patch 1;
Ok.
2 - there's a patch from Ivan Klokov sent 2 months ago:
"[PATCH 1/1] target/riscv: Clear
Unaligned 64-bit accesses were found in Linux to clobber carry bits,
resulting in bad results if an arithmetic operation involving a
carry bit was executed after an unaligned 64-bit operation.
hppa 2.0 defines additional carry bits in PSW register bits 32..39.
When restoring PSW after executing
On Thu, Feb 08, 2024 at 04:39:10PM +, Peter Maydell wrote:
> On Fri, 2 Feb 2024 at 20:48, Joe Komlodi wrote:
> >
> > It's possible for a reset to come in the middle of a transaction, which
> > causes the bus to be in an old state when a new transaction comes in.
> >
> > Signed-off-by: Joe
v3: https://patchew.org/QEMU/20240206204809.9859-1-amona...@ispras.ru/
v4:
https://patchew.org/QEMU/20240215081449.848220-1-richard.hender...@linaro.org/
Changes for v5:
- Move 3 byte sample back inline; document it.
- Drop AArch64 SVE alternative; neoverse-v2 still recommends simd for
From: Alexander Monakov
Increase unroll factor in SIMD loops from 4x to 8x in order to move
their bottlenecks from ALU port contention to load issue rate (two loads
per cycle on popular x86 implementations).
Avoid using out-of-bounds pointers in loop boundary conditions.
Follow SSE2
Benchmark each acceleration function vs an aligned buffer of zeros.
Signed-off-by: Richard Henderson
---
tests/bench/bufferiszero-bench.c | 42
tests/bench/meson.build | 4 ++-
2 files changed, 45 insertions(+), 1 deletion(-)
create mode 100644
From: Alexander Monakov
Test for length >= 256 inline, where is is often a constant.
Before calling into the accelerated routine, sample three bytes
from the buffer, which handles most non-zero buffers.
Signed-off-by: Alexander Monakov
Signed-off-by: Mikhail Romanov
Message-Id:
Because non-embedded aarch64 is expected to have AdvSIMD enabled, merely
double-check with the compiler flags for __ARM_NEON and don't bother with
a runtime check. Otherwise, model the loop after the x86 SSE2 function,
and use VADDV to reduce the four vector comparisons.
Signed-off-by: Richard
Because the three alternatives are monotonic, we don't
need to keep a couple of bitmasks, just identify the
strongest alternative at startup.
Signed-off-by: Richard Henderson
---
util/bufferiszero.c | 56 ++---
1 file changed, 22 insertions(+), 34
Signed-off-by: Richard Henderson
---
util/bufferiszero.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/util/bufferiszero.c b/util/bufferiszero.c
index a904b747c7..61ea59d2e0 100644
--- a/util/bufferiszero.c
+++ b/util/bufferiszero.c
@@ -26,7 +26,8 @@
#include
From: Alexander Monakov
Use of prefetching in bufferiszero.c is quite questionable:
- prefetches are issued just a few CPU cycles before the corresponding
line would be hit by demand loads;
- they are done for simple access patterns, i.e. where hardware
prefetchers can perform better;
-
From: Alexander Monakov
Thanks to early checks in the inline buffer_is_zero wrapper, the SIMD
routines are invoked much more rarely in normal use when most buffers
are non-zero. This makes use of AVX512 unprofitable, as it incurs extra
frequency and voltage transition periods during which the
From: Alexander Monakov
The SSE4.1 variant is virtually identical to the SSE2 variant, except
for using 'PTEST+JNZ' in place of 'PCMPEQB+PMOVMSKB+CMP+JNE' for testing
if an SSE register is all zeroes. The PTEST instruction decodes to two
uops, so it can be handled only by the complex decoder,
Split less-than and greater-than 256 cases.
Use unaligned accesses for head and tail.
Avoid using out-of-bounds pointers in loop boundary conditions.
Signed-off-by: Richard Henderson
---
util/bufferiszero.c | 86 +++--
1 file changed, 52 insertions(+), 34
From: Kaiwen Xue
This adds the indirect access registers required by sscsrind/smcsrind
and the operations on them. Note that xiselect and xireg are used for
both AIA and sxcsrind, and the behavior of accessing them depends on
whether each extension is enabled and the value stored in xiselect.
As per the ratified AIA spec v1.0, three stateen bits control AIA CSR
access.
Bit 60 controls the indirect CSRs
Bit 59 controls the most AIA CSR state
Bit 58 controls the IMSIC state such as stopei and vstopei
Enable the corresponding bits in [m|h]stateen and enable corresponding
checks in the
From: Kaiwen Xue
This adds the properties of smcdeleg/ssccfg. Implementation will be in
future patches.
Signed-off-by: Atish Patra
Signed-off-by: Kaiwen Xue
---
target/riscv/cpu.c | 4
target/riscv/cpu_cfg.h | 2 ++
2 files changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c
From: Kaiwen Xue
This adds checks in ops performed on xireg and xireg2-xireg6 so that the
counter delegation function will receive a valid xiselect value with the
proper extensions enabled.
Co-developed-by: Atish Patra
Signed-off-by: Kaiwen Xue
Signed-off-by: Atish Patra
---
From: Kaiwen Xue
This adds the properties for sxcsrind. Definitions of new registers and
implementations will come with future patches.
Signed-off-by: Atish Patra
Signed-off-by: Kaiwen Xue
---
target/riscv/cpu.c | 4
target/riscv/cpu_cfg.h | 2 ++
2 files changed, 6 insertions(+)
From: Kaiwen Xue
This adds definitions for counter delegation, including the new
scountinhibit register and the mstateen.CD bit.
Signed-off-by: Atish Patra
Signed-off-by: Kaiwen Xue
---
target/riscv/cpu.h | 1 +
target/riscv/cpu_bits.h | 8 +++-
target/riscv/machine.c | 1 +
3
From: Kaiwen Xue
Since xiselect and xireg also will be of use in sxcsrind, AIA should
have its own separated interface when those CSRs are accessed.
Signed-off-by: Atish Patra
Signed-off-by: Kaiwen Xue
---
target/riscv/csr.c | 147 +
1 file
From: Kaiwen Xue
The Smcdeleg/Ssccfg adds the support for counter delegation via
S*indcsr and Ssccfg.
It also adds a new shadow CSR scountinhibit and menvcfg enable bit (CDE)
to enable this extension and scountovf virtualization.
Signed-off-by: Kaiwen Xue
Co-developed-by: Atish Patra
This series adds the counter delegation extension support. The counter
delegation ISA extension(Smcdeleg/Ssccfg) actually depends on multiple ISA
extensions.
1. S[m|s]csrind : The indirect CSR extension[1] which defines additional
5 ([M|S|VS]IREG2-[M|S|VS]IREG6) register to address size
On 2/16/24 12:40, Daniel Henrique Barboza wrote:
After reading the reviews of patches 1 and 3 what I'm considering here is:
1 - drop patch 1;
Ok.
2 - there's a patch from Ivan Klokov sent 2 months ago:
"[PATCH 1/1] target/riscv: Clear vstart_qe_zero flag"
On Thu, Feb 8, 2024 at 8:39 AM Peter Maydell wrote:
>
> On Fri, 2 Feb 2024 at 20:48, Joe Komlodi wrote:
> >
> > It's possible for a reset to come in the middle of a transaction, which
> > causes the bus to be in an old state when a new transaction comes in.
> >
> > Signed-off-by: Joe Komlodi
>
Add myself to maintain multifd zero page checking acceleration function.
Signed-off-by: Hao Xiang
---
MAINTAINERS | 5 +
1 file changed, 5 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index a24c2b51b6..3ca407cb58 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3403,6 +3403,11 @@ F:
This change extends the MigrationStatus interface to track zero pages
and zero bytes counter.
Signed-off-by: Hao Xiang
---
migration/migration-hmp-cmds.c | 4
migration/migration.c | 2 ++
qapi/migration.json | 15 ++-
This change adds a dedicated handler for MigrationOps::ram_save_target_page in
multifd live migration. Now zero page checking can be done in the multifd
threads
and this becomes the default configuration. We still provide backward
compatibility
where zero page checking is done from the migration
This change adds zero page counters and updates multifd send/receive
tracing format to track the newly added counters.
Signed-off-by: Hao Xiang
---
migration/multifd.c| 43 ++
migration/multifd.h| 21 -
migration/ram.c|
v2 update:
* Implement zero-page-detection switch with enumeration "legacy",
"none" and "multifd".
* Move normal/zero pages from MultiFDSendParams to MultiFDPages_t.
* Add zeros and zero_bytes accounting.
This patchset is based on Juan Quintela's old series here
1. Implements the zero page detection and handling on the multifd
threads for non-compression, zlib and zstd compression backends.
2. Added a new value 'multifd' in ZeroPageDetection enumeration.
3. Add proper asserts to ensure pages->normal are used for normal pages
in all scenarios.
Now that zero page checking is done on the multifd sender threads by
default, we still provide an option for backward compatibility. This
change adds a qtest migration test case to set the zero-page-detection
option to "legacy" and run multifd migration with zero page checking on the
migration
This new parameter controls where the zero page checking is running.
1. If this parameter is set to 'legacy', zero page checking is
done in the migration main thread.
2. If this parameter is set to 'none', zero page checking is disabled.
Signed-off-by: Hao Xiang
---
On 2/16/24 15:56, Richard Henderson wrote:
On 2/16/24 03:57, Daniel Henrique Barboza wrote:
The 'vstart_eq_zero' flag which is used to determine if some insns, like
vector reductor operations, should SIGILL. At this moment the flag is
being updated only during cpu_get_tb_cpu_state(), at the
On 2/16/24 10:20, Alexander Monakov wrote:
FWIW, in situations like these I always recommend to run perf with fixed
sampling rate, i.e. 'perf record -e cycles:P -c 10' or 'perf record -e
cycles/period=10/P' to make sample counts between runs of different
duration directly comparable
Cc: qemu-sta...@nongnu.org
Fixes: 5427a9a7604 ("tcg: Add TCG_TARGET_CALL_{RET,ARG}_I128")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2169
Signed-off-by: Richard Henderson
---
See the gitlab issue for complete discussion of the ABI.
r~
---
tcg/aarch64/tcg-target.h | 6 +-
1
Now that all users of esp_fifo_pop_buf() operate on the main FIFO there is no
need to pass the FIFO explicitly.
Signed-off-by: Mark Cave-Ayland
---
hw/scsi/esp.c | 28 ++--
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
This allows these functions to be used earlier in the file without needing a
separate forward declaration.
Signed-off-by: Mark Cave-Ayland
---
hw/scsi/esp.c | 36 ++--
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
Signed-off-by: Mark Cave-Ayland
---
hw/scsi/esp.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
index 100560244b..7a24515bb9 100644
--- a/hw/scsi/esp.c
+++ b/hw/scsi/esp.c
@@ -312,7 +312,8 @@ static void do_message_phase(ESPState *s)
Now that all users of esp_fifo_pop() operate on the main FIFO there is no need
to pass the FIFO explicitly.
Signed-off-by: Mark Cave-Ayland
---
hw/scsi/esp.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
index b898e43e2b..0e42ff50e7
The ESP device has a DRQ (DMA request) signal that is used to handle flow
control
during DMA transfers. At the moment the DRQ signal is explicitly raised and
lowered at various points in the ESP state machine as required, rather than
implementing the logic described in the datasheet:
"DREQ will
This ensures that esp_update_drq() is called via esp_fifo_push() whenever the
host uses PDMA to transfer data to a SCSI device.
Signed-off-by: Mark Cave-Ayland
---
hw/scsi/esp.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
index
Instead of pushing data into the FIFO directly with fifo8_push_all(), add a new
esp_fifo_push_buf() function and use it accordingly.
Signed-off-by: Mark Cave-Ayland
---
hw/scsi/esp.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
There are still a few places that use fifo8_push() instead of esp_fifo_push() in
order to push a value into the FIFO. Update those places to use esp_fifo_push()
instead.
Signed-off-by: Mark Cave-Ayland
---
hw/scsi/esp.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
The aim is to restrict the esp_fifo_*() functions so that they only operate on
the hardware FIFO. When reading from cmdfifo in do_message_phase() use the
underlying Fifo8 functions directly.
Signed-off-by: Mark Cave-Ayland
---
hw/scsi/esp.c | 7 ++-
1 file changed, 6 insertions(+), 1
Now that all users of esp_fifo_push() operate on the main FIFO there is no need
to pass the FIFO explicitly.
Signed-off-by: Mark Cave-Ayland
---
hw/scsi/esp.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
index
The aim is to restrict the esp_fifo_*() functions so that they only operate on
the hardware FIFO. When reading from cmdfifo in do_command_phase() use the
underlying Fifo8 functions directly.
Signed-off-by: Mark Cave-Ayland
---
hw/scsi/esp.c | 4 ++--
1 file changed, 2 insertions(+), 2
Now the esp_update_drq() is called for all reads/writes to the FIFO, there is
no need to manually raise and lower the DRQ signal.
Signed-off-by: Mark Cave-Ayland
Fixes: https://gitlab.com/qemu-project/qemu/-/issues/611
Fixes: https://gitlab.com/qemu-project/qemu/-/issues/1831
---
hw/scsi/esp.c
This ensures that the DRQ line is always set correctly when reading/writing
single bytes to/from the FIFO.
Signed-off-by: Mark Cave-Ayland
---
hw/scsi/esp.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
index
This new function sets the DRQ line correctly according to the current transfer
mode, direction and FIFO contents. Update esp_fifo_push_buf() and
esp_fifo_pop_buf()
to use it so that DRQ is always set correctly when reading/writing multiple
bytes
to/from the FIFO.
Signed-off-by: Mark
On Thu, 15 Feb 2024, Richard Henderson wrote:
> On 2/15/24 13:37, Alexander Monakov wrote:
> > Ah, I guess you might be running at low perf_event_paranoid setting that
> > allows unprivileged sampling of kernel events? In our submissions the
> > percentage was for perf_event_paranoid=2, i.e.
Signed-off-by: Het Gala
---
qapi/migration.json | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/qapi/migration.json b/qapi/migration.json
index 5a565d9b8d..5756e650b0 100644
--- a/qapi/migration.json
+++ b/qapi/migration.json
@@ -1728,6 +1728,7 @@
#
# -> {
On 16/2/24 18:14, BALATON Zoltan wrote:
On Fri, 16 Feb 2024, Philippe Mathieu-Daudé wrote:
We want to set another qdev property (a link) for the pl110
and pl111 devices, we can not use sysbus_create_simple() which
only passes sysbus base address and IRQs as arguments. Inline
it so we can set
A few watchdog devices use qemu_system_reset_request(). This is not ideal since
behaviour of watchdog-expiry can't be changed by QMP using `watchdog_action`.
As stated in BiteSizedTasks wiki page, instead of using
qemu_system_reset_request()
to reset when a watchdog timer expires, let
A few watchdog devices use qemu_system_reset_request(). This is not ideal since
behaviour of watchdog-expiry can't be changed by QMP using `watchdog_action`.
As stated in BiteSizedTasks wiki page, instead of using
qemu_system_reset_request()
to reset when a watchdog timer expires, let
A few watchdog devices use qemu_system_reset_request(). This is not ideal since
behaviour of watchdog-expiry can't be changed by QMP using `watchdog_action`.
As stated in BiteSizedTasks wiki page, instead of using
qemu_system_reset_request()
to reset when a watchdog timer expires, let
On 2/16/24 05:12, Michael Tokarev wrote:
07.02.2024 05:52, Richard Henderson :
When we added SVE_MTEDESC_SHIFT, we effectively limited the
maximum size of MTEDESC. Adjust SIZEM1 to consume the remaining
bits (32 - 10 - 5 - 12 == 5). Assert that the data to be stored
fits within the field
On 2/16/24 03:57, Daniel Henrique Barboza wrote:
In the Vector spec section 3.2 [1]:
"When mstatus.VS is set to Initial or Clean, executing any instruction
that changes vector state, including the vector CSRs, will change
mstatus.VS to Dirty."
ldst_us_trans(), ldst_stride_trans(),
On 2/16/24 03:57, Daniel Henrique Barboza wrote:
The 'vstart_eq_zero' flag which is used to determine if some insns, like
vector reductor operations, should SIGILL. At this moment the flag is
being updated only during cpu_get_tb_cpu_state(), at the start of each
translation block.
This cadence
On Thu, Feb 15, 2024 at 07:01:46PM +0800, shiju.j...@huawei.com wrote:
> 56.china.huawei.com (7.191.161.198)
> Status: O
> Content-Length: 7949
> Lines: 181
>
> From: Shiju Jose
>
> CXL spec 3.1 section 8.2.9.9.11.2 describes the DDR5 Error Check Scrub (ECS)
> control feature.
>
> The
I agree, comment here is redundant, i will fix
it in the next patch.
Abhiram
On Fri, 16 Feb 2024 at 20:19, Peter Maydell
wrote:
> On Fri, 16 Feb 2024 at 13:56, Abhiram Tilak wrote:
> >
> > A few watchdog devices use qemu_system_reset_request(). This is not
> ideal since
> > behaviour of
On Thu, Feb 15, 2024 at 07:01:45PM +0800, shiju.j...@huawei.com wrote:
> From: Shiju Jose
>
> CXL spec 3.1 section 8.2.9.9.11.1 describes the device patrol scrub control
> feature. The device patrol scrub proactively locates and makes corrections
> to errors in regular cycle. The patrol scrub
On Thu, Feb 15, 2024 at 07:01:44PM +0800, shiju.j...@huawei.com wrote:
> From: Shiju Jose
>
> CXL spec 3.1 section 8.2.9.6 describes optional device specific features.
> CXL devices supports features with changeable attributes.
> Get Supported Features retrieves the list of supported device
probe_target_compiler() when checking for multilib support checks if
-nostdlib works together with -lgcc. It isn't necessary for building
various components in pc-bios/optionrom, as evidenced by looking at
actually used link flags there.
Alpine Linux for x86_64 does not ship with 32bit libgcc, but
I will exclude this patch from the series for now.
According to the discussions, the current code honours the
guest's preference.
Will wait for the enhancements needed in watchdog QAPI.
Abhiram
On Fri, 16 Feb 2024 at 20:24, Peter Maydell
wrote:
> On Fri, 16 Feb 2024 at 13:56, Abhiram Tilak
Hi,
We want to convert some VMWARE VM to KVM, and to reduce the VM down
time, we want to do it in two steps copy approach:
1. a snapshot is taken
- source VM continues to run on VMware => diff creates
2. snapshot is available for download as vmdk
- we need a software to copy snapshot to target
Ilya Leoshkevich writes:
> The upcoming follow-fork-mode child support requires knowing the child
> pid. Pass it down.
>
> Signed-off-by: Ilya Leoshkevich
> ---
> bsd-user/freebsd/os-proc.h | 6 +++---
> bsd-user/main.c | 4 +++-
> bsd-user/qemu.h | 2 +-
>
Ilya Leoshkevich writes:
> The upcoming follow-fork-mode child support requires knowing when
> fork() is about to happen in order to initialize its state. Add a hook
> for that.
>
> Signed-off-by: Ilya Leoshkevich
Reviewed-by: Alex Bennée
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
Ilya Leoshkevich writes:
> Currently ts_tid contains the parent tid after fork(), which is not
> correct. So far it has not affected anything, but the upcoming
> follow-fork-mode child support relies on the correct value, so fix it.
>
> Signed-off-by: Ilya Leoshkevich
> ---
> bsd-user/main.c
Cédric Le Goater writes:
> Hello Fabiano
>
> On 2/14/24 21:35, Fabiano Rosas wrote:
>> Cédric Le Goater writes:
>>
>>> Hello Fabiano
>>>
>>> On 2/8/24 14:29, Fabiano Rosas wrote:
Cédric Le Goater writes:
> In case of error, close_return_path_on_source() can perform a shutdown
On Fri, Feb 16, 2024 at 10:16:12AM +, Shiju Jose wrote:
> Hi Fan,
>
> >-Original Message-
> >From: fan
> >Sent: 15 February 2024 18:47
> >To: Shiju Jose
> >Cc: qemu-devel@nongnu.org; linux-...@vger.kernel.org; Jonathan Cameron
> >; tanxiaofei ;
> >Zengtao (B) ; Linuxarm ;
>
> -Original Message-
> From: Taylor Simpson
> Sent: Tuesday, February 13, 2024 10:27 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ; Marco
> Liebel (QUIC) ; richard.hender...@linaro.org;
> phi...@linaro.org; a...@rev.ng; a...@rev.ng;
> -Original Message-
> From: Taylor Simpson
> Sent: Tuesday, February 13, 2024 10:27 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ; Marco
> Liebel (QUIC) ; richard.hender...@linaro.org;
> phi...@linaro.org; a...@rev.ng; a...@rev.ng;
> -Original Message-
> From: Taylor Simpson
> Sent: Tuesday, February 13, 2024 10:27 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ; Marco
> Liebel (QUIC) ; richard.hender...@linaro.org;
> phi...@linaro.org; a...@rev.ng; a...@rev.ng;
On Fri, 16 Feb 2024, Philippe Mathieu-Daudé wrote:
We want to set another qdev property (a link) for the pl110
and pl111 devices, we can not use sysbus_create_simple() which
only passes sysbus base address and IRQs as arguments. Inline
it so we can set the link property in the next commit.
Ilya Leoshkevich writes:
> The upcoming follow-fork-mode child support will require disabling
> gdbstub in the parent process, which may have multiple threads (which
> are represented as CPUs).
>
> Loop over all CPUs in order to remove breakpoints and disable
> single-step. Move the respective
From: Pierrick Bouvier
When scoreboards need to be reallocated.
Signed-off-by: Pierrick Bouvier
Reviewed-by: Richard Henderson
Message-Id: <20240213094009.150349-8-pierrick.bouv...@linaro.org>
Signed-off-by: Alex Bennée
---
docs/devel/multi-thread-tcg.rst | 1 +
1 file changed, 1
This makes them a bit more visible in the TCG emulation menu rather
than hiding them away bellow the ToC limit.
Message-Id: <20240103173349.398526-43-alex.ben...@linaro.org>
Reviewed-by: Pierrick Bouvier
Signed-off-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
---
We can only request a list of registers once the vCPU has been
initialised so the user needs to use either call the get function on
vCPU initialisation or during the translation phase.
We don't expose the reg number to the plugin instead hiding it behind
an opaque handle. This allows for a bit of
From: Pierrick Bouvier
This ensures we run during a cpu_exec, which allows to call start/end
exclusive from this init hook (needed for new scoreboard API introduced
later).
async work is run before any tb is translated/executed, so we can
guarantee plugin init will be called before any other
With the new plugin register API we can now track changes to register
values. Currently the implementation is fairly dumb which will slow
down if a large number of register values are being tracked. This
could be improved by only instrumenting instructions which mention
registers we are interested
While we attempt to hide implementation details from the plugin we
shouldn't be totally obtuse. Let the user know what they can and can't
expect with the various instrumentation options.
Message-Id: <20240103173349.398526-44-alex.ben...@linaro.org>
Reviewed-by: Pierrick Bouvier
Signed-off-by:
From: Pierrick Bouvier
We found that vcpu_init_hook was called *after* idle callback.
vcpu_init is called from cpu_realize_fn, while idle/resume cb are called
from qemu_wait_io_event (in vcpu thread).
This change ensures we only call idle and resume cb only once a plugin
was init for a given
Expose an internal API to QEMU to return all the registers for a vCPU.
The list containing the details required to called gdb_read_register().
Based-on: <20231025093128.33116-15-akihiko.od...@daynix.com>
Cc: Akihiko Odaki
Message-Id: <20240103173349.398526-38-alex.ben...@linaro.org>
We can't directly save the ephemeral imatch from argv as that memory
will get recycled.
Message-Id: <20240103173349.398526-40-alex.ben...@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
---
contrib/plugins/execlog.c | 2 +-
1 file
From: Akihiko Odaki
This avoids optimizations incompatible when reading registers.
Signed-off-by: Akihiko Odaki
Reviewed-by: Pierrick Bouvier
Message-Id: <20240103173349.398526-37-alex.ben...@linaro.org>
Message-Id: <20231213-gdb-v17-12-777047380...@daynix.com>
Signed-off-by: Alex Bennée
From: Akihiko Odaki
GDBFeature has the num_regs member so use it where applicable to
remove magic numbers.
Signed-off-by: Akihiko Odaki
Message-Id: <20240103173349.398526-34-alex.ben...@linaro.org>
Message-Id: <20231213-gdb-v17-8-777047380...@daynix.com>
Signed-off-by: Alex Bennée
---
From: Pierrick Bouvier
This information is already accessible using qemu_info_t during plugin
install.
We will introduce another function (qemu_plugin_num_vcpus) which
represent how many cpus were enabled, by tracking new cpu indexes.
It's a breaking change, so we bump API version.
From: Akihiko Odaki
These members will be used to help plugins to identify registers.
The added members in instances of GDBFeature dynamically generated by
CPUs will be filled in later changes.
Signed-off-by: Akihiko Odaki
Message-Id: <20240103173349.398526-36-alex.ben...@linaro.org>
From: Akihiko Odaki
In preparation for a change to use GDBFeature as a parameter of
gdb_register_coprocessor(), convert the internal representation of
dynamic feature from plain XML to GDBFeature.
Signed-off-by: Akihiko Odaki
Reviewed-by: Richard Henderson
Message-Id:
From: Akihiko Odaki
Align the parameters of gdb_get_reg_cb and gdb_set_reg_cb with the
gdb_read_register and gdb_write_register members of CPUClass to allow
to unify the logic to access registers of the core and coprocessors
in the future.
Signed-off-by: Akihiko Odaki
Reviewed-by: Alex Bennée
From: Akihiko Odaki
Now we know all instances of GDBFeature that is used in CPU so we can
traverse them to find XML. This removes the need for a CPU-specific
lookup function for dynamic XMLs.
Signed-off-by: Akihiko Odaki
Reviewed-by: Alex Bennée
Message-Id:
From: Akihiko Odaki
In preparation for a change to use GDBFeature as a parameter of
gdb_register_coprocessor(), convert the internal representation of
dynamic feature from plain XML to GDBFeature.
Signed-off-by: Akihiko Odaki
Message-Id: <20240103173349.398526-29-alex.ben...@linaro.org>
From: Akihiko Odaki
This function is no longer used.
Signed-off-by: Akihiko Odaki
Reviewed-by: Alex Bennée
Message-Id: <20240103173349.398526-35-alex.ben...@linaro.org>
Message-Id: <20231213-gdb-v17-9-777047380...@daynix.com>
Signed-off-by: Alex Bennée
---
include/hw/core/cpu.h | 4
From: Akihiko Odaki
Simplify GDBRegisterState by replacing num_regs and xml members with
one member that points to GDBFeature.
Signed-off-by: Akihiko Odaki
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20240103173349.398526-31-alex.ben...@linaro.org>
Message-Id:
From: Akihiko Odaki
This is a tree-wide change to introduce GDBFeature parameter to
gdb_register_coprocessor(). The new parameter just replaces num_regs
and xml parameters for now. GDBFeature will be utilized to simplify XML
lookup in a following change.
Signed-off-by: Akihiko Odaki
Acked-by:
My default header template is GPLv3 but for QEMU code we really should
stick to GPLv2-or-later (allowing others to up-license it if they
wish). While this is test code we should still be consistent on the
source distribution.
I wrote all of this code so its not a problem. However there remains
1 - 100 of 255 matches
Mail list logo
