On Wed Apr 24, 2024 at 8:31 AM AEST, BALATON Zoltan wrote:
> This series does some further clean up mostly around BookE MMU to
> untangle it from other MMU models. It also contains some other changes
> that I've come up with while working on this. The first 3 patches are
> from the last exception
From: Dongwon Kim
When untabifying, the default size of the new window was inadvertently
set to the size smaller than quarter of the primary window size due
to lack of explicit configuration. This commit addresses the issue by
ensuring that the size of untabified windows is set to match the
-04-29 14:34:25 -0700)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20240430
for you to fetch changes up to a0c325c4b05cf7815739d6a84e567b95c8c5be7e:
tests/qtest : Add testcase for DM163 (2024-04-30 16:05:08 +0100
On 4/30/24 00:13, Thomas Huth wrote:
Hi Richard!
The following changes since commit 5fee33d97a7f2e95716417bd164f2f5264acd976:
Merge tag 'samuel-thibault' ofhttps://people.debian.org/~sthibault/qemu
into staging (2024-04-29 14:34:25 -0700)
are available in the Git repository at:
On Tue, Apr 30, 2024 at 09:00:17PM +0200, Philippe Mathieu-Daudé wrote:
> On 30/4/24 20:45, Philippe Mathieu-Daudé wrote:
> > Hi Ilya,
> >
> > On 30/4/24 19:55, Ilya Leoshkevich wrote:
> > > On Tue, Apr 30, 2024 at 02:27:54PM +0200, Philippe Mathieu-Daudé wrote:
> > > > Missing WASM testing by
On 4/30/24 15:08, James Bottomley wrote:
The requested feedback was to convert the tpmdev handler to being json
based, which requires rethreading all the backends. The good news is
this reduced quite a bit of code (especially as I converted it to
error_fatal handling as well, which removes
On 4/30/24 15:08, James Bottomley wrote:
The Microsoft Simulator (mssim) is the reference emulation platform
for the TCG TPM 2.0 specification.
https://github.com/Microsoft/ms-tpm-20-ref.git
It exports a fairly simple network socket based protocol on two
sockets, one for command (default
On 30/4/24 21:42, Richard Henderson wrote:
Because the three alternatives are monotonic, we don't need
to keep a couple of bitmasks, just identify the strongest
alternative at startup.
Generalize test_buffer_is_zero_next_accel and init_accel
by always defining an accel_table array.
On Wed, Apr 17, 2024 at 03:50:52PM +0800, Shiyang Ruan wrote:
> The length of Physical Address in General Media Event Record/DRAM Event
> Record is 64-bit, so the field mask should be defined as such length.
> Otherwise, this causes cxl_general_media and cxl_dram tracepoints to
> mask off the
>From 617b2d92085d03524dcf5c223568a4856cdff47f Mon Sep 17 00:00:00 2001
From: Ryan Mamone
Date: Tue, 30 Apr 2024 13:20:50 -0400
Subject: [PATCH] hw/display: Add SSD1306 dot matrix display controller support
Signed-off-by: Ryan Mamone
---
hw/display/Kconfig | 5 +
hw/display/meson.build |
On 4/30/24 10:27 AM, Igor Mammedov wrote:
On Fri, 3 Nov 2023 13:56:02 +0300
Dmitrii Gavrilov wrote:
Seems related to cpu hotpug issues,
CCing Boris for awareness.
Thank you Igor.
This patch appears to change timing in my test which makes the problem
much more difficult to reproduce.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
util/bufferiszero.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/util/bufferiszero.c b/util/bufferiszero.c
index c9a7ded016..f9af7841ba 100644
--- a/util/bufferiszero.c
+++
From: Alexander Monakov
Thanks to early checks in the inline buffer_is_zero wrapper, the SIMD
routines are invoked much more rarely in normal use when most buffers
are non-zero. This makes use of AVX512 unprofitable, as it incurs extra
frequency and voltage transition periods during which the
Because the three alternatives are monotonic, we don't need
to keep a couple of bitmasks, just identify the strongest
alternative at startup.
Generalize test_buffer_is_zero_next_accel and init_accel
by always defining an accel_table array.
Signed-off-by: Richard Henderson
---
From: Alexander Monakov
Use of prefetching in bufferiszero.c is quite questionable:
- prefetches are issued just a few CPU cycles before the corresponding
line would be hit by demand loads;
- they are done for simple access patterns, i.e. where hardware
prefetchers can perform better;
-
Because non-embedded aarch64 is expected to have AdvSIMD enabled, merely
double-check with the compiler flags for __ARM_NEON and don't bother with
a runtime check. Otherwise, model the loop after the x86 SSE2 function.
Use UMAXV for the vector reduction. This is 3 cycles on cortex-a76 and
2
v3: https://patchew.org/QEMU/20240206204809.9859-1-amona...@ispras.ru/
v6:
https://patchew.org/QEMU/20240424225705.929812-1-richard.hender...@linaro.org/
Changes for v7:
- Generalize test_buffer_is_zero_next_accel and initialization (phil)
r~
Alexander Monakov (5):
util/bufferiszero:
Split less-than and greater-than 256 cases.
Use unaligned accesses for head and tail.
Avoid using out-of-bounds pointers in loop boundary conditions.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
util/bufferiszero.c | 85 +++--
From: Alexander Monakov
Test for length >= 256 inline, where is is often a constant.
Before calling into the accelerated routine, sample three bytes
from the buffer, which handles most non-zero buffers.
Signed-off-by: Alexander Monakov
Signed-off-by: Mikhail Romanov
Message-Id:
From: Alexander Monakov
Increase unroll factor in SIMD loops from 4x to 8x in order to move
their bottlenecks from ALU port contention to load issue rate (two loads
per cycle on popular x86 implementations).
Avoid using out-of-bounds pointers in loop boundary conditions.
Follow SSE2
From: Alexander Monakov
The SSE4.1 variant is virtually identical to the SSE2 variant, except
for using 'PTEST+JNZ' in place of 'PCMPEQB+PMOVMSKB+CMP+JNE' for testing
if an SSE register is all zeroes. The PTEST instruction decodes to two
uops, so it can be handled only by the complex decoder,
Benchmark each acceleration function vs an aligned buffer of zeros.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tests/bench/bufferiszero-bench.c | 47
tests/bench/meson.build | 1 +
2 files changed, 48 insertions(+)
> -Original Message-
> From: Matheus Tavares Bernardino
> Sent: Tuesday, April 30, 2024 9:25 AM
> To: qemu-devel@nongnu.org
> Cc: bc...@quicinc.com; sidn...@quicinc.com; a...@rev.ng; a...@rev.ng;
> ltaylorsimp...@gmail.com; richard.hender...@linaro.org; Laurent Vivier
>
> Subject:
On 30/4/24 21:08, Thomas Huth wrote:
The sclpconsole currently does not have a proper parent in the QOM
tree, so it shows up under /machine/unattached - which is somewhat
ugly. We should rather attach it to /machine/sclp/s390-sclp-event-facility
where the other devices of type TYPE_SCLP_EVENT
On 30.04.24 21:08, Thomas Huth wrote:
The sclpconsole currently does not have a proper parent in the QOM
tree, so it shows up under /machine/unattached - which is somewhat
ugly. We should rather attach it to /machine/sclp/s390-sclp-event-facility
where the other devices of type TYPE_SCLP_EVENT
The Microsoft Simulator (mssim) is the reference emulation platform
for the TCG TPM 2.0 specification.
https://github.com/Microsoft/ms-tpm-20-ref.git
It exports a fairly simple network socket based protocol on two
sockets, one for command (default 2321) and one for control (default
2322). This
Instead of processing the tpmdev options using the old qemu options,
convert to the new visitor format which also allows the passing of
json on the command line.
Signed-off-by: James Bottomley
Tested-by: Stefan Berger
Reviewed-by: Stefan Berger
---
v4: add TpmConfiOptions
v5: exit(0) for help
The requested feedback was to convert the tpmdev handler to being json
based, which requires rethreading all the backends. The good news is
this reduced quite a bit of code (especially as I converted it to
error_fatal handling as well, which removes the return status
threading). The bad news is
The sclpconsole currently does not have a proper parent in the QOM
tree, so it shows up under /machine/unattached - which is somewhat
ugly. We should rather attach it to /machine/sclp/s390-sclp-event-facility
where the other devices of type TYPE_SCLP_EVENT already reside.
Signed-off-by: Thomas
On Fri, Apr 26, 2024 at 3:40 PM Peter Maydell wrote:
> > +addr = memory_region_get_ram_ptr(mr) + section.offset_within_region;
> > +rb = qemu_ram_block_from_host(addr, false, );
>
> ...and this call to qemu_ram_block_from_host() will only initialize
> offset if it does not fail (i.e.
On 30/04/2024 16.24, Thomas Huth wrote:
On 30/04/2024 13.58, Cédric Le Goater wrote:
On 4/30/24 10:04, Thomas Huth wrote:
The sclpconsole currently does not have a proper parent in the QOM
tree, so it shows up under /machine/unattached - which is somewhat
ugly. Let's attach it to /machine/sclp
On 30/4/24 20:45, Philippe Mathieu-Daudé wrote:
Hi Ilya,
On 30/4/24 19:55, Ilya Leoshkevich wrote:
On Tue, Apr 30, 2024 at 02:27:54PM +0200, Philippe Mathieu-Daudé wrote:
Missing WASM testing by Ilya (branch available at
https://gitlab.com/philmd/qemu/-/commits/tcg_flush_jmp_cache)
Hmm, it
Hi Ilya,
On 30/4/24 19:55, Ilya Leoshkevich wrote:
On Tue, Apr 30, 2024 at 02:27:54PM +0200, Philippe Mathieu-Daudé wrote:
Missing WASM testing by Ilya (branch available at
https://gitlab.com/philmd/qemu/-/commits/tcg_flush_jmp_cache)
Hmm, it dies very early now:
# gdb --args
On Tue, 30 Apr 2024 at 18:15, Alex Bennée wrote:
>
> Peter Maydell writes:
>
> > The TCGCPUOps::cpu_exec_halt method is called from cpu_handle_halt()
> > when the CPU is halted, so that a target CPU emulation can do
> > anything target-specific it needs to do. (At the moment we only use
> >
On Tue, 30 Apr 2024 at 18:31, Richard Henderson
wrote:
>
> On 4/30/24 07:00, Peter Maydell wrote:
> > +if (uadd64_overflow(timeout, offset, )) {
> > +nexttick = UINT64_MAX;
> > +}
> > +if (nexttick > INT64_MAX / gt_cntfrq_period_ns(cpu)) {
> > +/*
> > + * If
> -Original Message-
> From: Richard Henderson
> Sent: Tuesday, April 30, 2024 10:53 AM
> To: Matheus Bernardino (QUIC) ; qemu-
> de...@nongnu.org
> Cc: Brian Cain ; Sid Manning ;
> a...@rev.ng; a...@rev.ng; ltaylorsimp...@gmail.com; Laurent Vivier
>
> Subject: Re: [PATCH v3] Hexagon:
On 4/30/24 09:47, Dario Binacchi wrote:
The fp-bench test (i. e. tests/fp/fp-bench.c) use fenv.h that is not
always provided by the libc (uClibc). The patch disables its compilation
in case the header is not available.
Since uclibc has had fenv.h since 2008, are you sure this isn't simply a
On Mon, Apr 29, 2024 at 1:19 PM Jonah Palmer wrote:
>
>
>
> On 4/29/24 4:14 AM, Eugenio Perez Martin wrote:
> > On Thu, Apr 25, 2024 at 7:44 PM Si-Wei Liu wrote:
> >>
> >>
> >>
> >> On 4/24/2024 12:33 AM, Eugenio Perez Martin wrote:
> >>> On Wed, Apr 24, 2024 at 12:21 AM Si-Wei Liu wrote:
>
On 4/29/24 16:28, Atish Patra wrote:
scounteren/hcountern are also WARL registers similar to mcountern.
Only set the bits for the available counters during the write to
preserve the WARL behavior.
Signed-off-by: Atish Patra
---
Reviewed-by: Daniel Henrique Barboza
target/riscv/csr.c
On 4/29/24 16:28, Atish Patra wrote:
Currently, if a counter monitoring cycle/instret is stopped via
mcountinhibit we just update the state while the value is saved
during the next read. This is not accurate as the read may happen
many cycles after the counter is stopped. Ideally, the read
On Tue, Apr 30, 2024 at 02:27:54PM +0200, Philippe Mathieu-Daudé wrote:
> Missing WASM testing by Ilya (branch available at
> https://gitlab.com/philmd/qemu/-/commits/tcg_flush_jmp_cache)
Hmm, it dies very early now:
# gdb --args ./qemu-s390x -L /usr/s390x-linux-gnu
On Mon, Apr 29, 2024 at 09:58:42AM +0200, Markus Armbruster wrote:
> fan writes:
>
> > On Fri, Apr 26, 2024 at 11:12:50AM +0200, Markus Armbruster wrote:
> >> nifan@gmail.com writes:
>
> [...]
>
> >> > diff --git a/qapi/cxl.json b/qapi/cxl.json
> >> > index 4281726dec..2dcf03d973 100644
>
On 4/30/24 07:00, Peter Maydell wrote:
The TCGCPUOps::cpu_exec_halt method is called from cpu_handle_halt()
when the CPU is halted, so that a target CPU emulation can do
anything target-specific it needs to do. (At the moment we only use
this on i386.)
The current specification of the method
[...]
Thank you all for the valuable feedback. Since the QEMU interface seems
stable, I will rework my libvirt (not upstream) and post as an RFC.
--
Regards,
Collin
Call pci_default_write_config() in xen_pt_pci_write_config() only for
registers that have matching XenPTRegInfo structure, and do that only after
resolving any custom handlers. This is important for two reasons:
1. XenPTRegInfo has ro_mask which needs to be enforced - Xen-specific
hooks do that
The /dev/mem is used for two purposes:
- reading PCI_MSIX_ENTRY_CTRL_MASKBIT
- reading Pending Bit Array (PBA)
The first one was originally done because when Xen did not send all
vector ctrl writes to the device model, so QEMU might have outdated old
register value. If Xen is new enough, this
This series fixes handling MSI-X when device model is running in a stubdomain.
The main part is to avoid accessing /dev/mem, which also fixes running dom0
with lockdown enabled.
It depends on a behavior change of Xen that was just comitted, and signaled
with a feature flag. If Xen is too old (and
Update it to get XENFEAT_dm_msix_all_writes for the next patch.
Signed-off-by: Marek Marczykowski-Górecki
---
include/hw/xen/interface/features.h | 17 +
1 file changed, 17 insertions(+)
diff --git a/include/hw/xen/interface/features.h
b/include/hw/xen/interface/features.h
On 4/30/24 07:00, Peter Maydell wrote:
+if (uadd64_overflow(timeout, offset, )) {
+nexttick = UINT64_MAX;
+}
+if (nexttick > INT64_MAX / gt_cntfrq_period_ns(cpu)) {
+/*
+ * If the timeout is too long for the signed 64-bit range
+ * of a QEMUTimer, let
Alexandra Diupina writes:
As the subject is what ends up in the shortlog it is useful to prefix
the subsystem to make it easier to see what was touched when reviewing
log files. So maybe:
xlnx_dpdma: fix endianness bug
or even:
xlnx_dpdma: fix descriptor endianness bug
as we have space
Preallocate filter allows to implement really interesting setups.
Assume that we have
* shared block device, f.e. iSCSI LUN, implemented with some HW device
* clustered LVM on top of it
* QCOW2 image stored inside LVM volume
This allows very cheap clustered setups with all QCOW2 features intact.
On Mon, 29 Apr 2024 09:58:42 +0200
Markus Armbruster wrote:
> fan writes:
>
> > On Fri, Apr 26, 2024 at 11:12:50AM +0200, Markus Armbruster wrote:
> >> nifan@gmail.com writes:
>
> [...]
>
> >> > diff --git a/qapi/cxl.json b/qapi/cxl.json
> >> > index 4281726dec..2dcf03d973 100644
>
On Tue, Apr 30, 2024 at 7:55 AM Si-Wei Liu wrote:
>
>
>
> On 4/29/2024 1:14 AM, Eugenio Perez Martin wrote:
> > On Thu, Apr 25, 2024 at 7:44 PM Si-Wei Liu wrote:
> >>
> >>
> >> On 4/24/2024 12:33 AM, Eugenio Perez Martin wrote:
> >>> On Wed, Apr 24, 2024 at 12:21 AM Si-Wei Liu wrote:
>
>
Peter Maydell writes:
> The TCGCPUOps::cpu_exec_halt method is called from cpu_handle_halt()
> when the CPU is halted, so that a target CPU emulation can do
> anything target-specific it needs to do. (At the moment we only use
> this on i386.)
>
> The current specification of the method doesn't
Dario Binacchi writes:
> The fp-bench test (i. e. tests/fp/fp-bench.c) use fenv.h that is not
> always provided by the libc (uClibc). The patch disables its compilation
> in case the header is not available.
>
> The patch is based on a suggestion from Paolo Bonzini, which you can
> find at the
This parameter is always passed as 'false' from the caller.
Signed-off-by: Denis V. Lunev
CC: Andrey Zhadchenko
CC: Kevin Wolf
CC: Hanna Reitz
---
block/file-posix.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/block/file-posix.c b/block/file-posix.c
index
On Tue, Apr 30, 2024 at 12:29:14PM +0200, Thomas Huth wrote:
> On 30/04/2024 11.55, Daniel P. Berrangé wrote:
> > On Tue, Apr 30, 2024 at 08:45:29AM +0200, Thomas Huth wrote:
> > > Old machine types often have bugs or work-arounds that affect our
> > > possibilities to move forward with the QEMU
From: "Edgar E. Iglesias"
Add xen_mr_is_memory() to abstract away tests for the
xen_memory MR.
Signed-off-by: Edgar E. Iglesias
---
hw/xen/xen-hvm-common.c | 8 +++-
include/sysemu/xen.h| 8
system/physmem.c| 2 +-
3 files changed, 16 insertions(+), 2 deletions(-)
From: "Edgar E. Iglesias"
Propagate MR and is_write to xen_map_cache().
This is in preparation for adding support for grant mappings.
No functional change.
Signed-off-by: Edgar E. Iglesias
---
hw/xen/xen-mapcache.c | 10 ++
include/sysemu/xen-mapcache.h | 11 +++
From: "Edgar E. Iglesias"
Make xen_map_cache take a MapCache as argument. This is in
prepaparation to support multiple map caches.
No functional changes.
Signed-off-by: Edgar E. Iglesias
---
hw/xen/xen-mapcache.c | 35 ++-
1 file changed, 18 insertions(+), 17
Currently QEMU CPUs always run with a generic timer counter frequency
of 62.5MHz, but ARMv8.6 CPUs will run at 1GHz. For older versions of
the TF-A firmware that sbsa-ref runs, the frequency of the generic
timer is hardcoded into the firmware, and so if the CPU actually has
a different frequency
From: Juergen Gross
Today xen_ram_addr_from_mapcache() will either abort() or return 0 in
case it can't find a matching entry for a pointer value. Both cases
are bad, so change that to return an invalid address instead.
Signed-off-by: Juergen Gross
Signed-off-by: Edgar E. Iglesias
In previous versions of the Arm architecture, the frequency of the
generic timers as reported in CNTFRQ_EL0 could be any IMPDEF value,
and for QEMU we picked 62.5MHz, giving a timer tick period of 16ns.
In Armv8.6, the architecture standardized this frequency to 1GHz.
Because there is no ID
From: "Edgar E. Iglesias"
Make MCACHE_BUCKET_SHIFT runtime configurable per cache instance.
Signed-off-by: Edgar E. Iglesias
---
hw/xen/xen-mapcache.c | 52 ++-
1 file changed, 31 insertions(+), 21 deletions(-)
diff --git a/hw/xen/xen-mapcache.c
From: Juergen Gross
qemu_map_ram_ptr() and qemu_ram_ptr_length() share quite some code, so
modify qemu_ram_ptr_length() a little bit and use it for
qemu_map_ram_ptr(), too.
Signed-off-by: Juergen Gross
Signed-off-by: Vikram Garhwal
Signed-off-by: Edgar E. Iglesias
Reviewed-by: Stefano
The generic timer frequency is settable by board code via a QOM
property "cntfrq", but otherwise defaults to 62.5MHz. The way this
is done includes some complication resulting from how this was
originally a fixed value with no QOM property. Clean it up:
* always set cpu->gt_cntfrq_hz to some
From: "Edgar E. Iglesias"
When invalidating memory ranges, if we happen to hit the first
entry in a bucket we were never unmapping it. This was harmless
for foreign mappings but now that we're looking to reuse the
mapcache for transient grant mappings, we must unmap entries
when invalidated.
From: "Edgar E. Iglesias"
Make the lock functions take MapCache * as argument. This is
in preparation for supporting multiple caches.
No functional changes.
Signed-off-by: Edgar E. Iglesias
---
hw/xen/xen-mapcache.c | 34 +-
1 file changed, 17 insertions(+),
From: "Edgar E. Iglesias"
Break out xen_invalidate_map_cache_single().
No functional changes.
Signed-off-by: Edgar E. Iglesias
---
hw/xen/xen-mapcache.c | 25 +++--
1 file changed, 15 insertions(+), 10 deletions(-)
diff --git a/hw/xen/xen-mapcache.c
From: Inès Varhol
This device implements the IM120417002 colors shield v1.1 for Arduino
(which relies on the DM163 8x3-channel led driving logic) and features
a simple display of an 8x8 RGB matrix. The columns of the matrix are
driven by the DM163 and the rows are driven externally.
Acked-by:
in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20240430
for you to fetch changes up to a0c325c4b05cf7815739d6a84e567b95c8c5be7e:
tests/qtest : Add testcase for DM163 (2024-04-30 16:05:08 +0100
From: Raphael Poggi
clock_propagate() has an assert that clk->source is NULL, i.e. that
you are calling it on a clock which has no source clock. This made
sense in the original design where the only way for a clock's
frequency to change if it had a source clock was when that source
clock
From: "Edgar E. Iglesias"
Hi,
This is a follow-up on Vikrams v3:
http://next.patchew.org/QEMU/20240227223501.28475-1-vikram.garh...@amd.com/
Grant mappings are a mechanism in Xen for guests to grant each other
permissions to map and share pages. These grants can be temporary
so both map and
From: "Edgar E. Iglesias"
Add MapCache argument to xen_remap_bucket in preparation
to support multiple map caches.
No functional changes.
Signed-off-by: Edgar E. Iglesias
---
hw/xen/xen-mapcache.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
hw/arm/xen_arm.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/hw/arm/xen_arm.c b/hw/arm/xen_arm.c
index 15fa7dfa84..6fad829ede 100644
--- a/hw/arm/xen_arm.c
+++ b/hw/arm/xen_arm.c
@@ -125,6 +125,11 @@ static void
From: "Edgar E. Iglesias"
Add MapCache argument to xen_invalidate_map_cache_entry_unlocked.
This is in preparation for supporting multiple map caches.
No functional changes.
Signed-off-by: Edgar E. Iglesias
---
hw/xen/xen-mapcache.c | 21 +++--
1 file changed, 11
From: "Edgar E. Iglesias"
Add a second mapcache for grant mappings. The mapcache for
grants needs to work with XC_PAGE_SIZE granularity since
we can't map larger ranges than what has been granted to us.
Like with foreign mappings (xen_memory), machines using grants
are expected to initialize
As of version DDI0487K.a of the Arm ARM, some architectural features
which previously didn't have official names have been named. Add
these to the list of features which QEMU's TCG emulation supports.
Mostly these are features which we thought of as part of baseline 8.0
support. For SVE and
From: "Edgar E. Iglesias"
Add MapCache argument to xen_replace_cache_entry_unlocked in
preparation for supporting multiple map caches.
No functional change.
Signed-off-by: Edgar E. Iglesias
---
hw/xen/xen-mapcache.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git
From: "Edgar E. Iglesias"
The current mapcache assumes that all memory is mapped
in a single RAM MR (the first one with offset 0). Remove
this assumption and propagate the offset to the mapcache
so it can do reverse mappings (from hostptr -> ram_addr).
This is in preparation for adding grant
On 4/28/24 19:30, Song Gao wrote:
The following changes since commit fd87be1dada5672f877e03c2ca8504458292c479:
Merge tag 'accel-20240426' ofhttps://github.com/philmd/qemu into staging
(2024-04-26 15:28:13 -0700)
are available in the Git repository at:
From: Richard Henderson
For cpus using PMSA, when the MPU is disabled, the default memory
type is Normal, Non-cachable. This means that it should not
have alignment restrictions enforced.
Cc: qemu-sta...@nongnu.org
Fixes: 59754f85ed3 ("target/arm: Do memory type alignment check when
From: Inès Varhol
Signed-off-by: Arnaud Minier
Signed-off-by: Inès Varhol
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20240424200929.240921-5-ines.var...@telecom-paris.fr
Signed-off-by: Peter Maydell
---
hw/arm/b-l475e-iot01a.c | 59 +++--
From: "Edgar E. Iglesias"
Break out xen_map_cache_init_single() in preparation for
adding multiple map caches.
Signed-off-by: Edgar E. Iglesias
---
hw/xen/xen-mapcache.c | 53 ++-
1 file changed, 32 insertions(+), 21 deletions(-)
diff --git
On 4/28/24 19:30, Song Gao wrote:
The following changes since commit fd87be1dada5672f877e03c2ca8504458292c479:
Merge tag 'accel-20240426' ofhttps://github.com/philmd/qemu into staging
(2024-04-26 15:28:13 -0700)
are available in the Git repository at:
From: Alexandra Diupina
The DMA descriptor structures for this device have
a set of "address extension" fields which extend the 32
bit source addresses with an extra 16 bits to give a
48 bit address:
https://docs.amd.com/r/en-US/ug1085-zynq-ultrascale-trm/ADDR_EXT-Field
However, we
From: "Edgar E. Iglesias"
Break out xen_ram_addr_from_mapcache_single(), a multi-cache
aware version of xen_ram_addr_from_mapcache.
No functional changes.
Signed-off-by: Edgar E. Iglesias
---
hw/xen/xen-mapcache.c | 17 +++--
1 file changed, 11 insertions(+), 6 deletions(-)
diff
From: Inès Varhol
`test_dm163_bank()`
Checks that the pin "sout" of the DM163 led driver outputs the values
received on pin "sin" with the expected latency (depending on the bank).
`test_dm163_gpio_connection()`
Check that changes to relevant STM32L4x5 GPIO pins are propagated to the
DM163
From: Thomas Huth
"make check-qtest-aarch64" recently started failing on FreeBSD builds,
and valgrind on Linux also detected that there is something fishy with
the new stm32l4x5-usart: The code forgot to set the correct class_size
here, so the various class_init functions in this file wrote
Newer versions of the Arm ARM (e.g. rev K.a) now define fields for
ID_AA64MMFR3_EL1. Implement this register, so that we can set the
fields if we need to. There's no behaviour change here since we
don't currently set the register value to non-zero.
Signed-off-by: Peter Maydell
Reviewed-by:
From: Inès Varhol
Exposing SYSCFG inputs to the SoC is practical in order to wire the SoC
to the optional DM163 display from the board code (GPIOs outputs need
to be connected to both SYSCFG inputs and DM163 inputs).
STM32L4x5 SYSCFG in-irq interception needed to be changed accordingly.
Currently the sbsa_gdwt watchdog device hardcodes its frequency at
62.5MHz. In real hardware, this watchdog is supposed to be driven
from the system counter, which also drives the CPU generic timers.
Newer CPU types (in particular from Armv8.6) should have a CPU
generic timer frequency of 1GHz, so
FEAT_Spec_FPACC is a feature describing speculative behaviour in the
event of a PAC authontication failure when FEAT_FPACCOMBINE is
implemented. FEAT_Spec_FPACC means that the speculative use of
pointers processed by a PAC Authentication is not materially
different in terms of the impact on
From: Inès Varhol
Signed-off-by: Arnaud Minier
Signed-off-by: Inès Varhol
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20240424200929.240921-4-ines.var...@telecom-paris.fr
Signed-off-by: Peter Maydell
---
hw/arm/b-l475e-iot01a.c | 46 -
1 file
FEAT_ETS2 is a tighter set of guarantees about memory ordering
involving translation table walks than the old FEAT_ETS; FEAT_ETS has
been retired from the Arm ARM and the old ID_AA64MMFR1.ETS == 1
now gives no greater guarantees than ETS == 0.
FEAT_ETS2 requires:
* the virtual address of a load
The Linux kernel 5.10.16 binary for sunxi has been removed from
apt.armbian.com. This means that the avocado tests for these machines
will be skipped (status CANCEL) if the old binary isn't present in
the avocado cache.
Update to 6.6.16, in the same way we did in commit e384db41d8661
when we
From: Philippe Mathieu-Daudé
Use little endian for derivative OTP fuse key.
Cc: qemu-sta...@nongnu.org
Fixes: c752bb079b ("hw/nvram: NPCM7xx OTP device model")
Suggested-by: Avi Fishman
Signed-off-by: Philippe Mathieu-Daudé
Message-id: 20240422125813.1403-1-phi...@linaro.org
Reviewed-by:
FEAT_CSV2_3 adds a mechanism to identify if hardware cannot disclose
information about whether branch targets and branch history trained
in one hardware described context can control speculative execution
in a different hardware context.
There is no branch prediction in TCG, so we don't need to
From: Zenghui Yu
As it had never been used since the first commit a1477da3ddeb ("hvf: Add
Apple Silicon support").
Signed-off-by: Zenghui Yu
Message-id: 20240422092715.71973-1-zenghui...@linux.dev
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
target/arm/hvf/hvf.c | 1 -
1 file
The fp-bench test (i. e. tests/fp/fp-bench.c) use fenv.h that is not
always provided by the libc (uClibc). The patch disables its compilation
in case the header is not available.
The patch is based on a suggestion from Paolo Bonzini, which you can
find at the following link.
Link:
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