> From: CLEMENT MATHIEU--DRIF
> Sent: Friday, May 17, 2024 9:13 PM
>
> Hi Zhenzhong
>
> On 17/05/2024 12:23, Zhenzhong Duan wrote:
> > Caution: External email. Do not open attachments or click links, unless
> > this email
> comes from a known sender and you know the content is safe.
> >
> >
>
Replace stubbed OTP memory region with the new OTP device.
Signed-off-by: Rayhan Faizel
---
hw/arm/bcm2835_peripherals.c | 13 -
include/hw/arm/bcm2835_peripherals.h | 3 ++-
2 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/hw/arm/bcm2835_peripherals.c
The OTP device registers are currently stubbed. For now, the device
houses the OTP rows which will be accessed directly by other peripherals.
Signed-off-by: Rayhan Faizel
---
hw/nvram/bcm2835_otp.c | 187 +
hw/nvram/meson.build | 1 +
Four mailbox properties are implemented as follows:
1. Customer OTP: GET_CUSTOMER_OTP and SET_CUSTOMER_OTP
2. Device-specific private key: GET_PRIVATE_KEY and
SET_PRIVATE_KEY.
The customer OTP is located in the rows 36-43. The device-specific private key
is located in the rows 56-63.
The
All BCM2835 boards have on-board OTP memory with 66 32-bit rows. Usually,
its contents are accessible via mailbox commands.
[Changes in v2]
- Replace read/write with get/set in bcm2835_otp.c.
- Use impl instead of valid in bcm2835_otp.c.
- Replace all constant values with macros defined in
Hi,
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 4fdb66052587..16c2bdbfe6b6 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -53,6 +53,8 @@
#include "hw/pci-host/gpex.h"
#include "hw/display/ramfb.h"
#include "hw/acpi/aml-build.h"
+#include "hw/mem/memory-device.h"
On Fri, 17 May 2024, Nicholas Piggin wrote:
On Mon May 13, 2024 at 9:28 AM AEST, BALATON Zoltan wrote:
This is used only once and can be inlined.
This reminds me, ppc_hash32_pp_prot() calculates prot from
pp and nx (which is not from pp but from segment) and from
key of course. It could be
Hi Björj,
On 5/14/24 08:06, Björn Töpel wrote:
From: Björn Töpel
Virtio-based memory devices allows for dynamic resizing of virtual
machine memory, and requires proper hotplugging (add/remove) support
to work.
Enable virtio-md-pci with the corresponding missing hotplugging
callbacks for the
^ typo in the commit subject: 'disas/riscv: ...'
On 5/14/24 02:16, Alistair Francis wrote:
Previously we only listed a single pmpcfg CSR and the first 16 pmpaddr
CSRs. This patch fixes this to list all 16 pmpcfg and all 64 pmpaddr
CSRs are part of the dissassembly.
I think the correct here is
On 5/17/24 17:02, Philippe Mathieu-Daudé wrote:
WARNING & ERROR from checkpatch.pl in tests/unit/test-smp-parse.c
deliberately ignored.
The following changes since commit 85ef20f1673feaa083f4acab8cf054df77b0dbed:
Merge tag 'pull-maintainer-may24-160524-2' ofhttps://gitlab.com/stsquad/qemu
On 5/17/24 14:25, Thomas Huth wrote:
The following changes since commit 85ef20f1673feaa083f4acab8cf054df77b0dbed:
Merge tag 'pull-maintainer-may24-160524-2' ofhttps://gitlab.com/stsquad/qemu
into staging (2024-05-16 10:02:56 +0200)
are available in the Git repository at:
On 5/13/24 08:46, Rajnesh Kanwal wrote:
Qemu maps IRQs 0:15 for core interrupts and 16 onward for
guest interrupts which are later translated to hgiep in
`riscv_cpu_set_irq()` function.
With virtual IRQ support added, software now can fully
use the whole local interrupt range without any
On 5/13/24 08:46, Rajnesh Kanwal wrote:
AIA extends the width of all IRQ CSRs to 64bit even
in 32bit systems by adding missing half CSRs.
This seems to be missed while adding support for
virtual IRQs. The whole logic seems to be correct
except the width of the masks.
Fixes: 1697837ed9
On 5/18/24 11:31, Nicholas Piggin wrote:
+void spr_core_write_generic32(DisasContext *ctx, int sprn, int gprn)
+{
+TCGv t0 = tcg_temp_new();
+if (!(ctx->flags & POWERPC_FLAG_SMT)) {
+spr_write_generic32(ctx, sprn, gprn);
+return;
+}
+
+if (!gen_serialize(ctx)) {
+
On 5/18/24 11:31, Nicholas Piggin wrote:
+static void gen_attn(DisasContext *ctx)
+{
+#if defined(CONFIG_USER_ONLY)
+GEN_PRIV(ctx);
+#else
+gen_helper_attn(tcg_env);
+#endif
+}
You forgot to check priv in system mode.
Better as
GEN_PRIV(ctx);
#ifndef CONFIG_USER_ONLY
On 5/18/24 11:31, Nicholas Piggin wrote:
@@ -425,17 +426,17 @@ static void powerpc_set_excp_state(PowerPCCPU *cpu,
target_ulong vector,
env->reserve_addr = -1;
}
-static void powerpc_mcheck_checkstop(CPUPPCState *env)
-{
-/* KVM guests always have MSR[ME] enabled */
#ifdef
On 5/18/24 11:31, Nicholas Piggin wrote:
There is a memop_size() function for this.
Signed-off-by: Nicholas Piggin
---
target/ppc/translate.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
Reviewed-by: Richard Henderson
r~
On 5/18/24 11:31, Nicholas Piggin wrote:
Use DEF_MEMOP() consistently in larx and stcx. generation, and apply it
once when it's used rather than where the macros are expanded, to reduce
typing.
Signed-off-by: Nicholas Piggin
---
target/ppc/translate.c | 18 +-
1 file changed,
On 5/17/24 14:48, Nicholas Piggin wrote:
On Tue Apr 23, 2024 at 4:32 PM AEST, Chinmay Rath wrote:
Moving the below instructions to decodetree specification :
divd[u, e, eu][o][.]: XO-form
mod{sd, ud} : X-form
With this patch, all the fixed-point arithmetic
On Sat, 18 May 2024, Nicholas Piggin wrote:
There is a memop_size() function for this.
Signed-off-by: Nicholas Piggin
Reviewed-by: BALATON Zoltan
---
target/ppc/translate.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/target/ppc/translate.c
The ibm,pi-features property has a bit to say whether or not
msgsndp should be used. Linux checks if it is being run under
KVM and avoids msgsndp anyway, but it would be preferable to
rely on this bit.
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr.c | 27 +++
1 file
On Sat, 18 May 2024, Nicholas Piggin wrote:
On Mon May 13, 2024 at 9:27 AM AEST, BALATON Zoltan wrote:
This series does some further clean up mostly around BookE MMU to
untangle it from other MMU models. It also contains some other changes
that I've come up with while working on this. The
There is a memop_size() function for this.
Signed-off-by: Nicholas Piggin
---
target/ppc/translate.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 0882fe2fd2..cf2404330b 100644
--- a/target/ppc/translate.c
+++
PTCR is a per-core register.
Signed-off-by: Nicholas Piggin
---
target/ppc/misc_helper.c | 16 ++--
target/ppc/translate.c | 4
2 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c
index 6f419c9346..a67930d031
LDBAR, TTR are a Power-specific SPRs. These simple implementations
are enough for IBM proprietary firmware for now.
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu.h | 2 ++
target/ppc/cpu_init.c | 10 ++
2 files changed, 12 insertions(+)
diff --git a/target/ppc/cpu.h
An SPR can be either per-thread, per-core, or per-LPAR. Per-LPAR means
per-thread or per-core, depending on 1LPAR mode.
Signed-off-by: Nicholas Piggin
---
target/ppc/spr_common.h | 2 ++
target/ppc/translate.c | 26 ++
2 files changed, 28 insertions(+)
diff --git
attn is an implementation-specific instruction that on POWER (and G5/
970) can be enabled with a HID bit (disabled = illegal), and executing
it causes the host processor to stop and the service processor to be
notified. Generally used for debugging.
Implement attn and make it checkstop the
This implements the POWER SPRC/SPRD SPRs, and SCRATCH0-7 registers that
can be accessed via these indirect SPRs.
SCRATCH registers only provide storage, but they are used by firmware
for low level crash and progress data, so this implementation logs
writes to the registers to help with analysis.
Change the logging not to print to stderr as well, because a
checkstop is a guest error (or perhaps a simulated machine error)
rather than a QEMU error, so send it to the log.
Update the checkstop message, and log CPU registers too.
Signed-off-by: Nicholas Piggin
---
target/ppc/excp_helper.c |
AMOR, MMCRC, HRMOR, TSCR, HMEER, RPR SPRs are per-core or per-LPAR
registers with simple (generic) implementations.
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu_init.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/ppc/cpu_init.c
msgsnd has a broadcast mode that sends hypervisor doorbells to all
threads belonging to the same core as the target. A "subcore" mode
sends to all or one thread depending on 1LPAR mode.
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu.h | 6 +-
target/ppc/helper.h
>From the Freescale PowerPC Architecture Primer:
Alternate time base APU. This APU, implemented on the e500v2, defines
a 64-bit time base counter that differs from the PowerPC defined time
base in that it is not writable and counts at a different, and
typically much higher, frequency. The
The DECAR SPR is 32-bits width.
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu_init.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 71da8d4856..462246cb7d 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
Use DEF_MEMOP() consistently in larx and stcx. generation, and apply it
once when it's used rather than where the macros are expanded, to reduce
typing.
Signed-off-by: Nicholas Piggin
---
target/ppc/translate.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git
PPR32 provides access to the upper half of PPR.
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu.h| 1 +
target/ppc/spr_common.h | 2 ++
target/ppc/cpu_init.c | 12
target/ppc/translate.c | 16
4 files changed, 31 insertions(+)
diff --git
This is a bunch of instruction and register additions, improved SMT
support, etc. for TCG.
Thanks,
Nick
Nicholas Piggin (14):
target/ppc: larx/stcx generation need only apply DEF_MEMOP() once
target/ppc: Remove redundant MEMOP_GET_SIZE macro
target/ppc: Make checkstop actually stop the
checkstop state does not halt the system, interrupts continue to be
serviced, and other CPUs run. Make it stop the machine with
qemu_system_guest_panicked.
Signed-off-by: Nicholas Piggin
---
target/ppc/excp_helper.c | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
diff
On Mon May 13, 2024 at 9:27 AM AEST, BALATON Zoltan wrote:
> This series does some further clean up mostly around BookE MMU to
> untangle it from other MMU models. It also contains some other changes
> that I've come up with while working on this. The Simplify
> ppc_booke_xlate() part 1 and part 2
On Mon Apr 29, 2024 at 3:13 PM AEST, Chinmay Rath wrote:
> Moving VMX instructions of the following types to decodetree
> specification : storage access, integer logical & integer max/min.
FYI I've added these to
https://gitlab.com/npiggin/qemu/-/commits/ppc-next-test
With the 32-bit fixes.
Hi,
I just noticed the reference URL for number [4] in my cover-letter is incorrect.
On Sat, May 18, 2024 at 2:08 PM Dorjoy Chowdhury wrote:
>
> Hi,
>
> Hope everyone is doing well. I am working on adding AWS Nitro Enclave[1]
> emulation support in QEMU. Alexander Graf is mentoring me on this
On Fri, May 17, 2024 at 07:43:35PM -0300, Fabiano Rosas wrote:
> Daniel P. Berrangé writes:
>
> >
> > The only caller of monitor_fdset_dup_fd_add is qemu_open_internal
> > and that has a "Error **errp" parameter. We should rewrite
> > monitor_fdset_dup_fd_add to also have an "Error **errp" at
An EIF (Enclave Image Format)[1] image is used to boot an AWS nitro
enclave[2] virtual machine. The EIF file contains the necessary
kernel, cmdline, ramdisk(s) sections to boot.
This commit adds support for loading EIF image using the microvm
machine code. For microvm to boot from an EIF file,
AWS nitro enclaves[1] is an Amazon EC2[2] feature that allows creating
isolated execution environments, called enclaves, from Amazon EC2
instances which are used for processing highly sensitive data.
Enclaves have no persistent storage and no external networking. The
enclave VMs are based on
Hi,
Hope everyone is doing well. I am working on adding AWS Nitro Enclave[1]
emulation support in QEMU. Alexander Graf is mentoring me on this work. This is
a patch series adding, not yet complete, but useful emulation support of nitro
enclaves. I have a gitlab branch where you can view the
On Sun, Apr 14, 2024 at 2:21 AM Gautam Bhat wrote:
>
> Ah I had my .tlb_fill callback set to an empty function with just
> returning true. I need to put the actual code there. Let me fill this
> function up and see what happens.
>
> -Gautam.
Got it working. I can see the opcode now. Let me
On 2024/05/18 5:30, Daniel Henrique Barboza wrote:
Commit 33a24910ae changed 'reg_width' to use 'vlenb', i.e. vector length
in bytes, when in this context we want 'reg_width' as the length in
bits.
Fix 'reg_width' back to the value in bits like 7cb59921c05a
("target/riscv/gdbstub.c: use 'vlenb'
Add properties for user specified
- PCI vendor, device, subsystem vendor and subsystem IDs
- IEEE-OUI ID
e.g. PCI IDs to be specified as follows:
-device
nvme,id_vendor=0xABCD,id_device=0xA0B0,id_subsys_vendor=0xEF00,id_subsys=0xEF01
IEEE-OUI ID (Identify Controller bytes 75:73) is to be
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