[PATCH 3/3] tests/qtest/migration-test: Use custom asm bios for ppc64

Similar to other archs, build a custom bios memory updater. Running the test with OF code is a cool trick, but SLOF takes a long time to boot. This reduces test time by around 3x (150s to 50s). Signed-off-by: Nicholas Piggin --- tests/migration/migration-test.h | 1 +

[PATCH 2/3] tests/qtest/migration-test: Enable on ppc64

ppc64 with TCG seems to no longer be failing this test. Let's try to enable it. s390x is still hanging about 1 in 10 runs. Signed-off-by: Nicholas Piggin --- tests/qtest/migration-test.c | 16 +++- 1 file changed, 3 insertions(+), 13 deletions(-) diff --git

[PATCH 1/3] tests/qtest/migration-test: Quieten ppc64 QEMU warnigns

Signed-off-by: Nicholas Piggin --- tests/qtest/migration-test.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/tests/qtest/migration-test.c b/tests/qtest/migration-test.c index b7e3406471..c13535c37d 100644 --- a/tests/qtest/migration-test.c +++

[PATCH 0/3] tests/qtest/migration-test: Improve and enable on ppc64

ppc64 seems to be stable now, only problem is the speed, so I rewrote the test to avoid SLOF and use special bios blob like the other archs. Thanks, Nick Nicholas Piggin (3): tests/qtest/migration-test: Quieten ppc64 QEMU warnigns tests/qtest/migration-test: Enable on ppc64

[PATCH v2 19/67] target/arm: Convert FADD, FSUB, FDIV, FMUL to decodetree

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/helper-a64.h| 4 + target/arm/tcg/translate.h | 5 + target/arm/tcg/a64.decode | 27 + target/arm/tcg/translate-a64.c | 205 + target/arm/tcg/vec_helper.c|

[PATCH v2 50/67] target/arm: Convert ADD, SUB (vector) to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 6 ++ target/arm/tcg/translate-a64.c | 34 +++--- 2 files changed, 17 insertions(+), 23 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index

[PATCH v2 27/67] target/arm: Convert FRECPS, FRSQRTS to decodetree

These are the last instructions within handle_3same_float and disas_simd_scalar_three_reg_same_fp16 so remove them. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 12 ++ target/arm/tcg/translate-a64.c | 293 - 2

[PATCH v2 35/67] target/arm: Convert FMLAL, FMLSL to decodetree

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 10 +++ target/arm/tcg/translate-a64.c | 144 ++--- 2 files changed, 51 insertions(+), 103 deletions(-) diff --git a/target/arm/tcg/a64.decode

[PATCH v2 53/67] target/arm: Use TCG_COND_TSTNE in gen_cmtst_vec

Signed-off-by: Richard Henderson --- target/arm/tcg/gengvec.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/target/arm/tcg/gengvec.c b/target/arm/tcg/gengvec.c index 1d6bc6021d..1895c3b19f 100644 --- a/target/arm/tcg/gengvec.c +++ b/target/arm/tcg/gengvec.c @@ -943,9

[PATCH v2 66/67] target/arm: Convert FMADD, FMSUB, FNMADD, FNMSUB to decodetree

These are the only instructions in the 3 source scalar class. Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 10 ++ target/arm/tcg/translate-a64.c | 233 - 2 files changed, 93 insertions(+), 150 deletions(-) diff --git

[PATCH v2 54/67] target/arm: Convert SHADD, UHADD to gvec

Signed-off-by: Richard Henderson --- target/arm/helper.h | 6 -- target/arm/tcg/translate.h | 5 ++ target/arm/tcg/gengvec.c| 144 target/arm/tcg/neon_helper.c| 27 -- target/arm/tcg/translate-a64.c | 17 ++--

[PATCH v2 46/67] target/arm: Convert SQSHL and UQSHL (register) to gvec

Signed-off-by: Richard Henderson --- target/arm/helper.h | 8 target/arm/tcg/translate.h | 4 target/arm/tcg/neon-dp.decode | 10 ++--- target/arm/tcg/gengvec.c| 24 ++ target/arm/tcg/neon_helper.c| 36

[PATCH v2 49/67] target/arm: Convert SQRSHL, UQRSHL to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 4 +++ target/arm/tcg/translate-a64.c | 48 -- 2 files changed, 26 insertions(+), 26 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index

[PATCH v2 55/67] target/arm: Convert SHADD, UHADD to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 2 ++ target/arm/tcg/translate-a64.c | 11 +++ 2 files changed, 5 insertions(+), 8 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 3061e26242..e33d91fd0a 100644 ---

[PATCH v2 62/67] target/arm: Convert MUL, PMUL to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 5 target/arm/tcg/translate-a64.c | 51 +- 2 files changed, 25 insertions(+), 31 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index

[PATCH v2 52/67] target/arm: Use TCG_COND_TSTNE in gen_cmtst_{i32, i64}

Signed-off-by: Richard Henderson --- target/arm/tcg/gengvec.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/target/arm/tcg/gengvec.c b/target/arm/tcg/gengvec.c index 51e66ccf5f..1d6bc6021d 100644 --- a/target/arm/tcg/gengvec.c +++ b/target/arm/tcg/gengvec.c @@ -933,14

[PATCH v2 47/67] target/arm: Convert SQSHL, UQSHL to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 4 ++ target/arm/tcg/translate-a64.c | 74 ++ 2 files changed, 53 insertions(+), 25 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 9e02776036..85caf37948

[PATCH v2 63/67] target/arm: Convert MLA, MLS to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 8 target/arm/tcg/translate-a64.c | 77 ++ 2 files changed, 31 insertions(+), 54 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index

[PATCH v2 05/67] target/arm: Fix decode of FMOV (hp) vs MOVI

The decode of FMOV (vector, immediate, half-precision) vs invalid cases of MOVI are incorrect. Fixes RISU mismatch for invalid insn 0x2f01fd31. Fixes: 70b4e6a4457 ("arm/translate-a64: add FP16 FMOV to simd_mod_imm") Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 24

[PATCH v2 38/67] target/arm: Convert SUQADD and USQADD to gvec

Signed-off-by: Richard Henderson --- target/arm/helper.h| 16 + target/arm/tcg/translate-a64.h | 6 ++ target/arm/tcg/gengvec64.c | 106 +++ target/arm/tcg/translate-a64.c | 113 ++--- target/arm/tcg/vec_helper.c|

[PATCH v2 34/67] target/arm: Use gvec for neon pmax, pmin

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-neon.c | 78 ++--- 1 file changed, 4 insertions(+), 74 deletions(-) diff --git a/target/arm/tcg/translate-neon.c b/target/arm/tcg/translate-neon.c index 6c5a7a98e1..18b048611b

[PATCH v2 42/67] target/arm: Convert SUQADD, USQADD to decodetree

These are faux 2-operand instructions, reading from rd. Sort them next to the other three-operand same insns for clarity. Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 8 + target/arm/tcg/translate-a64.c | 64 -- 2 files changed, 14

[PATCH v2 21/67] target/arm: Introduce vfp_load_reg16

Load and zero-extend float16 into a TCGv_i32 before all scalar operations. Signed-off-by: Richard Henderson --- target/arm/tcg/translate-vfp.c | 39 +++--- 1 file changed, 22 insertions(+), 17 deletions(-) diff --git a/target/arm/tcg/translate-vfp.c

[PATCH v2 51/67] target/arm: Convert CMGT, CMHI, CMGE, CMHS, CMTST, CMEQ to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 12 +++ target/arm/tcg/translate-a64.c | 132 - 2 files changed, 60 insertions(+), 84 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index

[PATCH v2 41/67] target/arm: Convert SQADD, SQSUB, UQADD, UQSUB to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 11 target/arm/tcg/translate-a64.c | 100 +++-- 2 files changed, 68 insertions(+), 43 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index

[PATCH v2 31/67] target/arm: Convert ADDP to decodetree

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.h| 5 ++ target/arm/tcg/translate.h | 3 + target/arm/tcg/a64.decode | 6 ++ target/arm/tcg/gengvec.c | 12 target/arm/tcg/translate-a64.c | 128

[PATCH v2 64/67] target/arm: Tidy SQDMULH, SQRDMULH (vector)

We already have a gvec helper for the operations, but we aren't using it on the aa32 neon side. Create a unified expander for use by both aa32 and aa64 translators. Signed-off-by: Richard Henderson --- target/arm/tcg/translate.h | 4 target/arm/tcg/gengvec.c| 20

[PATCH v2 48/67] target/arm: Convert SQRSHL and UQRSHL (register) to gvec

Signed-off-by: Richard Henderson --- target/arm/helper.h | 8 ++ target/arm/tcg/translate.h | 4 +++ target/arm/tcg/neon-dp.decode | 17 ++-- target/arm/tcg/gengvec.c| 24 target/arm/tcg/neon_helper.c| 24

[PATCH v2 37/67] target/arm: Improve vector UQADD, UQSUB, SQADD, SQSUB

No need for a full comparison; xor produces non-zero bits for QC just fine. Signed-off-by: Richard Henderson --- target/arm/tcg/gengvec.c | 32 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/target/arm/tcg/gengvec.c b/target/arm/tcg/gengvec.c

[PATCH v2 57/67] target/arm: Convert SHSUB, UHSUB to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 2 ++ target/arm/tcg/translate-a64.c | 11 +++ 2 files changed, 5 insertions(+), 8 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index e33d91fd0a..b1bbcb144e 100644 ---

[PATCH v2 45/67] target/arm: Convert SRSHL, URSHL to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 4 target/arm/tcg/translate-a64.c | 22 +++--- 2 files changed, 11 insertions(+), 15 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index ea897d6732..9e02776036 100644

[PATCH v2 08/67] target/arm: Split out gengvec64.c

Split some routines out of translate-a64.c and translate-sve.c that are used by both. Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.h | 4 + target/arm/tcg/gengvec64.c | 190

[PATCH v2 32/67] target/arm: Use gvec for neon padd

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.h | 2 -- target/arm/tcg/neon_helper.c| 5 - target/arm/tcg/translate-neon.c | 3 +-- 3 files changed, 1 insertion(+), 9 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h

[PATCH v2 40/67] target/arm: Inline scalar SQADD, UQADD, SQSUB, UQSUB

This eliminates the last uses of these neon helpers. Incorporate the MO_64 expanders as an option to the vector expander. Signed-off-by: Richard Henderson --- target/arm/helper.h| 17 target/arm/tcg/translate.h | 15 +++ target/arm/tcg/gengvec.c | 116

[PATCH v2 30/67] target/arm: Use gvec for neon faddp, fmaxp, fminp

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.h | 7 - target/arm/tcg/translate-neon.c | 55 ++--- target/arm/tcg/vec_helper.c | 45 --- 3 files changed, 3 insertions(+), 104

[PATCH v2 28/67] target/arm: Convert FADDP to decodetree

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.h| 4 ++ target/arm/tcg/a64.decode | 12 + target/arm/tcg/translate-a64.c | 87 ++ target/arm/tcg/vec_helper.c| 23 + 4 files changed, 105

[PATCH v2 29/67] target/arm: Convert FMAXP, FMINP, FMAXNMP, FMINNMP to decodetree

These are the last instructions within disas_simd_three_reg_same_fp16, so remove it. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.h| 16 ++ target/arm/tcg/a64.decode | 24 +++ target/arm/tcg/translate-a64.c | 296

[PATCH v2 58/67] target/arm: Convert SRHADD, URHADD to gvec

Signed-off-by: Richard Henderson --- target/arm/helper.h | 7 -- target/arm/tcg/translate.h | 4 + target/arm/tcg/gengvec.c| 144 target/arm/tcg/neon_helper.c| 27 -- target/arm/tcg/translate-a64.c | 48 ++-

[PATCH v2 09/67] target/arm: Convert Cryptographic AES to decodetree

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 21 +++-- target/arm/tcg/translate-a64.c | 86 +++--- 2 files changed, 54 insertions(+), 53 deletions(-) diff --git a/target/arm/tcg/a64.decode

[PATCH v2 36/67] target/arm: Convert disas_simd_3same_logic to decodetree

This includes AND, ORR, EOR, BIC, ORN, BSF, BIT, BIF. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 10 + target/arm/tcg/translate-a64.c | 68 ++ 2 files changed, 29 insertions(+), 49 deletions(-) diff

[PATCH v2 56/67] target/arm: Convert SHSUB, UHSUB to gvec

Signed-off-by: Richard Henderson --- target/arm/helper.h | 6 -- target/arm/tcg/translate.h | 4 + target/arm/tcg/gengvec.c| 144 target/arm/tcg/neon_helper.c| 27 -- target/arm/tcg/translate-a64.c | 17 ++--

[PATCH v2 04/67] target/arm: Zero-extend writeback for fp16 FCVTZS (scalar, integer)

Fixes RISU mismatch for "fcvtzs h31, h0, #14". Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 4126aaa27e..d97acdbaf9 100644 ---

[PATCH v2 60/67] target/arm: Convert SMAX, SMIN, UMAX, UMIN to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 4 target/arm/tcg/translate-a64.c | 22 ++ 2 files changed, 10 insertions(+), 16 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 1c448b4f7c..bc98963bc5 100644

[PATCH v2 12/67] target/arm: Convert Cryptographic 3-register SHA512 to decodetree

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 11 target/arm/tcg/translate-a64.c | 97 -- 2 files changed, 32 insertions(+), 76 deletions(-) diff --git a/target/arm/tcg/a64.decode

[PATCH v2 67/67] target/arm: Convert FCSEL to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 4 ++ target/arm/tcg/translate-a64.c | 108 ++--- 2 files changed, 49 insertions(+), 63 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index

[PATCH v2 20/67] target/arm: Convert FMAX, FMIN, FMAXNM, FMINNM to decodetree

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.h| 4 + target/arm/tcg/a64.decode | 17 target/arm/tcg/translate-a64.c | 168 + target/arm/tcg/vec_helper.c| 4 + 4 files changed, 113 insertions(+),

[PATCH v2 61/67] target/arm: Convert SABA, SABD, UABA, UABD to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 4 target/arm/tcg/translate-a64.c | 22 ++ 2 files changed, 10 insertions(+), 16 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index bc98963bc5..07b604ec30 100644

[PATCH v2 16/67] target/arm: Convert XAR to decodetree

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 4 target/arm/tcg/translate-a64.c | 43 +++--- 2 files changed, 18 insertions(+), 29 deletions(-) diff --git a/target/arm/tcg/a64.decode

[PATCH v2 65/67] target/arm: Convert SQDMULH, SQRDMULH to decodetree

These are the last instructions within disas_simd_three_reg_same and disas_simd_scalar_three_reg_same, so remove them. Signed-off-by: Richard Henderson --- target/arm/helper.h| 10 ++ target/arm/tcg/a64.decode | 18 +++ target/arm/tcg/translate-a64.c | 276

[PATCH v2 59/67] target/arm: Convert SRHADD, URHADD to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 2 ++ target/arm/tcg/translate-a64.c | 11 +++ 2 files changed, 5 insertions(+), 8 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index b1bbcb144e..1c448b4f7c 100644 ---

[PATCH v2 43/67] target/arm: Convert SSHL, USHL to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 7 ++ target/arm/tcg/translate-a64.c | 40 +- 2 files changed, 32 insertions(+), 15 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index

[PATCH v2 44/67] target/arm: Convert SRSHL and URSHL (register) to gvec

Signed-off-by: Richard Henderson --- target/arm/helper.h | 10 + target/arm/tcg/translate.h | 4 target/arm/tcg/neon-dp.decode | 10 ++--- target/arm/tcg/gengvec.c| 22 +++ target/arm/tcg/neon_helper.c| 38

[PATCH v2 17/67] target/arm: Convert Advanced SIMD copy to decodetree

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 13 + target/arm/tcg/translate-a64.c | 426 +++-- 2 files changed, 152 insertions(+), 287 deletions(-) diff --git a/target/arm/tcg/a64.decode

[PATCH v2 15/67] target/arm: Convert Cryptographic 3-register, imm2 to decodetree

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 10 target/arm/tcg/translate-a64.c | 43 ++ 2 files changed, 22 insertions(+), 31 deletions(-) diff --git a/target/arm/tcg/a64.decode

[PATCH v2 22/67] target/arm: Expand vfp neg and abs inline

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.h| 6 target/arm/tcg/translate.h | 30 +++ target/arm/tcg/translate-a64.c | 44 +-- target/arm/tcg/translate-vfp.c | 54

[PATCH v2 07/67] target/arm: Split out gengvec.c

Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/tcg/translate.h |5 + target/arm/tcg/gengvec.c | 1612 target/arm/tcg/translate.c | 1588 ---

[PATCH v2 11/67] target/arm: Convert Cryptographic 2-register SHA to decodetree

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 6 target/arm/tcg/translate-a64.c | 54 +++--- 2 files changed, 10 insertions(+), 50 deletions(-) diff --git a/target/arm/tcg/a64.decode

[PATCH v2 10/67] target/arm: Convert Cryptographic 3-register SHA to decodetree

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 11 + target/arm/tcg/translate-a64.c | 78 +- 2 files changed, 21 insertions(+), 68 deletions(-) diff --git a/target/arm/tcg/a64.decode

[PATCH v2 06/67] target/arm: Verify sz=0 for Advanced SIMD scalar pairwise (fp16)

All of these insns have "if sz == '1' then UNDEFINED" in their pseudocode. Fixes a RISU miscompare for invalid insn 0x5ef0c87a. Fixes: 5c36d89567c ("arm/translate-a64: add all FP16 ops in simd_scalar_pairwise") Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 2 +- 1 file

[PATCH v2 23/67] target/arm: Convert FNMUL to decodetree

This is the last instruction within disas_fp_2src, so remove that and its subroutines. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 1 + target/arm/tcg/translate-a64.c | 177 + 2 files changed, 27

[PATCH v2 01/67] target/arm: Add neoverse-n1 to qemu-arm (DO NOT MERGE)

Hack, because there should be a better way to do this without duplicating code between cpu32.c and cpu64.c. Hack, because qemu-arm crashes without ARM_FEATURE_AARCH64 disabled. Needed in order to compare RISU results with aarch64.ci.qemu.org. Signed-off-by: Richard Henderson ---

[PATCH v2 39/67] target/arm: Inline scalar SUQADD and USQADD

This eliminates the last uses of these neon helpers. Incorporate the MO_64 expanders as an option to the vector expander. Signed-off-by: Richard Henderson --- target/arm/helper.h| 8 -- target/arm/tcg/translate-a64.h | 8 ++ target/arm/tcg/gengvec64.c | 71 ++

[PATCH v2 25/67] target/arm: Convert FCMEQ, FCMGE, FCMGT, FACGE, FACGT to decodetree

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.h| 5 + target/arm/tcg/a64.decode | 30 ++ target/arm/tcg/translate-a64.c | 188 +++-- target/arm/tcg/vec_helper.c| 30 ++ 4 files changed, 174

[PATCH v2 18/67] target/arm: Convert FMULX to decodetree

Convert all forms (scalar, vector, scalar indexed, vector indexed), which allows us to remove switch table entries elsewhere. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/helper-a64.h| 8 ++ target/arm/tcg/a64.decode | 45 +++

[PATCH v2 13/67] target/arm: Convert Cryptographic 2-register SHA512 to decodetree

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 5 target/arm/tcg/translate-a64.c | 50 ++ 2 files changed, 8 insertions(+), 47 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode

[PATCH v2 14/67] target/arm: Convert Cryptographic 4-register to decodetree

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 8 ++ target/arm/tcg/translate-a64.c | 132 +++-- 2 files changed, 51 insertions(+), 89 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode

[PATCH v2 24/67] target/arm: Convert FMLA, FMLS to decodetree

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.h| 2 + target/arm/tcg/a64.decode | 22 +++ target/arm/tcg/translate-a64.c | 241 + target/arm/tcg/vec_helper.c| 14 ++ 4 files changed, 163 insertions(+),

[PATCH v2 02/67] target/arm: Use PLD, PLDW, PLI not NOP for t32

This fixes a bug in that neither PLI nor PLDW are present in ARMv6T2, but are introduced with ARMv7 and ARMv7MP respectively. For clarity, do not use NOP for PLD. Note that there is no PLDW (literal) -- bit 5 of the first word is not decoded, and is PLD (literal). Confirmed on neoverse-n1 host

[PATCH v2 26/67] target/arm: Convert FABD to decodetree

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.h| 1 + target/arm/tcg/a64.decode | 6 target/arm/tcg/translate-a64.c | 60 ++ target/arm/tcg/vec_helper.c| 6 4 files changed, 53 insertions(+),

[PATCH v2 03/67] target/arm: Reject incorrect operands to PLD, PLDW, PLI

For all, rm == 15 is invalid. Prior to v8, thumb with rm == 13 is invalid. For PLDW, rn == 15 is invalid. Fixes a RISU mismatch for the HINTSPACE pattern in t32.risu compared to a neoverse-n1 host. Signed-off-by: Richard Henderson --- target/arm/tcg/a32-uncond.decode | 8 +++--

[PATCH v2 33/67] target/arm: Convert SMAXP, SMINP, UMAXP, UMINP to decodetree

These are the last instructions within handle_simd_3same_pair so remove it. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.h| 16 + target/arm/tcg/translate.h | 8 +++ target/arm/tcg/a64.decode | 4 ++ target/arm/tcg/gengvec.c

[PATCH v2 00/67] target/arm: Convert a64 advsimd to decodetree (part 1)

In the process, convert more code to gvec as well -- I will need the gvec code for implementing SME2. I guess this is about 1/3 of the job done, but there's no reason to wait until the patch set is completely unwieldy. Changes for v2: * Fix existing RISU failures vs neoverse-n1. * Introduce

[PATCH V2 0/3] improve -overcommit cpu-pm=on|off

Currently, if running "-overcommit cpu-pm=on" on hosts that don't have MWAIT support, the MWAIT/MONITOR feature is advertised to the guest and executing MWAIT/MONITOR on the guest triggers #UD. V2: - [PATCH 1]: took Thomas' suggestion for more generic fix - [PATCH 2/3]: no changes Zide Chen (3):

[PATCH V2 3/3] target/i386: Move host_cpu_enable_cpu_pm into kvm_cpu_realizefn()

It seems not a good idea to expand features in host_cpu_realizefn, which is for host CPU only. Additionally, cpu-pm option is KVM specific, and it's cleaner to put it in kvm_cpu_realizefn(), together with the WAITPKG code. Fixes: f5cc5a5c1686 ("i386: split cpu accelerators from cpu.c, using

[PATCH V2 2/3] target/i386: call cpu_exec_realizefn before x86_cpu_filter_features

cpu_exec_realizefn which calls the accel-specific realizefn may expand features. e.g., some accel-specific options may require extra features to be enabled, and it's appropriate to expand these features in accel- specific realizefn. One such example is the cpu-pm option, which may add

[PATCH V2 1/3] vl: Allow multiple -overcommit commands

Both cpu-pm and mem-lock are related to system resource overcommit, but they are separate from each other, in terms of how they are realized, and of course, they are applied to different system resources. It's tempting to use separate command lines to specify their behavior. e.g., in the

Re: [RFC PATCH v3 18/18] hw/arm/virt: Set SMMU OAS based on CPU PARANGE

Hi Mostafa, On 29/04/2024 04:24, Mostafa Saleh wrote: Use the new SMMU property to make the SMMU OAS match the CPU PARANGE. That's according to SMMU manual ARM IHI 0070F.b: > 6.3.6 SMMU_IDR5, OAS must match the system physical address size. Signed-off-by: Mostafa Saleh ---

[PATCH v2 5/6] Move tcg implementation of x86 get_physical_address into common helper code.

Signed-off-by: Don Porter --- target/i386/cpu.h| 41 ++ target/i386/helper.c | 515 + target/i386/tcg/sysemu/excp_helper.c | 555 +-- 3 files changed, 561 insertions(+), 550 deletions(-) diff --git

[PATCH v2 2/6] Convert 'info tlb' to use generic iterator

Signed-off-by: Don Porter --- target/i386/monitor.c | 203 ++ 1 file changed, 28 insertions(+), 175 deletions(-) diff --git a/target/i386/monitor.c b/target/i386/monitor.c index d7aae99c73..adf95edfb4 100644 --- a/target/i386/monitor.c +++

[PATCH v2 6/6] Convert x86_mmu_translate() to use common code.

Signed-off-by: Don Porter --- target/i386/arch_memory_mapping.c| 37 ++- target/i386/cpu.h| 11 +- target/i386/helper.c | 371 ++- target/i386/tcg/sysemu/excp_helper.c | 2 +- 4 files changed, 128 insertions(+), 293 deletions(-)

[PATCH v2 1/6] Add an "info pg" command that prints the current page tables

The new "info pg" monitor command prints the current page table, including virtual address ranges, flag bits, and snippets of physical page numbers. Completely filled regions of the page table with compatible flags are "folded", with the result that the complete output for a freshly booted x86-64

[PATCH v2 4/6] Convert x86_cpu_get_memory_mapping() to use generic iterators

Signed-off-by: Don Porter --- target/i386/arch_memory_mapping.c | 318 -- 1 file changed, 40 insertions(+), 278 deletions(-) diff --git a/target/i386/arch_memory_mapping.c b/target/i386/arch_memory_mapping.c index 00bf2a2116..040464dd34 100644 ---

[PATCH v2 0/6] Rework x86 page table walks

This version of the 'info pg' command adopts Peter Maydell's request to write some guest-agnostic page table iterator and accessor code, along with architecture-specific hooks. The first patch in this series contributes a generic page table iterator and an x86 instantiation. As a client, we

[PATCH v2 3/6] Convert 'info mem' to use generic iterator

Signed-off-by: Don Porter --- target/i386/monitor.c | 344 +- 1 file changed, 35 insertions(+), 309 deletions(-) diff --git a/target/i386/monitor.c b/target/i386/monitor.c index adf95edfb4..147743392d 100644 --- a/target/i386/monitor.c +++

Re: [PATCH] target/i386: disable jmp_opt if EFLAGS.RF is 1

On 5/24/24 08:33, Paolo Bonzini wrote: If EFLAGS.RF is 1, special processing in gen_eob_worker() is needed and therefore goto_tb cannot be used. Suggested-by: Richard Henderson Cc: qemu-sta...@nongnu.org Signed-off-by: Paolo Bonzini --- target/i386/tcg/translate.c | 2 +- 1 file changed, 1

Re: [PATCH] target/i386: always go through gen_eob*()

On 5/24/24 08:33, Paolo Bonzini wrote: Using DISAS_NORETURN does not process any of HF_INHIBIT_IRQ_MASK, HF_RF_MASK or HF_TF_MASK. Never use it, instead there is DISAS_EOB_ONLY. Cc: qemu-sta...@nongnu.org Signed-off-by: Paolo Bonzini --- target/i386/tcg/translate.c | 18 --

[PATCH 2/5] meson: remove unnecessary dependency

The dbus_display1_dep is not really used since all occurrences also request gio independently. Just list the generated sources and drop dbus_display1_dep. Signed-off-by: Paolo Bonzini --- audio/meson.build | 4 ++-- tests/qtest/meson.build | 2 +- ui/meson.build | 5 ++--- 3

[PATCH 1/5] meson: remove unnecessary reference to libm

libm is linked into all targets via libqemuutil, no need to specify it explicitly. Signed-off-by: Paolo Bonzini --- block/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/block/meson.build b/block/meson.build index e1f03fd773e..8993055c75e 100644 ---

[PATCH 4/5] meson: do not query modules before they are processed

Signed-off-by: Paolo Bonzini --- block/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/block/meson.build b/block/meson.build index 8993055c75e..158dc3b89db 100644 --- a/block/meson.build +++ b/block/meson.build @@ -119,7 +119,7 @@ foreach m : [ module_ss =

[PATCH 5/5] migration: remove unnecessary zlib dependency

zlib code is only used by the emulators, not by the tests. Signed-off-by: Paolo Bonzini --- meson.build | 2 +- migration/dirtyrate.c | 1 - migration/qemu-file.c | 1 - migration/meson.build | 2 +- 4 files changed, 2 insertions(+), 4 deletions(-) diff --git a/meson.build

[PATCH 3/5] tcg: include dependencies in static_library()

This ensures that for example libffi can be reached even if it is not in /usr/include. Signed-off-by: Paolo Bonzini --- tcg/meson.build | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tcg/meson.build b/tcg/meson.build index 8251589fd4e..ffbe754d8b3 100644 ---

[PATCH 0/5] meson: small cleanups

All found while looking at Akihiko's issues with declare_dependency( objects: ...). https://patchew.org/QEMU/20240524-objects-v1-0-07cbbe961...@daynix.com/ Paolo Bonzini (5): meson: remove unnecessary reference to libm meson: remove unnecessary dependency tcg: include dependencies

Re: [RFC PATCH 1/4] target/riscv/kvm: add software breakpoints support

On Tue, Apr 16, 2024 at 11:23 AM Daniel Henrique Barboza wrote: > > +int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint > > *bp, > > + vaddr len) > > +{ > > +if (len != 4 && len != 2) { > > +return -EINVAL; > > +} > > I

[PATCH] target/i386: always go through gen_eob*()

Using DISAS_NORETURN does not process any of HF_INHIBIT_IRQ_MASK, HF_RF_MASK or HF_TF_MASK. Never use it, instead there is DISAS_EOB_ONLY. Cc: qemu-sta...@nongnu.org Signed-off-by: Paolo Bonzini --- target/i386/tcg/translate.c | 18 -- target/i386/tcg/emit.c.inc | 4 ++-- 2

[PATCH] target/i386: disable jmp_opt if EFLAGS.RF is 1

If EFLAGS.RF is 1, special processing in gen_eob_worker() is needed and therefore goto_tb cannot be used. Suggested-by: Richard Henderson Cc: qemu-sta...@nongnu.org Signed-off-by: Paolo Bonzini --- target/i386/tcg/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

Re: [PATCH v2 1/3] hw/riscv/virt: Add memory hotplugging and virtio-md-pci support

On 5/24/24 12:02, David Hildenbrand wrote: On 24.05.24 15:14, Daniel Henrique Barboza wrote: On 5/21/24 07:56, Björn Töpel wrote: From: Björn Töpel Virtio-based memory devices (virtio-mem/virtio-pmem) allows for dynamic resizing of virtual machine memory, and requires proper hotplugging

Re: [PATCH 03/16] target/i386: document and group DISAS_* constants

On Fri, May 24, 2024 at 5:13 PM Richard Henderson wrote: > > On 5/24/24 08:04, Paolo Bonzini wrote: > > ... and nope, it's the other way round - DISAS_NORETURN is a bug > > waiting to happen for x86 translation because it doesn't process any > > of HF_INHIBIT_IRQ_MASK, HF_RF_MASK or HF_TF_MASK. >

Re: [PATCH v3 2/2] cxl/core: add poison creation event handler

在 2024/5/22 14:45, Dan Williams 写道: Shiyang Ruan wrote: [..] My expectation is MF_ACTION_REQUIRED is not appropriate for CXL event reported errors since action is only required for direct consumption events and those need not be reported through the device event queue. Got it. I'm not

Re: [PATCH 03/16] target/i386: document and group DISAS_* constants

On 5/24/24 08:04, Paolo Bonzini wrote: ... and nope, it's the other way round - DISAS_NORETURN is a bug waiting to happen for x86 translation because it doesn't process any of HF_INHIBIT_IRQ_MASK, HF_RF_MASK or HF_TF_MASK. Do you need to suppress use_goto_tb in these cases? r~

Re: [PATCH 16/16] target/i386: set CC_OP in helpers if they want CC_OP_EFLAGS

On 5/24/24 01:10, Paolo Bonzini wrote: Mark cc_op as clean and do not spill it at the end of the translation block. Technically this is a tiny bit less efficient, but: * it results in translations that are a tiny bit smaller * for most of these instructions, it is not unlikely that they are

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