Hi,
On Fri, 24 May 2024 at 16:23, Yong Huang wrote:
> I'm not testing the latest QEMU version while theoretically it is
> reproducible, I'll check it and give a conclusion.
* Yes, that'll help. Thank you.
> I'm not sure this usage is common but in our production environment, it is
> used.
* I
On Fri, 24 May 2024 at 18:00, Fabiano Rosas wrote:
> That's the point. If offset==0 we truncate all the way, if not, we truncate
> to the offset.
* Yes, I was wondering if the migration file has some data, but still
'offset' ends up being zero(0). If that's unlikely to happen, then we
are good.
Similar to other archs, build a custom bios memory updater. Running the
test with OF code is a cool trick, but SLOF takes a long time to boot.
This reduces test time by around 3x (150s to 50s).
Signed-off-by: Nicholas Piggin
---
tests/migration/migration-test.h | 1 +
tests/migration/ppc64/a-
ppc64 with TCG seems to no longer be failing this test. Let's try to
enable it. s390x is still hanging about 1 in 10 runs.
Signed-off-by: Nicholas Piggin
---
tests/qtest/migration-test.c | 16 +++-
1 file changed, 3 insertions(+), 13 deletions(-)
diff --git a/tests/qtest/migration-t
Signed-off-by: Nicholas Piggin
---
tests/qtest/migration-test.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/tests/qtest/migration-test.c b/tests/qtest/migration-test.c
index b7e3406471..c13535c37d 100644
--- a/tests/qtest/migration-test.c
+++ b/tests/qtest/migration-tes
ppc64 seems to be stable now, only problem is the speed, so I
rewrote the test to avoid SLOF and use special bios blob like
the other archs.
Thanks,
Nick
Nicholas Piggin (3):
tests/qtest/migration-test: Quieten ppc64 QEMU warnigns
tests/qtest/migration-test: Enable on ppc64
tests/qtest/migr
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/tcg/helper-a64.h| 4 +
target/arm/tcg/translate.h | 5 +
target/arm/tcg/a64.decode | 27 +
target/arm/tcg/translate-a64.c | 205 +
target/arm/tcg/vec_helper.c| 4
Signed-off-by: Richard Henderson
---
target/arm/tcg/a64.decode | 6 ++
target/arm/tcg/translate-a64.c | 34 +++---
2 files changed, 17 insertions(+), 23 deletions(-)
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 96ce35ad40..44383b4
These are the last instructions within handle_3same_float
and disas_simd_scalar_three_reg_same_fp16 so remove them.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/tcg/a64.decode | 12 ++
target/arm/tcg/translate-a64.c | 293 -
2
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/tcg/a64.decode | 10 +++
target/arm/tcg/translate-a64.c | 144 ++---
2 files changed, 51 insertions(+), 103 deletions(-)
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decod
Signed-off-by: Richard Henderson
---
target/arm/tcg/gengvec.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/target/arm/tcg/gengvec.c b/target/arm/tcg/gengvec.c
index 1d6bc6021d..1895c3b19f 100644
--- a/target/arm/tcg/gengvec.c
+++ b/target/arm/tcg/gengvec.c
@@ -943,9 +943
These are the only instructions in the 3 source scalar class.
Signed-off-by: Richard Henderson
---
target/arm/tcg/a64.decode | 10 ++
target/arm/tcg/translate-a64.c | 233 -
2 files changed, 93 insertions(+), 150 deletions(-)
diff --git a/target/arm/tcg/a64
Signed-off-by: Richard Henderson
---
target/arm/helper.h | 6 --
target/arm/tcg/translate.h | 5 ++
target/arm/tcg/gengvec.c| 144
target/arm/tcg/neon_helper.c| 27 --
target/arm/tcg/translate-a64.c | 17 ++--
target/arm/tcg
Signed-off-by: Richard Henderson
---
target/arm/helper.h | 8
target/arm/tcg/translate.h | 4
target/arm/tcg/neon-dp.decode | 10 ++---
target/arm/tcg/gengvec.c| 24 ++
target/arm/tcg/neon_helper.c| 36
Signed-off-by: Richard Henderson
---
target/arm/tcg/a64.decode | 4 +++
target/arm/tcg/translate-a64.c | 48 --
2 files changed, 26 insertions(+), 26 deletions(-)
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 85caf37948..96ce35ad40
Signed-off-by: Richard Henderson
---
target/arm/tcg/a64.decode | 2 ++
target/arm/tcg/translate-a64.c | 11 +++
2 files changed, 5 insertions(+), 8 deletions(-)
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 3061e26242..e33d91fd0a 100644
--- a/target/arm/t
Signed-off-by: Richard Henderson
---
target/arm/tcg/a64.decode | 5
target/arm/tcg/translate-a64.c | 51 +-
2 files changed, 25 insertions(+), 31 deletions(-)
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 07b604ec30..3ea064337
Signed-off-by: Richard Henderson
---
target/arm/tcg/gengvec.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/target/arm/tcg/gengvec.c b/target/arm/tcg/gengvec.c
index 51e66ccf5f..1d6bc6021d 100644
--- a/target/arm/tcg/gengvec.c
+++ b/target/arm/tcg/gengvec.c
@@ -933,14
Signed-off-by: Richard Henderson
---
target/arm/tcg/a64.decode | 4 ++
target/arm/tcg/translate-a64.c | 74 ++
2 files changed, 53 insertions(+), 25 deletions(-)
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 9e02776036..85caf37948
Signed-off-by: Richard Henderson
---
target/arm/tcg/a64.decode | 8
target/arm/tcg/translate-a64.c | 77 ++
2 files changed, 31 insertions(+), 54 deletions(-)
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 3ea0643370..2dea68a0a
The decode of FMOV (vector, immediate, half-precision) vs
invalid cases of MOVI are incorrect.
Fixes RISU mismatch for invalid insn 0x2f01fd31.
Fixes: 70b4e6a4457 ("arm/translate-a64: add FP16 FMOV to simd_mod_imm")
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-a64.c | 24 ++
Signed-off-by: Richard Henderson
---
target/arm/helper.h| 16 +
target/arm/tcg/translate-a64.h | 6 ++
target/arm/tcg/gengvec64.c | 106 +++
target/arm/tcg/translate-a64.c | 113 ++---
target/arm/tcg/vec_helper.c|
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-neon.c | 78 ++---
1 file changed, 4 insertions(+), 74 deletions(-)
diff --git a/target/arm/tcg/translate-neon.c b/target/arm/tcg/translate-neon.c
index 6c5a7a98e1..18b048611b 10
These are faux 2-operand instructions, reading from rd.
Sort them next to the other three-operand same insns for clarity.
Signed-off-by: Richard Henderson
---
target/arm/tcg/a64.decode | 8 +
target/arm/tcg/translate-a64.c | 64 --
2 files changed, 14 in
Load and zero-extend float16 into a TCGv_i32 before
all scalar operations.
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-vfp.c | 39 +++---
1 file changed, 22 insertions(+), 17 deletions(-)
diff --git a/target/arm/tcg/translate-vfp.c b/target/arm/tcg/
Signed-off-by: Richard Henderson
---
target/arm/tcg/a64.decode | 12 +++
target/arm/tcg/translate-a64.c | 132 -
2 files changed, 60 insertions(+), 84 deletions(-)
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 44383b4fc7..3061e2624
Signed-off-by: Richard Henderson
---
target/arm/tcg/a64.decode | 11
target/arm/tcg/translate-a64.c | 100 +++--
2 files changed, 68 insertions(+), 43 deletions(-)
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index f48adef5bb..19010af0
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper.h| 5 ++
target/arm/tcg/translate.h | 3 +
target/arm/tcg/a64.decode | 6 ++
target/arm/tcg/gengvec.c | 12
target/arm/tcg/translate-a64.c | 128 ++
We already have a gvec helper for the operations, but we aren't
using it on the aa32 neon side. Create a unified expander for
use by both aa32 and aa64 translators.
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate.h | 4
target/arm/tcg/gengvec.c| 20 +
Signed-off-by: Richard Henderson
---
target/arm/helper.h | 8 ++
target/arm/tcg/translate.h | 4 +++
target/arm/tcg/neon-dp.decode | 17 ++--
target/arm/tcg/gengvec.c| 24
target/arm/tcg/neon_helper.c| 24
target/arm/t
No need for a full comparison; xor produces non-zero bits
for QC just fine.
Signed-off-by: Richard Henderson
---
target/arm/tcg/gengvec.c | 32
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/target/arm/tcg/gengvec.c b/target/arm/tcg/gengvec.c
ind
Signed-off-by: Richard Henderson
---
target/arm/tcg/a64.decode | 2 ++
target/arm/tcg/translate-a64.c | 11 +++
2 files changed, 5 insertions(+), 8 deletions(-)
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index e33d91fd0a..b1bbcb144e 100644
--- a/target/arm/t
Signed-off-by: Richard Henderson
---
target/arm/tcg/a64.decode | 4
target/arm/tcg/translate-a64.c | 22 +++---
2 files changed, 11 insertions(+), 15 deletions(-)
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index ea897d6732..9e02776036 100644
---
Split some routines out of translate-a64.c and translate-sve.c
that are used by both.
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-a64.h | 4 +
target/arm/tcg/gengvec64.c | 190 +++
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper.h | 2 --
target/arm/tcg/neon_helper.c| 5 -
target/arm/tcg/translate-neon.c | 3 +--
3 files changed, 1 insertion(+), 9 deletions(-)
diff --git a/target/arm/helper.h b/target/arm/helper.h
inde
This eliminates the last uses of these neon helpers.
Incorporate the MO_64 expanders as an option to the vector expander.
Signed-off-by: Richard Henderson
---
target/arm/helper.h| 17
target/arm/tcg/translate.h | 15 +++
target/arm/tcg/gengvec.c | 116 +++
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper.h | 7 -
target/arm/tcg/translate-neon.c | 55 ++---
target/arm/tcg/vec_helper.c | 45 ---
3 files changed, 3 insertions(+), 104 deletions(-)
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper.h| 4 ++
target/arm/tcg/a64.decode | 12 +
target/arm/tcg/translate-a64.c | 87 ++
target/arm/tcg/vec_helper.c| 23 +
4 files changed, 105 insertion
These are the last instructions within disas_simd_three_reg_same_fp16,
so remove it.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper.h| 16 ++
target/arm/tcg/a64.decode | 24 +++
target/arm/tcg/translate-a64.c | 296 ++
Signed-off-by: Richard Henderson
---
target/arm/helper.h | 7 --
target/arm/tcg/translate.h | 4 +
target/arm/tcg/gengvec.c| 144
target/arm/tcg/neon_helper.c| 27 --
target/arm/tcg/translate-a64.c | 48 ++-
target/a
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/tcg/a64.decode | 21 +++--
target/arm/tcg/translate-a64.c | 86 +++---
2 files changed, 54 insertions(+), 53 deletions(-)
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.d
This includes AND, ORR, EOR, BIC, ORN, BSF, BIT, BIF.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/tcg/a64.decode | 10 +
target/arm/tcg/translate-a64.c | 68 ++
2 files changed, 29 insertions(+), 49 deletions(-)
diff --git
Signed-off-by: Richard Henderson
---
target/arm/helper.h | 6 --
target/arm/tcg/translate.h | 4 +
target/arm/tcg/gengvec.c| 144
target/arm/tcg/neon_helper.c| 27 --
target/arm/tcg/translate-a64.c | 17 ++--
target/arm/tcg/
Fixes RISU mismatch for "fcvtzs h31, h0, #14".
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-a64.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 4126aaa27e..d97acdbaf9 100644
--- a/target/arm/tcg/trans
Signed-off-by: Richard Henderson
---
target/arm/tcg/a64.decode | 4
target/arm/tcg/translate-a64.c | 22 ++
2 files changed, 10 insertions(+), 16 deletions(-)
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 1c448b4f7c..bc98963bc5 100644
---
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/tcg/a64.decode | 11
target/arm/tcg/translate-a64.c | 97 --
2 files changed, 32 insertions(+), 76 deletions(-)
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
Signed-off-by: Richard Henderson
---
target/arm/tcg/a64.decode | 4 ++
target/arm/tcg/translate-a64.c | 108 ++---
2 files changed, 49 insertions(+), 63 deletions(-)
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 6f6cd805b7..5dadbc74d7
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper.h| 4 +
target/arm/tcg/a64.decode | 17
target/arm/tcg/translate-a64.c | 168 +
target/arm/tcg/vec_helper.c| 4 +
4 files changed, 113 insertions(+), 8
Signed-off-by: Richard Henderson
---
target/arm/tcg/a64.decode | 4
target/arm/tcg/translate-a64.c | 22 ++
2 files changed, 10 insertions(+), 16 deletions(-)
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index bc98963bc5..07b604ec30 100644
---
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/tcg/a64.decode | 4
target/arm/tcg/translate-a64.c | 43 +++---
2 files changed, 18 insertions(+), 29 deletions(-)
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
These are the last instructions within disas_simd_three_reg_same
and disas_simd_scalar_three_reg_same, so remove them.
Signed-off-by: Richard Henderson
---
target/arm/helper.h| 10 ++
target/arm/tcg/a64.decode | 18 +++
target/arm/tcg/translate-a64.c | 276 ++--
Signed-off-by: Richard Henderson
---
target/arm/tcg/a64.decode | 2 ++
target/arm/tcg/translate-a64.c | 11 +++
2 files changed, 5 insertions(+), 8 deletions(-)
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index b1bbcb144e..1c448b4f7c 100644
--- a/target/arm/t
Signed-off-by: Richard Henderson
---
target/arm/tcg/a64.decode | 7 ++
target/arm/tcg/translate-a64.c | 40 +-
2 files changed, 32 insertions(+), 15 deletions(-)
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 7c350ba833..ea897d6
Signed-off-by: Richard Henderson
---
target/arm/helper.h | 10 +
target/arm/tcg/translate.h | 4
target/arm/tcg/neon-dp.decode | 10 ++---
target/arm/tcg/gengvec.c| 22 +++
target/arm/tcg/neon_helper.c| 38 ++
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/tcg/a64.decode | 13 +
target/arm/tcg/translate-a64.c | 426 +++--
2 files changed, 152 insertions(+), 287 deletions(-)
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/tcg/a64.decode | 10
target/arm/tcg/translate-a64.c | 43 ++
2 files changed, 22 insertions(+), 31 deletions(-)
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.de
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper.h| 6
target/arm/tcg/translate.h | 30 +++
target/arm/tcg/translate-a64.c | 44 +--
target/arm/tcg/translate-vfp.c | 54 +---
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate.h |5 +
target/arm/tcg/gengvec.c | 1612
target/arm/tcg/translate.c | 1588 ---
target/arm/tcg/
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/tcg/a64.decode | 6
target/arm/tcg/translate-a64.c | 54 +++---
2 files changed, 10 insertions(+), 50 deletions(-)
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/tcg/a64.decode | 11 +
target/arm/tcg/translate-a64.c | 78 +-
2 files changed, 21 insertions(+), 68 deletions(-)
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decod
All of these insns have "if sz == '1' then UNDEFINED" in their pseudocode.
Fixes a RISU miscompare for invalid insn 0x5ef0c87a.
Fixes: 5c36d89567c ("arm/translate-a64: add all FP16 ops in
simd_scalar_pairwise")
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-a64.c | 2 +-
1 file c
This is the last instruction within disas_fp_2src,
so remove that and its subroutines.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/tcg/a64.decode | 1 +
target/arm/tcg/translate-a64.c | 177 +
2 files changed, 27 insertions(+
Hack, because there should be a better way to do this without
duplicating code between cpu32.c and cpu64.c. Hack, because
qemu-arm crashes without ARM_FEATURE_AARCH64 disabled.
Needed in order to compare RISU results with aarch64.ci.qemu.org.
Signed-off-by: Richard Henderson
---
target/arm/tcg
This eliminates the last uses of these neon helpers.
Incorporate the MO_64 expanders as an option to the vector expander.
Signed-off-by: Richard Henderson
---
target/arm/helper.h| 8 --
target/arm/tcg/translate-a64.h | 8 ++
target/arm/tcg/gengvec64.c | 71 ++
ta
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper.h| 5 +
target/arm/tcg/a64.decode | 30 ++
target/arm/tcg/translate-a64.c | 188 +++--
target/arm/tcg/vec_helper.c| 30 ++
4 files changed, 174 insertion
Convert all forms (scalar, vector, scalar indexed, vector indexed),
which allows us to remove switch table entries elsewhere.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/tcg/helper-a64.h| 8 ++
target/arm/tcg/a64.decode | 45 +++
target/arm/tcg/tra
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/tcg/a64.decode | 5
target/arm/tcg/translate-a64.c | 50 ++
2 files changed, 8 insertions(+), 47 deletions(-)
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/tcg/a64.decode | 8 ++
target/arm/tcg/translate-a64.c | 132 +++--
2 files changed, 51 insertions(+), 89 deletions(-)
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper.h| 2 +
target/arm/tcg/a64.decode | 22 +++
target/arm/tcg/translate-a64.c | 241 +
target/arm/tcg/vec_helper.c| 14 ++
4 files changed, 163 insertions(+), 1
This fixes a bug in that neither PLI nor PLDW are present in ARMv6T2,
but are introduced with ARMv7 and ARMv7MP respectively.
For clarity, do not use NOP for PLD.
Note that there is no PLDW (literal) -- bit 5 of the first word
is not decoded, and is PLD (literal). Confirmed on neoverse-n1
host wh
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper.h| 1 +
target/arm/tcg/a64.decode | 6
target/arm/tcg/translate-a64.c | 60 ++
target/arm/tcg/vec_helper.c| 6
4 files changed, 53 insertions(+), 20
For all, rm == 15 is invalid.
Prior to v8, thumb with rm == 13 is invalid.
For PLDW, rn == 15 is invalid.
Fixes a RISU mismatch for the HINTSPACE pattern in t32.risu
compared to a neoverse-n1 host.
Signed-off-by: Richard Henderson
---
target/arm/tcg/a32-uncond.decode | 8 +++--
target/arm/tcg/
These are the last instructions within handle_simd_3same_pair
so remove it.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper.h| 16 +
target/arm/tcg/translate.h | 8 +++
target/arm/tcg/a64.decode | 4 ++
target/arm/tcg/gengvec.c
In the process, convert more code to gvec as well -- I will need
the gvec code for implementing SME2. I guess this is about 1/3
of the job done, but there's no reason to wait until the patch
set is completely unwieldy.
Changes for v2:
* Fix existing RISU failures vs neoverse-n1.
* Introduce v
Currently, if running "-overcommit cpu-pm=on" on hosts that don't
have MWAIT support, the MWAIT/MONITOR feature is advertised to the
guest and executing MWAIT/MONITOR on the guest triggers #UD.
V2:
- [PATCH 1]: took Thomas' suggestion for more generic fix
- [PATCH 2/3]: no changes
Zide Chen (3):
It seems not a good idea to expand features in host_cpu_realizefn,
which is for host CPU only. Additionally, cpu-pm option is KVM
specific, and it's cleaner to put it in kvm_cpu_realizefn(), together
with the WAITPKG code.
Fixes: f5cc5a5c1686 ("i386: split cpu accelerators from cpu.c, using
Acce
cpu_exec_realizefn which calls the accel-specific realizefn may expand
features. e.g., some accel-specific options may require extra features
to be enabled, and it's appropriate to expand these features in accel-
specific realizefn.
One such example is the cpu-pm option, which may add CPUID_EXT_M
Both cpu-pm and mem-lock are related to system resource overcommit, but
they are separate from each other, in terms of how they are realized,
and of course, they are applied to different system resources.
It's tempting to use separate command lines to specify their behavior.
e.g., in the following
Hi Mostafa,
On 29/04/2024 04:24, Mostafa Saleh wrote:
Use the new SMMU property to make the SMMU OAS match the CPU PARANGE.
That's according to SMMU manual ARM IHI 0070F.b: > 6.3.6 SMMU_IDR5, OAS
must match the system physical address size.
Signed-off-by: Mostafa Saleh
---
hw/arm/vi
Signed-off-by: Don Porter
---
target/i386/cpu.h| 41 ++
target/i386/helper.c | 515 +
target/i386/tcg/sysemu/excp_helper.c | 555 +--
3 files changed, 561 insertions(+), 550 deletions(-)
diff --git a/target/i386
Signed-off-by: Don Porter
---
target/i386/monitor.c | 203 ++
1 file changed, 28 insertions(+), 175 deletions(-)
diff --git a/target/i386/monitor.c b/target/i386/monitor.c
index d7aae99c73..adf95edfb4 100644
--- a/target/i386/monitor.c
+++ b/target/i386/mo
Signed-off-by: Don Porter
---
target/i386/arch_memory_mapping.c| 37 ++-
target/i386/cpu.h| 11 +-
target/i386/helper.c | 371 ++-
target/i386/tcg/sysemu/excp_helper.c | 2 +-
4 files changed, 128 insertions(+), 293 deletions(-)
The new "info pg" monitor command prints the current page table,
including virtual address ranges, flag bits, and snippets of physical
page numbers. Completely filled regions of the page table with
compatible flags are "folded", with the result that the complete
output for a freshly booted x86-64
Signed-off-by: Don Porter
---
target/i386/arch_memory_mapping.c | 318 --
1 file changed, 40 insertions(+), 278 deletions(-)
diff --git a/target/i386/arch_memory_mapping.c
b/target/i386/arch_memory_mapping.c
index 00bf2a2116..040464dd34 100644
--- a/target/i386/arch_
This version of the 'info pg' command adopts Peter Maydell's request
to write some guest-agnostic page table iterator and accessor code,
along with architecture-specific hooks. The first patch in this
series contributes a generic page table iterator and an x86
instantiation. As a client, we first
Signed-off-by: Don Porter
---
target/i386/monitor.c | 344 +-
1 file changed, 35 insertions(+), 309 deletions(-)
diff --git a/target/i386/monitor.c b/target/i386/monitor.c
index adf95edfb4..147743392d 100644
--- a/target/i386/monitor.c
+++ b/target/i386/mo
On 5/24/24 08:33, Paolo Bonzini wrote:
If EFLAGS.RF is 1, special processing in gen_eob_worker() is needed and
therefore goto_tb cannot be used.
Suggested-by: Richard Henderson
Cc: qemu-sta...@nongnu.org
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 2 +-
1 file changed, 1
On 5/24/24 08:33, Paolo Bonzini wrote:
Using DISAS_NORETURN does not process any of HF_INHIBIT_IRQ_MASK,
HF_RF_MASK or HF_TF_MASK. Never use it, instead there is
DISAS_EOB_ONLY.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 18 --
The dbus_display1_dep is not really used since all occurrences also
request gio independently. Just list the generated sources and drop
dbus_display1_dep.
Signed-off-by: Paolo Bonzini
---
audio/meson.build | 4 ++--
tests/qtest/meson.build | 2 +-
ui/meson.build | 5 ++---
3 file
libm is linked into all targets via libqemuutil, no need to specify it
explicitly.
Signed-off-by: Paolo Bonzini
---
block/meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/block/meson.build b/block/meson.build
index e1f03fd773e..8993055c75e 100644
--- a/block/meson.
Signed-off-by: Paolo Bonzini
---
block/meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/block/meson.build b/block/meson.build
index 8993055c75e..158dc3b89db 100644
--- a/block/meson.build
+++ b/block/meson.build
@@ -119,7 +119,7 @@ foreach m : [
module_ss = ss.
zlib code is only used by the emulators, not by the tests.
Signed-off-by: Paolo Bonzini
---
meson.build | 2 +-
migration/dirtyrate.c | 1 -
migration/qemu-file.c | 1 -
migration/meson.build | 2 +-
4 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/meson.build b/meson.bui
This ensures that for example libffi can be reached even if it is not
in /usr/include.
Signed-off-by: Paolo Bonzini
---
tcg/meson.build | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/tcg/meson.build b/tcg/meson.build
index 8251589fd4e..ffbe754d8b3 100644
--- a/tcg/me
All found while looking at Akihiko's issues with declare_dependency(
objects: ...).
https://patchew.org/QEMU/20240524-objects-v1-0-07cbbe961...@daynix.com/
Paolo Bonzini (5):
meson: remove unnecessary reference to libm
meson: remove unnecessary dependency
tcg: include dependenci
On Tue, Apr 16, 2024 at 11:23 AM Daniel Henrique Barboza
wrote:
> > +int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint
> > *bp,
> > + vaddr len)
> > +{
> > +if (len != 4 && len != 2) {
> > +return -EINVAL;
> > +}
>
> I wonder
Using DISAS_NORETURN does not process any of HF_INHIBIT_IRQ_MASK,
HF_RF_MASK or HF_TF_MASK. Never use it, instead there is
DISAS_EOB_ONLY.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 18 --
target/i386/tcg/emit.c.inc | 4 ++--
2 fi
If EFLAGS.RF is 1, special processing in gen_eob_worker() is needed and
therefore goto_tb cannot be used.
Suggested-by: Richard Henderson
Cc: qemu-sta...@nongnu.org
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/t
On 5/24/24 12:02, David Hildenbrand wrote:
On 24.05.24 15:14, Daniel Henrique Barboza wrote:
On 5/21/24 07:56, Björn Töpel wrote:
From: Björn Töpel
Virtio-based memory devices (virtio-mem/virtio-pmem) allows for
dynamic resizing of virtual machine memory, and requires proper
hotplugging
On Fri, May 24, 2024 at 5:13 PM Richard Henderson
wrote:
>
> On 5/24/24 08:04, Paolo Bonzini wrote:
> > ... and nope, it's the other way round - DISAS_NORETURN is a bug
> > waiting to happen for x86 translation because it doesn't process any
> > of HF_INHIBIT_IRQ_MASK, HF_RF_MASK or HF_TF_MASK.
>
在 2024/5/22 14:45, Dan Williams 写道:
Shiyang Ruan wrote:
[..]
My expectation is MF_ACTION_REQUIRED is not appropriate for CXL event
reported errors since action is only required for direct consumption
events and those need not be reported through the device event queue.
Got it.
I'm not very
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