25.06.2024 21:35, Richard Henderson wrote:
The inner loop, bounded by eltspersegment, must not be
larger than the outer loop, bounded by elements.
Cc: qemu-sta...@nongnu.org
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/tcg/vec_helper.c | 24 -
Hi
On Tue, Jul 2, 2024 at 4:09 AM wrote:
> From: Dongwon Kim
>
> Enable hotkey for toggling window fullscreening for all individual
> untabified VCs
>
> Cc: Marc-André Lureau
> Cc: Vivek Kasireddy
> Signed-off-by: Dongwon Kim
>
Reviewed-by: Marc-André Lureau
(/rant I wish we had more comm
On 02/07/2024 00.23, BALATON Zoltan wrote:
On Mon, 1 Jul 2024, Michael S. Tsirkin wrote:
On Thu, Jun 27, 2024 at 10:37:43PM +0900, Akihiko Odaki wrote:
Based-on:
<3ad18bc590ef28e1526e8053568086b453e7ffde.1718211878.git.quic_mathb...@quicinc.com>
("[PATCH] cpu: fix memleak of 'halt_cond' and 't
On 27/06/2024 15.37, Akihiko Odaki wrote:
A test function may not be executed depending on the test command line
so it is wrong to free data with a test function. Use
qtest_add_data_func_full() to register a function to free data.
Signed-off-by: Akihiko Odaki
---
tests/qtest/device-introspect
On 6/25/24 9:07 AM, Jamin Lin wrote:
change from v1:
aspeed/soc: coverity defect: DIVIDE_BY_ZERO
aspeed/sdmc: coverity defect: Control flow issues (DEADCODE)
change from v2:
add more commit log from reviewer suggestion, Cédric.
change from v3:
replace qemu_log_mask with assert dram size 0.
Jam
From: Michael S. Tsirkin
Sent: 01 July 2024 22:02
To: CLEMENT MATHIEU--DRIF
Cc: qemu-devel@nongnu.org ; jasow...@redhat.com
; zhenzhong.d...@intel.com ;
kevin.t...@intel.com ; yi.l@intel.com
; joao.m.mart...@oracle.com ;
pet...@redhat.com
Subject: Re: [
On 6/25/24 8:58 AM, Cédric Le Goater wrote:
The RAM size of the SDMC device is validated for the SoC and set when
the Aspeed machines are initialized and then later used by several
SoC implementations. However, the SDMC model never checks that the RAM
size has been actually set before being used.
On 6/25/24 9:08 AM, Cédric Le Goater wrote:
The tacoma-bmc machine was a board including an AST2600 SoC based BMC
and a witherspoon like OpenPOWER system. It was used for bring up of
the AST2600 SoC in labs. It can be easily replaced by the rainier-bmc
machine which is part of a real product offe
On 6/19/24 12:01 PM, Jamin Lin wrote:
Fix coding style issues from checkpatch.pl
Test command:
./scripts/checkpatch.pl --no-tree -f hw/net/ftgmac100.c
Signed-off-by: Jamin Lin
Applied to aspeed-next.
Thanks,
C.
---
hw/net/ftgmac100.c | 12
1 file changed, 8 insertions
From: Clément Mathieu--Drif
Signed-off-by: Clément Mathieu--Drif
---
hw/pci/pci.c| 24 ++--
include/hw/pci/pci_device.h | 1 +
2 files changed, 15 insertions(+), 10 deletions(-)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index c8a8aab306..51feede3cf 100644
--
From: Clément Mathieu--Drif
Signed-off-by: Clément Mathieu--Drif
---
hw/pci/pcie.c | 24 +++
include/hw/pci/pcie.h | 6 +-
include/hw/pci/pcie_regs.h| 3 +++
include/standard-headers/linux/pci_regs.h | 1
From: Clément Mathieu--Drif
Signed-off-by: Clément Mathieu--Drif
---
hw/i386/intel_iommu.c | 2 +-
hw/i386/intel_iommu_internal.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 71cebe2fd3..2a78fc823f 100644
--- a
From: Clément Mathieu--Drif
Signed-off-by: Clément Mathieu--Drif
---
hw/i386/intel_iommu.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index e047d2ca83..2e4f535dd1 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu
From: Clément Mathieu--Drif
IOMMU have to implement iommu_ats_request_translation to support ATS.
Devices can use IOMMU_TLB_ENTRY_TRANSLATION_ERROR to check the tlb
entries returned by a translation request.
Signed-off-by: Clément Mathieu--Drif
---
include/exec/memory.h | 26 +
From: Clément Mathieu--Drif
Signed-off-by: Clément Mathieu--Drif
---
hw/i386/intel_iommu.c | 13 ++---
include/hw/i386/intel_iommu.h | 2 +-
2 files changed, 11 insertions(+), 4 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 2a78fc823f..e047d2ca8
From: Clément Mathieu--Drif
ats_enabled and pasid_enabled check whether the capabilities are
present or not. If so, we read the configuration space to get
the status of the feature (enabled or not).
Signed-off-by: Clément Mathieu--Drif
---
hw/pci/pcie.c | 18 ++
include
From: Clément Mathieu--Drif
This will help developers of svm devices to track a state
Signed-off-by: Clément Mathieu--Drif
---
include/exec/memory.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/exec/memory.h b/include/exec/memory.h
index aa8e114e77..bf91c4bed7 100644
--- a/inclu
From: Clément Mathieu--Drif
Signed-off-by: Clément Mathieu--Drif
---
tests/unit/meson.build | 1 +
tests/unit/test-atc.c | 527 +
2 files changed, 528 insertions(+)
create mode 100644 tests/unit/test-atc.c
diff --git a/tests/unit/meson.build b/tests/
From: Clément Mathieu--Drif
As the SVM-capable devices will need to cache translations, we provide
an first implementation.
This cache uses a two-level design based on hash tables.
The first level is indexed by a PASID and the second by a virtual addresse.
Signed-off-by: Clément Mathieu--Drif
From: Clément Mathieu--Drif
We add a convenient way to initialize an device-iotlb notifier.
This is meant to be used by ATS-capable devices.
pci_device_iommu_memory_region_pasid is introduces in this commit and
will be used in several other SVM-related functions exposed in
the PCI API.
Signed-o
From: Clément Mathieu--Drif
Implements the behavior defined in section 10.2.3.5 of PCIe spec rev 5.
This is needed by devices that support ATS.
Signed-off-by: Clément Mathieu--Drif
---
hw/i386/intel_iommu.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/hw/i386/
From: Clément Mathieu--Drif
Signed-off-by: Clément Mathieu--Drif
Reviewed-by: Zhenzhong Duan
---
hw/i386/intel_iommu.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 98996ededc..71cebe2fd3 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw
From: Clément Mathieu--Drif
Devices implementing ATS can send translation requests using
pci_ats_request_translation_pasid.
The invalidation events are sent back to the device using the iommu
notifier managed with pci_register_iommu_tlb_event_notifier and
pci_unregister_iommu_tlb_event_notifier
From: Clément Mathieu--Drif
This will be useful for devices that support ATS
Signed-off-by: Clément Mathieu--Drif
---
include/exec/memory.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/exec/memory.h b/include/exec/memory.h
index bf91c4bed7..003ee06610 100644
--- a/include/exec/m
From: Clément Mathieu--Drif
This will be necessary for devices implementing ATS.
We also define a new macro IOMMU_ACCESS_FLAG_FULL in addition to
IOMMU_ACCESS_FLAG to support more access flags.
IOMMU_ACCESS_FLAG is kept for convenience and backward compatibility.
Here are the flags added (define
From: Clément Mathieu--Drif
Signed-off-by: Clément Mathieu--Drif
---
hw/pci/pci.c | 19 +++
include/hw/pci/pci.h | 34 ++
2 files changed, 53 insertions(+)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index 51feede3cf..3fe47d4002 100644
--- a
From: Clément Mathieu--Drif
The 'level' field in vtd_iotlb_key is an unsigned integer.
We don't need to store level as an int in vtd_lookup_iotlb.
VTDIOTLBPageInvInfo.mask is used in binary operations with addresses.
Signed-off-by: Clément Mathieu--Drif
---
hw/i386/intel_iommu.c | 2
From: Clément Mathieu--Drif
The constant must be unsigned, otherwise the two's complement
overrides the other fields when a PASID is present
Signed-off-by: Clément Mathieu--Drif
---
hw/i386/intel_iommu_internal.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/i386/intel
From: Clément Mathieu--Drif
Signed-off-by: Clément Mathieu--Drif
---
hw/i386/intel_iommu.c | 75 --
hw/i386/intel_iommu_internal.h | 1 +
2 files changed, 73 insertions(+), 3 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index
From: Clément Mathieu--Drif
Signed-off-by: Clément Mathieu--Drif
---
hw/i386/intel_iommu.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 2e4f535dd1..f77972130f 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -2
From: Clement Mathieu--Drif
This series belongs to a list of series that add SVM support for VT-d.
As a starting point, we use the series called 'intel_iommu: Enable stage-1
translation' (rfc2) by Zhenzhong Duan and Yi Liu.
Here we focus on the implementation of ATS support in the IOMMU and on
From: Clément Mathieu--Drif
We use this information in vtd_do_iommu_translate to populate the
IOMMUTLBEntry and indicate the correct page mask. This prevents ATS
devices from sending many useless translation requests when a megapage
or gigapage iova is not mapped to a physical address.
Signed-of
Hi Huang, Ying,
Thanks for your feedback and helpful suggestions. Replies inlined.
June 30, 2024 at 10:13 PM, "Huang, Ying" wrote:
>
> Hi, Jack,
>
> "Ho-Ren (Jack) Chuang" writes:
>
> I suggest you to merge the [0/1] with the change log here. [0/1]
>
> describes why do we need the patch. T
On Fri, 2024-06-28 at 11:16 +0200, Cédric Le Goater wrote:
> On 6/28/24 9:02 AM, Philippe Mathieu-Daudé wrote:
> > When booting U-boot/Linux on Aspeed boards via eMMC,
> > some commands don't behave as expected from the spec.
> >
> > Add the 'x-aspeed-emmc-kludge' property to allow non
> > standar
From: Akihiko Odaki
macOS versions older than 12.0 are no longer supported.
docs/about/build-platforms.rst says:
> Support for the previous major version will be dropped 2 years after
> the new major version is released or when the vendor itself drops
> support, whichever comes first.
macOS 12.
From: Thomas Huth
hw/hw.h only contains the prototype of hw_error() nowadays, so
files that don't use this function don't need to include this
header.
Signed-off-by: Thomas Huth
Reviewed-by: Cédric Le Goater
Reviewed-by: Peter Maydell
Message-ID: <20240701132649.58345-1-th...@redhat.com>
Sign
From: Daniel P. Berrangé
This changes the DEFINE_SPAPR_MACHINE macro to use the common
helpers for constructing versioned symbol names and strings,
bringing greater consistency across targets.
The added benefit is that it avoids the need to repeat the
version number twice in two different format
From: Daniel P. Berrangé
This calls the MACHINE_VER_DELETION() macro in the machine type
registration method, so that when a versioned machine type reaches
the end of its life, it is no longer registered with QOM and thus
cannot be used.
The actual definition of the machine type should be delete
From: Akihiko Odaki
macOS versions older than 12.0 are no longer supported.
docs/about/build-platforms.rst says:
> Support for the previous major version will be dropped 2 years after
> the new major version is released or when the vendor itself drops
> support, whichever comes first.
macOS 12.
From: Akihiko Odaki
macOS versions older than 12.0 are no longer supported.
docs/about/build-platforms.rst says:
> Support for the previous major version will be dropped 2 years after
> the new major version is released or when the vendor itself drops
> support, whichever comes first.
macOS 12.
From: Akihiko Odaki
macOS versions older than 12.0 are no longer supported.
docs/about/build-platforms.rst says:
> Support for the previous major version will be dropped 2 years after
> the new major version is released or when the vendor itself drops
> support, whichever comes first.
macOS 12.
From: Daniel P. Berrangé
The various targets which define versioned machine types have
a bunch of obfuscated macro code for defining unique function
and variable names using string concatenation.
This adds a couple of helpers to improve the clarity of such
code macro.
Reviewed-by: Thomas Huth
From: Akihiko Odaki
dump_guest_core is exposed as dump-guest-core with QOM.
Signed-off-by: Akihiko Odaki
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: David Hildenbrand
Message-ID: <20240628-dump-v1-1-c581d10f3...@daynix.com>
Signed-off-by: Philippe Mathieu-Daudé
---
system/physmem.c | 2
From: Mark Cave-Ayland
This prevents the IRQs from being leaked when the macio IDE device is used.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Peter Maydell
Reviewed-by: Akihiko Odaki
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <20240628160334.653168-1-mark.cave-ayl...@ilande.co.uk>
Sig
From: Daniel P. Berrangé
The automatic deprecation mechanism introduced in the preceeding patches
will mark every i440fx machine upto and including 2.12 as deprecated. As
such we can revert the manually added deprecation introduced in:
commit 792b4fdd4eb8197bd6eb9e80a1dfaf0cb3b54aeb
Author:
From: Daniel P. Berrangé
This extends the deprecation policy to indicate that versioned machine
types will be marked deprecated after 3 years, and then subject to
removal after a further 3 years has passed.
Reviewed-by: Thomas Huth
Signed-off-by: Daniel P. Berrangé
Reviewed-by: Philippe Mathie
From: Daniel P. Berrangé
This changes the DEFINE_I440FX_MACHINE macro to use the common
helpers for constructing versioned symbol names and strings,
bringing greater consistency across targets.
The added benefit is that it avoids the need to repeat the
version number thrice in three different fo
From: Daniel P. Berrangé
This changes the DEFINE_Q35_MACHINE macro to use the common
helpers for constructing versioned symbol names and strings,
bringing greater consistency across targets.
The added benefit is that it avoids the need to repeat the
version number thrice in three different forma
From: Daniel P. Berrangé
The automatic deprecation mechanism introduced in the preceeding patches
will mark every spapr machine upto and including 2.12 as deprecated. As
such we can revert the manually added deprecation which was a subset:
commit 1392617d35765d5d912625fbb5cab1ffbed8e140
Auth
From: Daniel P. Berrangé
This calls the MACHINE_VER_DEPRECATION() macro in the definition of
all machine type classes which support versioning. This ensures
that they will automatically get deprecation info set when they
reach the appropriate point in their lifecycle.
Reviewed-by: Thomas Huth
S
From: Daniel P. Berrangé
This changes the DEFINE_VIRT_MACHINE macro to use the common
helpers for constructing versioned symbol names and strings,
bringing greater consistency across targets.
Reviewed-by: Thomas Huth
Signed-off-by: Daniel P. Berrangé
Reviewed-by: Philippe Mathieu-Daudé
Messag
From: Daniel P. Berrangé
The new deprecation and deletion policy for versioned machine types is
being introduced in QEMU 9.1.0.
Under the new policy a number of old machine types (any prior to 2.12)
would be liable for immediate deletion which would be a violation of our
historical deprecation a
From: Daniel P. Berrangé
Versioned machines live for a long time to provide back compat for
incoming migration and restore of saved images. To guide users away from
usage of old machines, however, we want to deprecate any older than 3
years (equiv of 9 releases), and delete any older than 6 years
The following changes since commit b6d32a06fc0984e537091cba08f2e1ed9f775d74:
Merge tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu into
staging (2024-06-30 16:12:24 -0700)
are available in the Git repository at:
https://github.com/philmd/qemu.git tags/hw-misc-20240702
for you t
From: Daniel P. Berrangé
This changes the DEFINE_CCW_MACHINE macro to use the common
helpers for constructing versioned symbol names and strings,
bringing greater consistency across targets.
The added benefit is that it avoids the need to repeat the
version number twice in two different formats
From: Daniel P. Berrangé
This changes the DEFINE_VIRT_MACHINE macro to use the common
helpers for constructing versioned symbol names and strings,
bringing greater consistency across targets.
A DEFINE_VIRT_MACHINE_AS_LATEST helper is added so that it
is not required to pass 'false' for every sin
From: Oleg Sviridov
Pointer, returned from function 'spapr_vio_find_by_reg',
may be NULL and is dereferenced immediately after.
Found by Linux Verification Center (linuxtesting.org) with SVACE.
Signed-off-by: Oleg Sviridov
Message-ID: <20240531073636.3779559-1-oleg.sviri...@red-soft.ru>
Signed
On 1/7/24 22:01, Thomas Huth wrote:
The initial virtio-net-ccw devices currently do not have a proper parent
in the QOM tree, so they show up under /machine/unattached - which is
somewhat ugly. Let's attach them to /machine/virtual-css-bridge/virtual-css
instead.
Signed-off-by: Thomas Huth
---
> From: "Michael S. Tsirkin"
> Date: Mon, Jul 1, 2024, 23:17
> Subject: Re: [PATCH] vhost-user: Skip unnecessary duplicated
> VHOST_USER_SET_LOG_BASE requests
> To: "Alex Bennée"
> Cc: "BillXiang",
> On Mon, Jul 01, 2024 at 04:14:35PM +0100, Alex Bennée wrote:
> > "BillXiang" writes:
> >
>
On 5/30/2024 7:16 PM, Pankaj Gupta wrote:
From: Michael Roth
SEV-SNP firmware allows a special guest page to be populated with a
table of guest CPUID values so that they can be validated through
firmware before being loaded into encrypted guest memory where they can
be used in place of hypervis
On 2024/6/21 17:20, Chen, Jiqian wrote:
> Hi MST,
>
> On 2024/6/6 18:22, Jiqian Chen wrote:
>> In current code, when guest does S3, virtio-gpu are reset due to the
>> bit No_Soft_Reset is not set. After resetting, the display resources
>> of virtio-gpu are destroyed, then the display can't come ba
在 2024/6/25 21:56, Shiyang Ruan 写道:
在 2024/6/22 1:51, Dan Williams 写道:
Shiyang Ruan wrote:
Background:
Since CXL device is a memory device, while CPU consumes a poison page of
CXL device, it always triggers a MCE by interrupt (INT18), no matter
which-First path is configured. This is the
Add the return value check for kvm_virtio_pci_vector_use_one().
Since the return value of function virtio_pci_set_vector() is void,
we can do nothing here. So just add the error message here.
Signed-off-by: Cindy Lu
---
hw/virtio/virtio-pci.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion
The crash was reported in MAC OS and NixOS, here is the link for this bug
https://gitlab.com/qemu-project/qemu/-/issues/2334
https://gitlab.com/qemu-project/qemu/-/issues/2321
changelog v4 -> v3
- Address the comments in V3
- sperate the return check in kvm_virtio_pci_vector_use_one()
in diff
The crash was reported in MAC OS and NixOS, here is the link for this bug
https://gitlab.com/qemu-project/qemu/-/issues/2334
https://gitlab.com/qemu-project/qemu/-/issues/2321
The root cause is the function virtio_pci_set_guest_notifiers() was not called
in the virtio_input device.So the vector_ir
> -Original Message-
> From: qemu-devel-bounces+yaoxt.fnst=fujitsu@nongnu.org
> On Behalf Of
> Pierrick Bouvier
> Sent: Tuesday, July 2, 2024 9:10 AM
> To: qemu-devel@nongnu.org
> Cc: Eduardo Habkost ; Alex Bennée
> ; Pierrick Bouvier ;
> Paolo
> Bonzini ; Philippe Mathieu-Daudé ;
>
On 2024/7/1 23:10, Philippe Mathieu-Daudé wrote:
Hi Tiancheng, Zhiwei,
On 1/7/24 05:37, LIU Zhiwei wrote:
From: TANG Tiancheng
Ensure that riscv_cpu_sxl returns MXL_RV32 when runningRV32 in an
RV64 QEMU.
Signed-off-by: TANG Tiancheng
Fixes: 05e6ca5e156 ("target/riscv: Ignore reserved bits
A specific plugin test can now read and check a plugin output, to ensure
it contains expected values.
Signed-off-by: Pierrick Bouvier
---
tests/tcg/Makefile.target | 7 +++
1 file changed, 7 insertions(+)
diff --git a/tests/tcg/Makefile.target b/tests/tcg/Makefile.target
index dc5c8b7a3b4..
Only multiarch tests are run with plugins, and we want to be able to run
per-arch test with plugins too.
Signed-off-by: Pierrick Bouvier
---
tests/tcg/Makefile.target | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/tests/tcg/Makefile.target b/tests/tcg/Makefile.target
index
Add an explicit test to check expected memory values are read/written.
For sizes 8, 16, 32, 64 and 128, we generate a load/store operation.
For size 8 -> 64, we generate an atomic __sync_val_compare_and_swap too.
For 128bits memory access, we rely on SSE2 instructions.
By default, atomic accesses
This value can be accessed only during a memory callback, using
new qemu_plugin_mem_get_value function.
Returned value can be extended when QEMU will support accesses wider
than 128 bits.
Signed-off-by: Pierrick Bouvier
---
include/qemu/qemu-plugin.h | 32
plu
By using "print-accesses=true" option, mem plugin will now print every
value accessed, with associated size, type (store vs load), symbol,
instruction address and phys/virt address accessed.
Signed-off-by: Pierrick Bouvier
---
tests/plugin/mem.c | 69 +
Different code paths handle memory accesses:
- tcg generated code
- load/store helpers
- atomic helpers
This value is saved in cpu->plugin_state.
Atomic operations are doing read/write at the same time, so we generate
two memory callbacks instead of one, to allow plugins to access distinct
values
This series allows plugins to know which value is read/written during a memory
access.
For every memory access, we know copy this value before calling mem callbacks,
and those can query it using new API function:
- qemu_plugin_mem_get_value
Mem plugin was extended to print accesses, and a new tes
data was correctly copied, but size of array was not set
(g_array_sized_new only reserves memory, but does not set size).
As a result, callbacks were not called for code path relying on
plugin_register_vcpu_mem_cb().
Found when trying to trigger mem access callbacks for atomic
instructions.
Sign
Hi, all
When I did the cxl memory hot-plug test on QEMU, I accidentally connected
two memdev to the same downstream port, the command like below:
> -object memory-backend-ram,size=262144k,share=on,id=vmem0 \
> -object memory-backend-ram,size=262144k,share=on,id=vmem1 \
> -device pxb-cxl,bus_nr=1
From: Dongwon Kim
Enable hotkey for toggling window fullscreening for all individual
untabified VCs
Cc: Marc-André Lureau
Cc: Vivek Kasireddy
Signed-off-by: Dongwon Kim
---
ui/gtk.c | 39 +++
1 file changed, 35 insertions(+), 4 deletions(-)
diff --git a/u
On Fri, Jun 28, 2024, 7:28 AM Markus Armbruster wrote:
> When a command's arguments are specified as an explicit type T,
> generated documentation points to the members of T.
>
> Example:
>
> ##
> # @announce-self:
> #
> # Trigger generation of broadcast RARP frames to update netw
> what does "changed" mean here? changed compared to what?
For a split queue, if the shadow_avail_idx synced from avail ring idx
by *vring_avail_idx(vq) last time doesn't equal the current value of avail
ring idx.*
*vq->shadow_avail_idx **!= vring_avail_idx(vq);*
For packed queue, the logic is si
Ping - happy to merge this series myself but didn't wanna change iotests
without at least an ack from the lord of that castle.
On Wed, Jun 26, 2024, 7:22 PM John Snow wrote:
> Python 3.13 isn't out yet, but it's in beta and Fedora is ramping up to
> make it the default system interpreter for Fed
From: "Edgar E. Iglesias"
Bail out in qemu_ram_block_from_host() when
xen_ram_addr_from_mapcache() does not find an existing
mapping.
Signed-off-by: Edgar E. Iglesias
---
system/physmem.c | 4
1 file changed, 4 insertions(+)
diff --git a/system/physmem.c b/system/physmem.c
index 33d09f75
From: "Edgar E. Iglesias"
This fixes the unmapping of the first mapping in a bucket of a mapcache.
We also add error handling to qemu_ram_block_from_host() to bail out when
xen_ram_addr_from_mapcache() doesn't find an existing mapping.
Cheers,
Edgar
Edgar E. Iglesias (2):
physmem: Bail out q
From: "Edgar E. Iglesias"
This fixes the clobbering of the entry->next pointer when
unmapping the first entry in a bucket of a mapcache.
Fixes: 123acd816d ("xen: mapcache: Unmap first entries in buckets")
Reported-by: Anthony PERARD
Signed-off-by: Edgar E. Iglesias
---
hw/xen/xen-mapcache.c |
linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20240701
for you to fetch changes up to 58c782de557beb496bfb4c5ade721bbbd2480c72:
tests/qtest: Ensure STM32L4x5 EXTI state is correct at the end of QTests
(2024-07-01 15:4
On Mon, Jul 1, 2024 at 6:21 PM Anthony PERARD
wrote:
> On Mon, Jul 01, 2024 at 04:34:53PM +0200, Edgar E. Iglesias wrote:
> > On Mon, Jul 1, 2024 at 4:30 PM Edgar E. Iglesias <
> edgar.igles...@gmail.com>
> > wrote:
> > > On Mon, Jul 1, 2024 at 3:58 PM Edgar E. Iglesias <
> edgar.igles...@gmail.c
On 7/1/24 10:01 PM, Thomas Huth wrote:
The initial virtio-net-ccw devices currently do not have a proper parent
in the QOM tree, so they show up under /machine/unattached - which is
somewhat ugly. Let's attach them to /machine/virtual-css-bridge/virtual-css
instead.
Signed-off-by: Thomas Huth
On Mon, Jul 01, 2024 at 09:51:35AM -0700, Omar Sandoval wrote:
> Every other architecture does this, and debuggers need it to be able to
> identify which prstatus note corresponds to which CPU.
>
> Reviewed-by: Harsh Prateek Bora
Oops, I forgot to copy Thomas's reviewed-by from v1:
Reviewed-by:
Currently there is no mechanism guaranteeing
that it is safe to delete the object pointed
by opaque in timer_init.
This race condition happens if a timer is
created on a separate thread and timer_del
is called between qemu_mutex_unlock and
cb(opaque) in timerlist_run_timers.
In this case the user
On 7/1/24 10:48 AM, Eric Auger wrote:
The 2 first patches are fixes of
cf2647a76e ("virtio-iommu: Compute host reserved regions")
They can be taken separately of the rest.
Then the series uses the HostIOMMUDevice interface to fetch
information about the page size mask supported along the assigne
On Mon, Jul 01, 2024 at 10:48:52AM +0200, Eric Auger wrote:
> The 2 first patches are fixes of
> cf2647a76e ("virtio-iommu: Compute host reserved regions")
> They can be taken separately of the rest.
>
> Then the series uses the HostIOMMUDevice interface to fetch
> information about the page size
On 01/07/2024 13:58, Peter Maydell wrote:
On Sat, 29 Jun 2024 at 21:01, BALATON Zoltan wrote:
To avoid a warning about unfreed qemu_irq embed the i8259 irq in the
device state instead of allocating it.
Signed-off-by: BALATON Zoltan
---
hw/isa/vt82c686.c | 7 ---
1 file changed, 4 ins
On Thu, Jun 27, 2024 at 02:18:03PM +0200, Igor Mammedov wrote:
> On Tue, 25 Jun 2024 20:38:39 +0530
> Sunil V L wrote:
>
> > As per the step 5 in the process documented in bios-tables-test.c,
> > generate the expected ACPI AML data files for RISC-V using the
> > rebuild-expected-aml.sh script and
On Mon, Jul 01, 2024 at 08:42:39AM -0400, Raphael Norwitz wrote:
> I have no issues with these APIs, but I'm not a QMP expert so others
> should review those bits.
>
> For the vhost-user-blk code:
>
> Acked-by: Raphael Norwitz
Could the relevant bits get ack from qapi maintainers please?
> O
On Sun, Jun 30, 2024 at 01:43:48PM +, Mikhail Krasheninnikov wrote:
> Add a Virtio backend for SD/MMC devices. Confirmed interoperability with
> Linux.
>
> Signed-off-by: Mikhail Krasheninnikov
> CC: Matwey Kornilov
> CC: qemu-bl...@nongnu.org
> CC: Michael S. Tsirkin
> ---
> hw/virtio/Kco
On Tue, Jun 25, 2024 at 07:28:19PM +0800, Yuke Peng wrote:
> According to Intel VT-d specification 5.1.4, CFI must be blocked when
> Extended Interrupt Mode is enabled or Compatibility format interrupts
> are disabled.
>
> Signed-off-by: Yuke Peng
> ---
> hw/i386/intel_iommu.c | 28 +
On 7/1/24 10:19 PM, Philippe Mathieu-Daudé wrote:
On 1/7/24 18:54, Cédric Le Goater wrote:
On 7/1/24 6:40 PM, Philippe Mathieu-Daudé wrote:
On 28/6/24 09:44, Cédric Le Goater wrote:
On 6/28/24 9:00 AM, Philippe Mathieu-Daudé wrote:
All commands switching from TRANSFER state to (sending)DATA
d
On 30/06/2024 14:04, Zheyu Ma wrote:
This patch addresses a potential out-of-bounds memory access issue in the
tcx_blit_writel function. It adds bounds checking to ensure that memory
accesses do not exceed the allocated VRAM size. If an out-of-bounds access
is detected, an error is logged using
On Sun, Jun 23, 2024 at 06:23:30PM +0300, Dmitry Osipenko wrote:
> Hello,
>
> This series enables Vulkan Venus context support on virtio-gpu.
>
> All virglrender and almost all Linux kernel prerequisite changes
> needed by Venus are already in upstream. For kernel there is a pending
> KVM patchse
On Mon, Jul 01, 2024 at 02:48:58PM +0400, Marc-André Lureau wrote:
> Hi,
>
> All R-b now, it looks good to merge. Thanks for all the effort!
>
> Michael, are you taking it through your tree?
I could but did you intend to give your Reviewed-by?
> On Sun, Jun 23, 2024 at 7:23 PM Dmitry Osipenk
On Tue, Jun 18, 2024 at 08:29:59PM -0400, John Snow wrote:
> This series focuses primarily on converting our existing QAPI/QMP
> documentation to remove special "Note" and "Example" sections in favor
> of rST markup for the same.
>
> This is being done primarily to reduce the number of specially p
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