Re: [PATCH 1/3] hw/intc/loongson_ipi_common: Add loongson ipi common class

On 2024/7/3 下午2:16, Jiaxun Yang wrote: 在2024年7月3日七月 上午10:12，Bibo Mao写道： Loongson ipi common class and instance is created here, it comes from file loongson_ipi mostly. For the new added loongson ipi common class, there is four interfaces defined here: 1. Interfaces pre_save/post_load are

Re: [RFC PATCH 0/4] hw/display/virtio-gpu: Introducing asynchronous guest display render

Hi On Tue, Jul 2, 2024 at 10:11 PM Kim, Dongwon wrote: > Hi Marc-André, > > On 7/2/2024 3:29 AM, Marc-André Lureau wrote: > > Hi > > > > On Fri, Jun 21, 2024 at 3:20 AM > > wrote: > > > > From: Dongwon Kim dongwon@intel.com>> > > > > Introducing new vi

Re: [PATCH 1/3] hw/intc/loongson_ipi_common: Add loongson ipi common class

在2024年7月3日七月 上午10:12，Bibo Mao写道： > Loongson ipi common class and instance is created here, it comes > from file loongson_ipi mostly. For the new added loongson ipi > common class, there is four interfaces defined here: > 1. Interfaces pre_save/post_load are used for future kvm child class > 2.

Re: [PATCH v2 00/22] qga: clean up command source locations and conditionals

Hi Daniel On Tue, Jul 2, 2024 at 10:00 PM Daniel P. Berrangé wrote: > > Ping: for any review comments from QGA maintainers ? Maybe you could resend for patchew to correctly handle the series. thanks > > On Thu, Jun 13, 2024 at 04:01:05PM +0100, Daniel P. Berrangé wrote: > > This series is a si

Re: [PATCH v10 11/12] hw/pci: Convert rom_bar into OnOffAuto

On Wed, Jul 03, 2024 at 04:15:23AM +0200, BALATON Zoltan wrote: > On Tue, 2 Jul 2024, Michael S. Tsirkin wrote: > > On Thu, Jun 27, 2024 at 03:08:00PM +0900, Akihiko Odaki wrote: > > > rom_bar is tristate but was defined as uint32_t so convert it into > > > OnOffAuto. > > > > > > Signed-off-by: Ak

Re: [SPAM] [RFC PATCH v42 90/98] hw/sd/sdcard: Add experimental 'x-aspeed-emmc-kludge' property

On 7/3/24 7:10 AM, Andrew Jeffery wrote: On Tue, 2024-07-02 at 18:15 +0200, Philippe Mathieu-Daudé wrote: On 2/7/24 07:06, Andrew Jeffery wrote: On Fri, 2024-06-28 at 11:16 +0200, Cédric Le Goater wrote: On 6/28/24 9:02 AM, Philippe Mathieu-Daudé wrote: When booting U-boot/Linux on Aspeed boa

Re: [PATCH v7] virtio-net: Fix network stall at the host side waiting for kick

> This answer does not make sense from API POV. The core logic of function virtio_queue_set_notification_and_check() actually is a copy of function vhost_enable_notify() from vhost.c in kernel. > > > +bool virtio_queue_set_notification_and_check(VirtQueue *vq, int enable) > > > +{ > > > + uint16

Re: [PATCH 0/2] docs/python: bump minimum Sphinx version

John Snow writes: > On Tue, Jul 2, 2024 at 3:59 PM John Snow wrote: > >> With recent deprecations, we can advance our minimum sphinx version >> safely. This is heavily motivated by new qapidoc work which is much >> easier to maintain cross-version compatibility for - see difficulties in >> our d

Re: [SPAM] [RFC PATCH v42 90/98] hw/sd/sdcard: Add experimental 'x-aspeed-emmc-kludge' property

On Tue, 2024-07-02 at 18:15 +0200, Philippe Mathieu-Daudé wrote: > On 2/7/24 07:06, Andrew Jeffery wrote: > > On Fri, 2024-06-28 at 11:16 +0200, Cédric Le Goater wrote: > > > On 6/28/24 9:02 AM, Philippe Mathieu-Daudé wrote: > > > > When booting U-boot/Linux on Aspeed boards via eMMC, > > > > some

Re: [PULL 00/12] qtest, s390x, avocado and doc patches

On 7/2/24 03:32, Thomas Huth wrote: Hi Richard! The following changes since commit c80a339587fe4148292c260716482dd2f86d4476: Merge tag 'pull-target-arm-20240701' ofhttps://git.linaro.org/people/pmaydell/qemu-arm into staging (2024-07-01 10:41:45 -0700) are available in the Git reposito

[PATCH] README.rst: add the missing punctuations

Make the README more clearly. Signed-off-by: Zhihai Dong --- README.rst | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/README.rst b/README.rst index 21df79ef43..b120a1f69e 100644 --- a/README.rst +++ b/README.rst @@ -82,7 +82,7 @@ guidelines set out in the `style secti

[PATCH qemu] target/riscv: Add Zilsd and Zcmlsd extension support

From: lxx <1733205...@qq.com> This patch adds support for the Zilsd and Zcmlsd extension, which is documented at https://github.com/riscv/riscv-zilsd/releases/tag/v0.9.0 Co-developed-by: SUN Dongya Co-developed-by: LIU Xu Co-developed-by: ZHAO Fujin --- target/riscv/cpu.c

Re: [PATCH 4/6] target/riscv: Detect sxl to set bit width for RV32 in RV64

On 2024/7/3 10:33, Alistair Francis wrote: On Mon, Jul 1, 2024 at 1:41 PM LIU Zhiwei wrote: From: TANG Tiancheng Ensure correct bit width based on sxl when running RV32 on RV64 QEMU. This is required as MMU address translations run in S-mode. Signed-off-by: TANG Tiancheng Reviewed-by: Liu

Re: [PATCH 0/6] target/riscv: Expose RV32 cpu to RV64 QEMU

On Wed, Jul 3, 2024 at 12:25 AM Philippe Mathieu-Daudé wrote: > > Hi Zhiwei, > > On 1/7/24 05:37, LIU Zhiwei wrote: > > From: TANG Tiancheng > > > > This patch set aims to expose 32-bit RISC-V cpu to RV64 QEMU. Thus > > qemu-system-riscv64 can directly boot a RV32 Linux. > > > > This patch set ha

Re: [PATCH 4/6] target/riscv: Detect sxl to set bit width for RV32 in RV64

On Mon, Jul 1, 2024 at 1:41 PM LIU Zhiwei wrote: > > From: TANG Tiancheng > > Ensure correct bit width based on sxl when running RV32 on RV64 QEMU. > This is required as MMU address translations run in S-mode. > > Signed-off-by: TANG Tiancheng > Reviewed-by: Liu Zhiwei > --- > target/riscv/cpu

RE: [PATCH v4 5/7] tests/tcg: allow to check output of plugins

Tested-by: Xingtao Yao > -Original Message- > From: qemu-devel-bounces+yaoxt.fnst=fujitsu@nongnu.org > On Behalf Of > Pierrick Bouvier > Sent: Wednesday, July 3, 2024 2:45 AM > To: qemu-devel@nongnu.org > Cc: Alex Bennée ; Mahmoud Mandour > ; Pierrick Bouvier ; > Alexandre Iooss ; Ph

Re: [PATCH 2/6] target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32

On Mon, Jul 1, 2024 at 1:40 PM LIU Zhiwei wrote: > > From: TANG Tiancheng > > Ensure pmp_size is correctly determined using mxl for RV32 > in RV64 QEMU. > > Signed-off-by: TANG Tiancheng > Reviewed-by: Liu Zhiwei Reviewed-by: Alistair Francis Alistair > --- > target/riscv/pmp.c | 2 +- > 1

Re: [PATCH 1/6] target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI

On Mon, Jul 1, 2024 at 1:40 PM LIU Zhiwei wrote: > > From: TANG Tiancheng > > RV32 OpenSBI need a fw_dynamic_info parameter with 32-bit fields instead > of target_ulong. > > In RV64 QEMU, target_ulong is 64. So it is not right for booting RV32 OpenSBI. > We create a fw_dynmaic_info32 struct for t

RE: [PATCH v4 4/7] tests/tcg: add mechanism to run specific tests with plugins

Tested-by: Xingtao Yao > -Original Message- > From: qemu-devel-bounces+yaoxt.fnst=fujitsu@nongnu.org > On Behalf Of > Pierrick Bouvier > Sent: Wednesday, July 3, 2024 2:45 AM > To: qemu-devel@nongnu.org > Cc: Alex Bennée ; Mahmoud Mandour > ; Pierrick Bouvier ; > Alexandre Iooss ; Ph

Re: [PATCH] disas/riscv: Add decode for Zawrs extension

On Wed, Jun 26, 2024 at 7:43 PM Rob Bradford wrote: > > From: Balaji Ravikumar > > Add disassembly support for these instructions from Zawrs: > > * wrs.sto > * wrs.nto > > Signed-off-by: Balaji Ravikumar > Signed-off-by: Rob Bradford Thanks for the patch. Do you mind rebasing on https://github

Re: [PATCH v10 11/12] hw/pci: Convert rom_bar into OnOffAuto

On Tue, 2 Jul 2024, Michael S. Tsirkin wrote: On Thu, Jun 27, 2024 at 03:08:00PM +0900, Akihiko Odaki wrote: rom_bar is tristate but was defined as uint32_t so convert it into OnOffAuto. Signed-off-by: Akihiko Odaki Commit log should explain why this is an improvement, not just what's done.

Re: [PATCH] disas/riscv: Add decode for Zawrs extension

On Wed, Jun 26, 2024 at 7:43 PM Rob Bradford wrote: > > From: Balaji Ravikumar > > Add disassembly support for these instructions from Zawrs: > > * wrs.sto > * wrs.nto > > Signed-off-by: Balaji Ravikumar > Signed-off-by: Rob Bradford Acked-by: Alistair Francis Alistair > --- > disas/riscv.

[PATCH 2/3] hw/intc/loongarch_ipi: Add loongarch ipi support

Loongarch ipi is added here and ipi is emulated in userspace when running in kvm mode. It inherits from TYPE_LOONGSON_IPI_COMMON class, and two interfaces get_iocsr_as() and cpu_by_arch_id() is added for Loongarch 3A5000 machine. Signed-off-by: Bibo Mao --- hw/intc/loongarch_ipi.c | 80 +

[PATCH 3/3] hw/loongarch/virt: Replace loongson ipi with loongarch ipi

Loongarch ipi inherits from class LoongsonIPICommonClass, and it only contains Loongarch 3A5000 virt machine specific interfaces, rather than mix different machine implementations together. Signed-off-by: Bibo Mao --- hw/intc/Kconfig | 3 +++ hw/intc/meson.build | 1 + hw/loo

[PATCH 0/3] Replace loongson ipi with loongarch ipi

Here base class TYPE_LOONGSON_IPI_COMMON is added, it comes from loongson ipi mostly. And it defined four abstract interfaces which can be used for MIPS 3A4000 and Loongarch 3A5000 machine, also can be used for 3A5000 irqchip in kernel mode soon. Also Loongarch ipi is added here, it inherits from

[PATCH 1/3] hw/intc/loongson_ipi_common: Add loongson ipi common class

Loongson ipi common class and instance is created here, it comes from file loongson_ipi mostly. For the new added loongson ipi common class, there is four interfaces defined here: 1. Interfaces pre_save/post_load are used for future kvm child class 2. Interface get_iocsr_as can be used for differ

Re: [PATCH v3 00/11] target/riscv: Support zimop/zcmop/zama16b/zabha

On Wed, Jul 3, 2024 at 11:48 AM LIU Zhiwei wrote: > > All the patches in this patch set have been reviewed or acked. > > v2->v3: > 1. Add review tags. > 2. Reword the patch 10 in commit log > > v1->v2: > 1. Fix the isa orders. > 2. Make zimop/zcmop/zama16b/zabha depend on priviledg

Re: [PATCH v7 07/11] target/riscv: Save counter values during countinhibit update

On Thu, Jun 27, 2024 at 9:58 AM Atish Patra wrote: > > Currently, if a counter monitoring cycle/instret is stopped via > mcountinhibit we just update the state while the value is saved > during the next read. This is not accurate as the read may happen > many cycles after the counter is stopped. I

Re: [PATCH v7 03/11] target/riscv: Add cycle & instret privilege mode filtering properties

On Thu, Jun 27, 2024 at 9:59 AM Atish Patra wrote: > > From: Kaiwen Xue > > This adds the properties for ISA extension smcntrpmf. Patches > implementing it will follow. > > Signed-off-by: Atish Patra > Signed-off-by: Kaiwen Xue > --- > target/riscv/cpu.c | 2 ++ > target/riscv/cpu_cfg.h |

RE: [PATCH v4 6/7] tests/plugin/mem: add option to print memory accesses

Tested-by: Xingtao Yao one small suggestion: Keeping the addresses or values of fixed size in output message can improve the readability of logs. like: > +case QEMU_PLUGIN_MEM_VALUE_U8: > +g_string_append_printf(out, "0x%"PRIx8, value.data.u8); > +break; case QEMU_PLUGIN_MEM_

[PATCH v3 05/11] target/riscv: Support Zama16b extension

Zama16b is the property that misaligned load/stores/atomics within a naturally aligned 16-byte region are atomic. According to the specification, Zama16b applies only to AMOs, loads and stores defined in the base ISAs, and loads and stores of no more than XLEN bits defined in the F, D, and Q exten

[PATCH v3 11/11] disas/riscv: Support zabha disassemble

Signed-off-by: LIU Zhiwei Acked-by: Alistair Francis --- disas/riscv.c | 60 +++ 1 file changed, 60 insertions(+) diff --git a/disas/riscv.c b/disas/riscv.c index 2e315b4936..05b663ebfe 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -954,6 +954

[PATCH v3 10/11] target/riscv: Expose zabha extension as a cpu property

Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5219b44176..8cd52e6801 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -117,6 +117,7 @@ const RISCVIsaExt

[PATCH v3 09/11] target/riscv: Add amocas.[b|h] for Zabha

Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/insn32.decode | 2 ++ target/riscv/insn_trans/trans_rvzabha.c.inc | 14 ++ 2 files changed, 16 insertions(+) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 8a4801d4

[PATCH v3 08/11] target/riscv: Move gen_cmpxchg before adding amocas.[b|h]

Signed-off-by: LIU Zhiwei Acked-by: Alistair Francis --- target/riscv/insn_trans/trans_rvzacas.c.inc | 13 - target/riscv/translate.c| 13 + 2 files changed, 13 insertions(+), 13 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvzacas.c.inc b

[PATCH v3 07/11] target/riscv: Add AMO instructions for Zabha

Signed-off-by: LIU Zhiwei Acked-by: Alistair Francis --- target/riscv/cpu_cfg.h | 1 + target/riscv/insn32.decode | 20 +++ target/riscv/insn_trans/trans_rvzabha.c.inc | 131 target/riscv/translate.c| 4 +- 4 fil

[PATCH v3 06/11] target/riscv: Move gen_amo before implement Zabha

Signed-off-by: LIU Zhiwei Acked-by: Alistair Francis --- target/riscv/insn_trans/trans_rva.c.inc | 21 - target/riscv/translate.c| 21 + 2 files changed, 21 insertions(+), 21 deletions(-) diff --git a/target/riscv/insn_trans/trans_rva.c.in

[PATCH v3 04/11] disas/riscv: Support zcmop disassemble

Although in QEMU disassemble, we usually lift compressed instruction to an normal format when display the instruction name. For C.MOP.n, it is more reasonable to directly display its compressed name, because its behavior can be redefined by later extension. Signed-off-by: LIU Zhiwei Acked-by: Ali

[PATCH v3 03/11] target/riscv: Add zcmop extension

Zcmop defines eight 16-bit MOP instructions named C.MOP.n, where n is an odd integer between 1 and 15, inclusive. C.MOP.n is encoded in the reserved encoding space corresponding to C.LUI xn, 0. Unlike the MOPs defined in the Zimop extension, the C.MOP.n instructions are defined to not write any re

[PATCH v3 02/11] disas/riscv: Support zimop disassemble

Signed-off-by: LIU Zhiwei Acked-by: Alistair Francis Reviewed-by: Deepak Gupta --- disas/riscv.c | 100 ++ 1 file changed, 100 insertions(+) diff --git a/disas/riscv.c b/disas/riscv.c index 90d6b26de9..3ecbdcbe8d 100644 --- a/disas/riscv.c +++ b/

[PATCH v3 00/11] target/riscv: Support zimop/zcmop/zama16b/zabha

All the patches in this patch set have been reviewed or acked. v2->v3: 1. Add review tags. 2. Reword the patch 10 in commit log v1->v2: 1. Fix the isa orders. 2. Make zimop/zcmop/zama16b/zabha depend on priviledged 1.13 3. Add review tags. The v2 patch set is here https://mai

[PATCH v3 01/11] target/riscv: Add zimop extension

Zimop extension defines an encoding space for 40 MOPs.The Zimop extension defines 32 MOP instructions named MOP.R.n, where n is an integer between 0 and 31, inclusive. The Zimop extension additionally defines 8 MOP instructions named MOP.RR.n, where n is an integer between 0 and 7. These 40 MOPs i

Re: [PATCH] hw/display/sm501: Validate local memory size index in sm501_system_config_write

On Wed, 3 Jul 2024, Zheyu Ma wrote: In sm501_system_config_write(), we update the local memory size index based on the incoming value. However, there was no check to ensure that the index is within the valid range, which could result in a buffer overflow. This commit adds a check to ensure that

RE: [PATCH v4 7/7] tests/tcg/x86_64: add test for plugin memory access

> -Original Message- > From: qemu-devel-bounces+yaoxt.fnst=fujitsu@nongnu.org > On Behalf Of > Pierrick Bouvier > Sent: Wednesday, July 3, 2024 2:45 AM > To: qemu-devel@nongnu.org > Cc: Alex Bennée ; Mahmoud Mandour > ; Pierrick Bouvier ; > Alexandre Iooss ; Philippe Mathieu-Daudé >

Re: [PATCH v7 06/11] target/riscv: Implement privilege mode filtering for cycle/instret

On Thu, Jun 27, 2024 at 9:59 AM Atish Patra wrote: > > Privilege mode filtering can also be emulated for cycle/instret by > tracking host_ticks/icount during each privilege mode switch. This > patch implements that for both cycle/instret and mhpmcounters. The > first one requires Smcntrpmf while t

Re: [PATCH v7 05/11] target/riscv: Add cycle & instret privilege mode filtering support

On Thu, Jun 27, 2024 at 10:00 AM Atish Patra wrote: > > From: Kaiwen Xue > > QEMU only calculates dummy cycles and instructions, so there is no > actual means to stop the icount in QEMU. Hence this patch merely adds > the functionality of accessing the cfg registers, and cause no actual > effects

Re: [PATCH v7 04/11] target/riscv: Add cycle & instret privilege mode filtering definitions

On Thu, Jun 27, 2024 at 9:58 AM Atish Patra wrote: > > From: Kaiwen Xue > > This adds the definitions for ISA extension smcntrpmf. > > Signed-off-by: Kaiwen Xue > Reviewed-by: Daniel Henrique Barboza > Signed-off-by: Atish Patra Reviewed-by: Alistair Francis Alistair > --- > target/riscv/

Re: [PATCH v7 01/11] target/riscv: Combine set_mode and set_virt functions.

On Thu, Jun 27, 2024 at 10:02 AM Atish Patra wrote: > > From: Rajnesh Kanwal > > Combining riscv_cpu_set_virt_enabled() and riscv_cpu_set_mode() > functions. This is to make complete mode change information > available through a single function. > > This allows to easily differentiate between HS-

Re: [PATCH v2 10/11] target/riscv: Enable zabha for max cpu

On Sun, Jun 30, 2024 at 1:13 PM LIU Zhiwei wrote: > > Signed-off-by: LIU Zhiwei This isn't really max CPU specific, it's just exposing the extension. Do you mind updating the title? Otherwise Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu.c | 2 ++ > 1 file changed, 2 inse

RE: [PATCH] hw/nvme: Fix memory leak in nvme_dsm

> -Original Message- > From: qemu-devel-bounces+yaoxt.fnst=fujitsu@nongnu.org > On Behalf Of Zheyu > Ma > Sent: Wednesday, July 3, 2024 7:13 AM > To: Keith Busch ; Klaus Jensen ; Jesper > Devantier > Cc: Zheyu Ma ; qemu-bl...@nongnu.org; > qemu-devel@nongnu.org > Subject: [PATCH] h

Re: [PATCH v2 05/11] target/riscv: Support Zama16b extension

On Sun, Jun 30, 2024 at 1:11 PM LIU Zhiwei wrote: > > Zama16b is the property that misaligned load/stores/atomics within > a naturally aligned 16-byte region are atomic. > > According to the specification, Zama16b applies only to AMOs, loads > and stores defined in the base ISAs, and loads and sto

Re: [PATCH 2/2] hw/isa/vt82c686.c: Embed i8259 irq in device state instead of allocating

On Tue, 2 Jul 2024, Bernhard Beschow wrote: Am 2. Juli 2024 18:42:23 UTC schrieb Bernhard Beschow : Am 1. Juli 2024 12:58:15 UTC schrieb Peter Maydell : On Sat, 29 Jun 2024 at 21:01, BALATON Zoltan wrote: To avoid a warning about unfreed qemu_irq embed the i8259 irq in the device state inste

Re: [PATCH 3/3] util/cpuinfo-riscv: Use linux __riscv_hwprobe syscall

On Fri, Jun 28, 2024 at 4:06 AM Richard Henderson wrote: > > With recent linux kernels, there is a syscall to probe for various > ISA extensions. These bits were phased in over several kernel > releases, so we still require checks for symbol availability. > > Signed-off-by: Richard Henderson Ac

Re: [PATCH 2/3] util/cpuinfo-riscv: Support OpenBSD signal frame

On Fri, Jun 28, 2024 at 4:06 AM Richard Henderson wrote: > > Reported-by: Brad Smith > Signed-off-by: Richard Henderson Acked-by: Alistair Francis Alistair > --- > util/cpuinfo-riscv.c | 7 +++ > 1 file changed, 7 insertions(+) > > diff --git a/util/cpuinfo-riscv.c b/util/cpuinfo-riscv.

Re: [PATCH 1/3] util/cpuinfo-riscv: Support host/cpuinfo.h for riscv

On Fri, Jun 28, 2024 at 4:06 AM Richard Henderson wrote: > > Move detection code out of tcg, similar to other hosts. > > Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Alistair > --- > host/include/riscv/host/cpuinfo.h | 23 + > tcg/riscv/tcg-target.h| 46

[PATCH 0/4] target/ppc: Cleanups for dcbz

Hi Zoltan, These are the sorts of cleanups that I was talking about re the dcbz helpers. This makes only a small difference to an artifical memset benchmark. However, see 20240702234155.2106399-1-richard.hender...@linaro.org [PATCH 0/2] target/arm: Fix unwind from dc zva and FEAT_MOPS and

[PATCH 4/4] target/ppc: Merge helper_{dcbz,dcbzep}

Merge the two and pass the mmu_idx directly from translation. Swap the argument order in dcbz_common to avoid extra swaps. Signed-off-by: Richard Henderson --- target/ppc/helper.h | 3 +-- target/ppc/mem_helper.c | 14 -- target/ppc/translate.c | 4 ++-- 3 files changed, 7 ins

[PATCH 1/4] target/ppc/mem_helper.c: Remove a conditional from dcbz_common()

From: BALATON Zoltan Instead of passing a bool and select a value within dcbz_common() let the callers pass in the right value to avoid this conditional statement. On PPC dcbz is often used to zero memory and some code uses it a lot. This change improves the run time of a test case that copies me

[PATCH 3/4] target/ppc: Split out helper_dbczl for 970

We can determine at translation time whether the insn is or is not dbczl. We must retain a runtime check against the HID5 register, but we can move that to a separate function that never affects other ppc models. Signed-off-by: Richard Henderson --- target/ppc/helper.h | 7 +-- target/

[PATCH 2/4] target/ppc: Hoist dcbz_size out of dcbz_common

The 970 logic does not apply to dcbzep, which is an e500 insn. Signed-off-by: Richard Henderson --- target/ppc/mem_helper.c | 30 +++--- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index 361fd72226..506

[PATCH 0/2] target/arm: Fix unwind from dc zva and FEAT_MOPS

While looking into Zoltan's attempt to speed up ppc64 DCBZ (data cache block set to zero), I wondered what AArch64 was doing differently. It turned out that Arm is the only user of tlb_vaddr_to_host. None of the code sequences in use between AArch64, Power64 and S390X are 100% safe, with race con

[PATCH 1/2] accel/tcg: Introduce memset_ra, memmove_ra

Add wrappers that set and clear helper_retaddr around the host memory operation. This cannot fail for system mode, but might raise SIGSEGV for user mode. Signed-off-by: Richard Henderson --- include/exec/cpu_ldst.h | 40 accel/tcg/user-exec.c | 22

[PATCH 2/2] target/arm: Use memset_ra, memmove_ra in helper-a64.c

Without this, qemu user will not unwind from the SIGSEGV properly and die with qemu-aarch64: QEMU internal SIGSEGV {code=ACCERR, addr=0x7d1b36ec2000} Segmentation fault Fill in the test case for ppc and s390x, which also use memset from within a helper (but don't currently crash fwiw). Signe

[PATCH] hw/nvme: Fix memory leak in nvme_dsm

The allocated memory to hold LBA ranges leaks in the nvme_dsm function. This happens because the allocated memory for iocb->range is not freed in all error handling paths. Fix this by adding a free to ensure that the allocated memory is properly freed. ASAN log: ==3075137==ERROR: LeakSanitizer: d

Re: [PATCH 3/3] util/cpuinfo-riscv: Use linux __riscv_hwprobe syscall

On 7/2/24 15:15, Daniel Henrique Barboza wrote: On 6/27/24 3:03 PM, Richard Henderson wrote: With recent linux kernels, there is a syscall to probe for various ISA extensions.  These bits were phased in over several kernel releases, so we still require checks for symbol availability. Signed-o

Re: [PATCH 1/3] util/cpuinfo-riscv: Support host/cpuinfo.h for riscv

On 7/2/24 12:55, Philippe Mathieu-Daudé wrote: On 27/6/24 20:03, Richard Henderson wrote: ... +    info |= !got_sigill * CPUINFO_ZBA; A bit too optimized to my taste, 'if (sigill) info|=ZBA' would be simpler to follow. I switched to "info |= got_sigill ? 0 : CPUINFO_ZBA". Otherwi

Re: [PULL 0/6] aspeed queue

ository at: https://github.com/legoater/qemu/ tags/pull-aspeed-20240702 for you to fetch changes up to 5b0961f7ad6790f473623703834351b6e43fbaa6: hw/net:ftgmac100: fix coding style (2024-07-02 07:53:53 +0200) aspeed queue:

Re: [PULL 00/67] SD/MMC patches for 2024-07-02

repository at: https://github.com/philmd/qemu.git tags/sdmmc-20240702 for you to fetch changes up to 8442e1625ba6723bee2c6d0fdb7207a3e27a2b05: hw/sd/sdcard: Add sd_acmd_SEND_SCR handler (ACMD51) (2024-07-02 10:08:32 +0200) Checkpatch warnings ignored: WARNING: added, moved or dele

Re: [PATCH v2 00/11] target/riscv: Support zimop/zcmop/zama16b/zabha

Hi LIU, On Sun, Jun 30, 2024 at 11:05:48AM +0800, LIU Zhiwei wrote: We have sent their implementations separately, and we have received few objective comments except for some ISA extensions order. So, I have put them together as one patch set to make it easier for merging. v1->v2: 1. Fix th

[PATCH] hw/display/sm501: Validate local memory size index in sm501_system_config_write

In sm501_system_config_write(), we update the local memory size index based on the incoming value. However, there was no check to ensure that the index is within the valid range, which could result in a buffer overflow. This commit adds a check to ensure that the local memory size index is within

Re: [PATCH 1/3] util/cpuinfo-riscv: Support host/cpuinfo.h for riscv

On 6/27/24 3:03 PM, Richard Henderson wrote: Move detection code out of tcg, similar to other hosts. Signed-off-by: Richard Henderson --- Reviewed-by: Daniel Henrique Barboza host/include/riscv/host/cpuinfo.h | 23 + tcg/riscv/tcg-target.h| 46 -

Re: [PATCH 2/3] util/cpuinfo-riscv: Support OpenBSD signal frame

On 6/27/24 3:03 PM, Richard Henderson wrote: Reported-by: Brad Smith Signed-off-by: Richard Henderson --- Acked-by: Daniel Henrique Barboza util/cpuinfo-riscv.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/util/cpuinfo-riscv.c b/util/cpuinfo-riscv.c index 6b97100620..ab

Re: [PATCH 3/3] util/cpuinfo-riscv: Use linux __riscv_hwprobe syscall

On 6/27/24 3:03 PM, Richard Henderson wrote: With recent linux kernels, there is a syscall to probe for various ISA extensions. These bits were phased in over several kernel releases, so we still require checks for symbol availability. Signed-off-by: Richard Henderson --- meson.build

[PATCH v1 1/1] target/i386: Delete a duplicated macro definition CR4_FRED_MASK

Macro CR4_FRED_MASK is defined twice due to a merge incident, delete one. Signed-off-by: Xin Li (Intel) --- target/i386/cpu.h | 6 -- 1 file changed, 6 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 29daf37048..b73685a745 100644 --- a/target/i386/cpu.h +++ b/target/i3

Re: [PATCH] hw/virtio/virtio-crypto: Fix op_code assignment in virtio_crypto_create_asym_session

On Tue, Jul 2, 2024 at 11:05 PM Michael S. Tsirkin wrote: > On Tue, Jul 02, 2024 at 11:04:43PM +0200, Zheyu Ma wrote: > > The assignment of the op_code in the virtio_crypto_create_asym_session > > function was moved before its usage to ensure it is correctly set. > > Previously, if the function f

[PATCH v3] hw/virtio/virtio-crypto: Fix op_code assignment in virtio_crypto_create_asym_session

Currently, if the function fails during the key_len check, the op_code does not have a proper value, causing virtio_crypto_free_create_session_req not to free the memory correctly, leading to a memory leak. By setting the op_code before performing any checks, we ensure that virtio_crypto_free_crea

Re: [PATCH 2/2] hw/isa/vt82c686.c: Embed i8259 irq in device state instead of allocating

Am 2. Juli 2024 18:42:23 UTC schrieb Bernhard Beschow : > > >Am 1. Juli 2024 12:58:15 UTC schrieb Peter Maydell : >>On Sat, 29 Jun 2024 at 21:01, BALATON Zoltan wrote: >>> >>> To avoid a warning about unfreed qemu_irq embed the i8259 irq in the >>> device state instead of allocating it. >>> >>>

Re: [PATCH v2] hw/virtio/virtio-crypto: Fix op_code assignment in virtio_crypto_create_asym_session

On Tue, Jul 02, 2024 at 11:05:19PM +0200, Zheyu Ma wrote: > The assignment of the op_code in the virtio_crypto_create_asym_session > function was moved before its usage to ensure it is correctly set. > Previously, if the function failed during the key_len check, the op_code > did not have a prop

Re: [PATCH] hw/virtio/virtio-crypto: Fix op_code assignment in virtio_crypto_create_asym_session

On Tue, Jul 02, 2024 at 11:04:43PM +0200, Zheyu Ma wrote: > The assignment of the op_code in the virtio_crypto_create_asym_session > function was moved before its usage to ensure it is correctly set. > Previously, if the function failed during the key_len check, the op_code > did not have a proper

Re: [PATCH] hw/virtio/virtio-crypto: Fix op_code assignment in virtio_crypto_create_asym_session

On Tue, Jul 02, 2024 at 11:02:27PM +0200, Zheyu Ma wrote: > The assignment of the op_code in the virtio_crypto_create_asym_session > function was moved before its usage to ensure it is correctly set. > Previously, if the function failed during the key_len check, the op_code when you say Previously

[PATCH v2] hw/virtio/virtio-crypto: Fix op_code assignment in virtio_crypto_create_asym_session

The assignment of the op_code in the virtio_crypto_create_asym_session function was moved before its usage to ensure it is correctly set. Previously, if the function failed during the key_len check, the op_code did not have a proper value, causing virtio_crypto_free_create_session_req to not free t

[PATCH] hw/virtio/virtio-crypto: Fix op_code assignment in virtio_crypto_create_asym_session

The assignment of the op_code in the virtio_crypto_create_asym_session function was moved before its usage to ensure it is correctly set. Previously, if the function failed during the key_len check, the op_code did not have a proper value, causing virtio_crypto_free_create_session_req to not free t

[PATCH] hw/virtio/virtio-crypto: Fix op_code assignment in virtio_crypto_create_asym_session

The assignment of the op_code in the virtio_crypto_create_asym_session function was moved before its usage to ensure it is correctly set. Previously, if the function failed during the key_len check, the op_code did not have a proper value, causing virtio_crypto_free_create_session_req to not free t

[PATCH 1/2] ui/egl-helpers: Consolidate create-sync and create-fence

From: Dongwon Kim There is no reason to split those two operations so combining two functions - egl_dmabuf_create_sync and egl_dmabuf_create_fence. v2: egl_dmabuf_create_fence -> egl_dmabuf_create_fence_fd (Marc-André Lureau ) Cc: Gerd Hoffmann Cc: Marc-André Lureau Cc: Vivek Kasireddy S

[PATCH 0/2] Consolidate create-sync and create-fence

From: Dongwon Kim Sync object itself is never used as is so can be removed from QemuDmaBuf struct. So now sync is only temporarily needed when creating fence for the object which means what was done in egl_dmabuf_create_sync can now be a part of egl_dmabuf_create_fence function. And egl_dmabuf_cr

[PATCH 2/2] ui/dmabuf: Remove 'sync' from QemuDmaBuf struct

From: Dongwon Kim Sync object is not used so removing it from QemuDmaBuf struct Cc: Gerd Hoffmann Cc: Marc-André Lureau Cc: Vivek Kasireddy Signed-off-by: Dongwon Kim --- include/ui/dmabuf.h | 2 -- ui/dmabuf.c | 14 -- 2 files changed, 16 deletions(-) diff --git a/inc

[PULL v2 60/88] hw/arm/virt-acpi-build: Drop local iort_node_offset

From: Nicolin Chen Both the other two callers of build_iort_id_mapping() just directly pass in the IORT_NODE_OFFSET macro. Keeping a "const uint32_t" local variable storing the same value doesn't have any gain. Simplify this by replacing the only place using this local variable with the macro di

[PULL v2 24/88] hw/mem/cxl_type3: Add DC extent list representative and get DC extent list mailbox support

From: Fan Ni Add dynamic capacity extent list representative to the definition of CXLType3Dev and implement get DC extent list mailbox command per CXL.spec.3.1:.8.2.9.9.9.2. Tested-by: Svetly Todorov Reviewed-by: Jonathan Cameron Signed-off-by: Fan Ni Message-Id: <20240523174651.1089554-10-ni

[PULL v2 38/88] hw/cxl: Fix read from bogus memory

From: Ira Weiny Peter and coverity report: We've passed '&data' to address_space_write(), which means "read from the address on the stack where the function argument 'data' lives", so instead of writing 64 bytes of data to the guest , we'll write 64 bytes which st

[PULL v2 09/88] Fix vhost user assertion when sending more than one fd

From: Christian Pötzsch If the client sends more than one region this assert triggers. The reason is that two fd's are 8 bytes and VHOST_MEMORY_BASELINE_NREGIONS is exactly 8. The assert is wrong because it should not test for the size of the fd array, but for the numbers of regions. Signed-off

[PULL v2 70/88] tests/data/acpi: Move x86 ACPI tables under x86/${machine} path

From: Sunil V L To support multiple architectures using same machine name, create x86 folder and move all x86 related AML files for each machine type inside. Signed-off-by: Sunil V L Reviewed-by: Igor Mammedov Message-Id: <20240625150839.1358279-10-suni...@ventanamicro.com> Reviewed-by: Michae

[PULL v2 87/88] pcie_sriov: Register VFs after migration

From: Akihiko Odaki pcie_sriov doesn't have code to restore its state after migration, but igb, which uses pcie_sriov, naively claimed its migration capability. Add code to register VFs after migration and fix igb migration. Fixes: 3a977deebe6b ("Intrdocue igb device emulation") Signed-off-by:

[PULL v2 80/88] hw/ppc/spapr_pci: Do not create DT for disabled PCI device

From: Akihiko Odaki Disabled means it is a disabled SR-IOV VF or it is powered off, and hidden from the guest. Signed-off-by: Akihiko Odaki Message-Id: <20240627-reuse-v10-2-7ca0b8ed3...@daynix.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/ppc/spapr_pci.c | 4

[PULL v2 14/88] Revert "vhost-user: fix lost reconnect"

From: Li Feng This reverts commit f02a4b8e6431598612466f76aac64ab492849abf. Since the current patch cannot completely fix the lost reconnect problem, there is a scenario that is not considered: - When the virtio-blk driver is removed from the guest os, s->connected has no chance to be set to f

[PULL v2 63/88] uefi-test-tools/UefiTestToolsPkg: Add RISC-V support

From: Sunil V L Enable building the test application for RISC-V with appropriate dependencies updated. Signed-off-by: Sunil V L Acked-by: Gerd Hoffmann Acked-by: Alistair Francis Acked-by: Igor Mammedov Message-Id: <20240625150839.1358279-3-suni...@ventanamicro.com> Reviewed-by: Michael S. T

[PULL v2 69/88] tests/qtest/bios-tables-test.c: Set "arch" for x86 tests

From: Sunil V L To search for expected AML files under ${arch}/${machine} path, set this field for X86 related test cases. Signed-off-by: Sunil V L Reviewed-by: Igor Mammedov Message-Id: <20240625150839.1358279-9-suni...@ventanamicro.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael

[PULL v2 05/88] virtio: Prevent creation of device using notification-data with ioeventfd

From: Jonah Palmer Prevent the realization of a virtio device that attempts to use the VIRTIO_F_NOTIFICATION_DATA transport feature without disabling ioeventfd. Due to ioeventfd not being able to carry the extra data associated with this feature, having both enabled is a functional mismatch and

[PULL v2 26/88] hw/cxl/events: Add qmp interfaces to add/release dynamic capacity extents

From: Fan Ni To simulate FM functionalities for initiating Dynamic Capacity Add (Opcode 5604h) and Dynamic Capacity Release (Opcode 5605h) as in CXL spec r3.1 7.6.7.6.5 and 7.6.7.6.6, we implemented two QMP interfaces to issue add/release dynamic capacity extents requests. With the change, we al

[PULL v2 36/88] Revert "docs/specs/pvpanic: mark shutdown event as not implemented"

From: Thomas Weißschuh The missing functionality has been implemented now. This reverts commit e739d1935c461d0668057e9dbba9d06f728d29ec. Signed-off-by: Thomas Weißschuh Message-Id: <20240527-pvpanic-shutdown-v8-8-5a28ec025...@t-8ch.de> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S.

[PULL v2 86/88] pcie_sriov: Remove num_vfs from PCIESriovPF

From: Akihiko Odaki num_vfs is not migrated so use PCI_SRIOV_CTRL_VFE and PCI_SRIOV_NUM_VF instead. Signed-off-by: Akihiko Odaki Message-Id: <20240627-reuse-v10-8-7ca0b8ed3...@daynix.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- include/hw/pci/pcie_sriov.h | 1 -

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