On 2024/7/5 13:13, CLEMENT MATHIEU--DRIF wrote:
On 05/07/2024 05:03, Yi Liu wrote:
Caution: External email. Do not open attachments or click links,
unless this email comes from a known sender and you know the content
is safe.
On 2024/5/30 20:24, CLEMENT MATHIEU--DRIF wrote:
This series belon
On 7/5/24 5:41 AM, Andrew Jeffery wrote:
On Thu, 2024-07-04 at 07:36 +0200, Cédric Le Goater wrote:
From: Cédric Le Goater
When the boot-from-eMMC HW strapping bit is set, use the 'boot-config'
property to set the boot config register to boot from the first boot
area partition of the eMMC devi
On 7/5/24 5:36 AM, Andrew Jeffery wrote:
On Thu, 2024-07-04 at 07:36 +0200, Cédric Le Goater wrote:
From: Cédric Le Goater
Bit SCU500[2] of the AST2600 controls the boot device of the SoC.
Future changes will configure this bit to boot from eMMC disk images
specially built for this purpose.
Update meson-buildoptions.sh to stay in sync with meson_options.txt.
Signed-off-by: Zhao Liu
---
scripts/meson-buildoptions.sh | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/scripts/meson-buildoptions.sh b/scripts/meson-buildoptions.sh
index cfadb5ea86af..c970
On 05/07/2024 05:03, Yi Liu wrote:
> Caution: External email. Do not open attachments or click links,
> unless this email comes from a known sender and you know the content
> is safe.
>
>
> On 2024/5/30 20:24, CLEMENT MATHIEU--DRIF wrote:
>> This series belongs to a list of series that add SVM sup
On Fri, Jul 05, 2024 at 02:40:19PM +1000, Nicholas Piggin wrote:
> On Fri Jul 5, 2024 at 11:41 AM AEST, David Gibson wrote:
> > On Fri, Jul 05, 2024 at 11:18:47AM +1000, Nicholas Piggin wrote:
> > > On Thu Jul 4, 2024 at 10:15 PM AEST, Peter Maydell wrote:
> > > > On Sat, 29 Jun 2024 at 04:17, Davi
From: Clément Mathieu--Drif
VTDIOTLBPageInvInfo.mask might not fit in an uint8_t.
Moreover, this field is used in binary operations with 64-bit addresses.
Signed-off-by: Clément Mathieu--Drif
---
hw/i386/intel_iommu_internal.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a
From: Clément Mathieu--Drif
Various fixes for VT-d
This series contains fixes that will be necessary
when adding in-guest (fully emulated) SVM support.
v3
FRCD construction macro :
- Longer sha1 for the 'Fixes' tag
- Add '.' at the end of the sentence
Make types mat
From: Clément Mathieu--Drif
The constant must be unsigned, otherwise the two's complement
overrides the other fields when a PASID is present.
Fixes: 1b2b12376c8a ("intel-iommu: PASID support")
Signed-off-by: Clément Mathieu--Drif
Reviewed-by: Yi Liu
---
hw/i386/intel_iommu_internal.h | 2 +-
From: Clément Mathieu--Drif
The 'level' field in vtd_iotlb_key is an unsigned integer.
We don't need to store level as an int in vtd_lookup_iotlb.
Signed-off-by: Clément Mathieu--Drif
---
hw/i386/intel_iommu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/i386/intel_io
On Fri, Jul 05, 2024 at 02:21:35AM +, Yang Dongshan wrote:
> > virtqueue_get_avail_bytes would always return the opaque.
> Then the condition will change from:
>
> static int virtio_net_has_buffers(VirtIONetQueue *q, int bufsize)
> {
> if (virtio_queue_empty(q->rx_vq) ||
> (n->
On Fri Jul 5, 2024 at 11:41 AM AEST, David Gibson wrote:
> On Fri, Jul 05, 2024 at 11:18:47AM +1000, Nicholas Piggin wrote:
> > On Thu Jul 4, 2024 at 10:15 PM AEST, Peter Maydell wrote:
> > > On Sat, 29 Jun 2024 at 04:17, David Gibson
> > > wrote:
> > > >
> > > > On Fri, Jun 28, 2024 at 04:20:02P
On Thu, 2024-07-04 at 07:36 +0200, Cédric Le Goater wrote:
> From: Cédric Le Goater
>
> Hello,
>
> This series enables boot from eMMC on the rainier-bmc machine, which
> is the default behavior and also on the AST2600 EVB using a machine
> option to change the default.
>
> It depends solely on
On Thu, 2024-07-04 at 07:36 +0200, Cédric Le Goater wrote:
> From: Cédric Le Goater
>
> The default behavior of some Aspeed machines is to boot from the eMMC
> device, like the rainier-bmc. Others like ast2600-evb could also boot
> from eMMC if the HW strapping boot-from-eMMC bit was set. Add a
>
On Thu, 2024-07-04 at 07:36 +0200, Cédric Le Goater wrote:
> From: Cédric Le Goater
>
> To change default behavior of a machine and boot from eMMC, future
> changes will add a machine option to let the user configure the
> boot-from-eMMC HW strapping bit. Add a new machine attribute first.
>
> S
On Thu, 2024-07-04 at 07:36 +0200, Cédric Le Goater wrote:
> From: Cédric Le Goater
>
> This value is taken from a running Rainier machine.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: Andrew Jeffery
On Thu, 2024-07-04 at 07:36 +0200, Cédric Le Goater wrote:
> From: Cédric Le Goater
>
> When the boot-from-eMMC HW strapping bit is set, use the 'boot-config'
> property to set the boot config register to boot from the first boot
> area partition of the eMMC device.
>
> Signed-off-by: Cédric Le
On Thu, 2024-07-04 at 07:36 +0200, Cédric Le Goater wrote:
> From: Cédric Le Goater
>
> Report support on the AST2600 SoC if the boot-from-eMMC HW strapping
> bit is set at the board level. AST2700 also has support but it is not
> yet ready in QEMU and others SoCs do not have support, so return f
On Thu, 2024-07-04 at 07:36 +0200, Cédric Le Goater wrote:
> From: Cédric Le Goater
>
> Bit SCU500[2] of the AST2600 controls the boot device of the SoC.
>
> Future changes will configure this bit to boot from eMMC disk images
> specially built for this purpose.
>
> Signed-off-by: Joel Stanley
This is a ping to the patch below.
https://lore.kernel.org/qemu-devel/ty0pr0101mb42850337f8917d1f514107fba4...@ty0pr0101mb4285.apcprd01.prod.exchangelabs.com/
差出人: TaiseiIto
送信日時: 2024年6月25日 21:03
宛先: qemu-devel@nongnu.org
CC: pbonz...@redhat.com ; m...@redhat.co
On Thu, 2024-07-04 at 07:36 +0200, Cédric Le Goater wrote:
> From: Cédric Le Goater
>
> The first boot area partition (64K) of the eMMC device should contain
> an initial boot loader (u-boot SPL). Load it as a ROM only if an eMMC
> device is available to boot from but no flash device is.
>
> Sig
On Thu, 2024-07-04 at 07:36 +0200, Cédric Le Goater wrote:
> From: Cédric Le Goater
>
> The QEMU device representing the eMMC device of machine is currently
> created with type SD_CARD. Change the type to EMMC now that it is
> available.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: Andrew
On 2024/7/4 23:12, CLEMENT MATHIEU--DRIF wrote:
From: Clément Mathieu--Drif
The constant must be unsigned, otherwise the two's complement
overrides the other fields when a PASID is present
I'm not native speaker. But it's better to see a "." in the end
of the sentence. :)
Fixes: 1b2b12376c
On 2024/5/30 20:24, CLEMENT MATHIEU--DRIF wrote:
This series belongs to a list of series that add SVM support for VT-d.
Here we focus on the implementation of PRI support in the IOMMU and on a
PCI-level
API for PRI to be used by virtual devices.
This work is based on the VT-d specification ver
On 2024/7/4 23:12, CLEMENT MATHIEU--DRIF wrote:
From: Clément Mathieu--Drif
wait_desc with SW=0,IF=0,FN=1 must not be considered as an
invalid descriptor as it is used to implement section 7.10 of
the VT-d spec
After a second thinking. t would be better to move this patch to the
PRI series [1
On 2024/7/5 06:13, Michael S. Tsirkin wrote:
On Thu, Jul 04, 2024 at 03:12:48PM +, CLEMENT MATHIEU--DRIF wrote:
From: Clément Mathieu--Drif
The 'level' field in vtd_iotlb_key is an unsigned integer.
We don't need to store level as an int in vtd_lookup_iotlb.
VTDIOTLBPageInvInfo.mask is us
On 04/07/2024 17:34, Zhao Liu wrote:
> From: Zhao Liu
>
> Guest crashes (Segmentation fault) when getting cxl-fmw property via
> qmp:
>
IMO, it's fair to say "Guest crashes" which generally means the guest kernel
panic etc.
I'd prefer the subject like:
hw/cxl/cxl-host: Fix segmentation fault
We set the value of register CSR_PRCFG3, but left out CSR_PRCFG1
and CSR_PRCFG2. Set CSR_PRCFG1 and CSR_PRCFG2 according to the
default values of the physical machine.
Signed-off-by: Song Gao
---
v2:
- Add a new patch fix set CSR_CRMD wrong value;
- Set PRCFG1-PRCFG3 values in loongarch_la464_i
After cpu_reset, DATF in CSR_CRMD is 0, DATM is 0.
See the manual[1] 6.4.
[1]:
https://github.com/loongson/LoongArch-Documentation/releases/download/2023.04.20/LoongArch-Vol1-v1.10-EN.pdf
Signed-off-by: Song Gao
---
target/loongarch/cpu.c | 6 +++---
1 file changed, 3 insertions(+), 3 deleti
On 05/07/2024 10:15, Zhao Liu wrote:
>> There is a new user for cfmw_list now
>> https://lore.kernel.org/qemu-devel/20240704093404.1848132-1-zhao1@linux.intel.com/
>>
>> So I think we should drop this patch.
> Hi Zhijian,
>
> I'm not a "real" user and that bug was originally found by code r
> virtqueue_get_avail_bytes would always return the opaque.
Then the condition will change from:
static int virtio_net_has_buffers(VirtIONetQueue *q, int bufsize)
{
if (virtio_queue_empty(q->rx_vq) ||
(n->mergeable_rx_bufs &&
!virtqueue_avail_bytes(q->rx_vq, bufsize, 0))
On Fri, Jul 05, 2024 at 11:18:47AM +1000, Nicholas Piggin wrote:
> On Thu Jul 4, 2024 at 10:15 PM AEST, Peter Maydell wrote:
> > On Sat, 29 Jun 2024 at 04:17, David Gibson
> > wrote:
> > >
> > > On Fri, Jun 28, 2024 at 04:20:02PM +0100, Peter Maydell wrote:
> > > > On Thu, 27 Jun 2024 at 14:39, A
On Thu, Jul 04, 2024 at 01:15:57PM +0100, Peter Maydell wrote:
> On Sat, 29 Jun 2024 at 04:17, David Gibson
> wrote:
> >
> > On Fri, Jun 28, 2024 at 04:20:02PM +0100, Peter Maydell wrote:
> > > On Thu, 27 Jun 2024 at 14:39, Akihiko Odaki
> > > wrote:
> > > >
> > > > FDT properties are aligned b
On Fri, Jul 05, 2024 at 01:04:51AM +, Zhijian Li (Fujitsu) wrote:
> Date: Fri, 5 Jul 2024 01:04:51 +
> From: "Zhijian Li (Fujitsu)"
> Subject: Re: [PATCH 1/3] hw/cxl: Get rid of unused cfmw_list
>
> Jonathan,
>
>
> There is a new user for cfmw_list now
> https://lore.kernel.org/qemu-dev
在 2024/7/4 下午8:47, maobibo 写道:
On 2024/7/4 下午7:12, Song Gao wrote:
We set the value of register CSR_PRCFG3, but left out CSR_PRCFG1
and CSR_PRCFG2. Set CSR_PRCFG1 and CSR_PRCFG2 according to the
default values of the physical machine.
Signed-off-by: Song Gao
---
target/loongarch/cpu.c | 6
Reviewed-by: Xingtao Yao
> -Original Message-
> From: qemu-devel-bounces+yaoxt.fnst=fujitsu@nongnu.org
> On Behalf Of
> Pierrick Bouvier
> Sent: Friday, July 5, 2024 8:34 AM
> To: qemu-devel@nongnu.org
> Cc: Alexandre Iooss ; Richard Henderson
> ; Marcel Apfelbaum
> ; Pierrick Bouvie
Reviewed-by: Xingtao Yao
> -Original Message-
> From: qemu-devel-bounces+yaoxt.fnst=fujitsu@nongnu.org
> On Behalf Of
> Pierrick Bouvier
> Sent: Friday, July 5, 2024 8:34 AM
> To: qemu-devel@nongnu.org
> Cc: Alexandre Iooss ; Richard Henderson
> ; Marcel Apfelbaum
> ; Pierrick Bouvie
On Thu Jul 4, 2024 at 10:15 PM AEST, Peter Maydell wrote:
> On Sat, 29 Jun 2024 at 04:17, David Gibson
> wrote:
> >
> > On Fri, Jun 28, 2024 at 04:20:02PM +0100, Peter Maydell wrote:
> > > On Thu, 27 Jun 2024 at 14:39, Akihiko Odaki
> > > wrote:
> > > >
> > > > FDT properties are aligned by 4 b
Jonathan,
There is a new user for cfmw_list now
https://lore.kernel.org/qemu-devel/20240704093404.1848132-1-zhao1@linux.intel.com/
So I think we should drop this patch.
On 02/07/2024 22:34, Jonathan Cameron wrote:
> From: Li Zhijian
>
> There is no user for this member. All '-M cxl-fmw.N
> -Original Message-
> From: qemu-devel-bounces+yaoxt.fnst=fujitsu@nongnu.org
> On Behalf Of Zhao
> Liu
> Sent: Thursday, July 4, 2024 5:34 PM
> To: Jonathan Cameron ; Fan Ni
>
> Cc: qemu-devel@nongnu.org; qemu-sta...@nongnu.org; Zhao Liu
>
> Subject: [PATCH] hw/cxl/cxl-host: Fix
Posted v5.
On 7/2/24 11:44, Pierrick Bouvier wrote:
This series allows plugins to know which value is read/written during a memory
access.
For every memory access, we know copy this value before calling mem callbacks,
and those can query it using new API function:
- qemu_plugin_mem_get_value
M
On Fri, 5 Jul 2024, BALATON Zoltan wrote:
On Thu, 4 Jul 2024, Bernhard Beschow wrote:
When @cpu_intr is populated before vt82xx's realize(), it can be directly
passed
to i8259_init(), avoiding the need for the intermediate
via_isa_request_i8259_irq() handler. The result is less code and runtime
This value can be accessed only during a memory callback, using
new qemu_plugin_mem_get_value function.
Returned value can be extended when QEMU will support accesses wider
than 128 bits.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1719
Resolves: https://gitlab.com/qemu-project/qemu/-
On Thu, 4 Jul 2024, Bernhard Beschow wrote:
When @cpu_intr is populated before vt82xx's realize(), it can be directly passed
to i8259_init(), avoiding the need for the intermediate
via_isa_request_i8259_irq() handler. The result is less code and runtime
overhead, and a fixed memory leak caused by
Different code paths handle memory accesses:
- tcg generated code
- load/store helpers
- atomic helpers
This value is saved in cpu->neg.plugin_mem_value_{high,low}. Values are
written only for accessed word size (upper bits are not set).
Atomic operations are doing read/write at the same time, so
By using "print-accesses=true" option, mem plugin will now print every
value accessed, with associated size, type (store vs load), symbol,
instruction address and phys/virt address accessed.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
tests/plugin/mem.c | 69 +
A specific plugin test can now read and check a plugin output, to ensure
it contains expected values.
Tested-by: Xingtao Yao
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
tests/tcg/Makefile.target | 7 +++
1 file changed, 7 insertions(+)
diff --git a/tests/tcg/Makefil
Add an explicit test to check expected memory values are read/written.
For sizes 8, 16, 32, 64 and 128, we generate a load/store operation.
For size 8 -> 64, we generate an atomic __sync_val_compare_and_swap too.
For 128bits memory access, we rely on SSE2 instructions.
By default, atomic accesses
This series allows plugins to know which value is read/written during a memory
access.
For every memory access, we know copy this value before calling mem callbacks,
and those can query it using new API function:
- qemu_plugin_mem_get_value
Mem plugin was extended to print accesses, and a new tes
data was correctly copied, but size of array was not set
(g_array_sized_new only reserves memory, but does not set size).
As a result, callbacks were not called for code path relying on
plugin_register_vcpu_mem_cb().
Found when trying to trigger mem access callbacks for atomic
instructions.
Revi
Only multiarch tests are run with plugins, and we want to be able to run
per-arch test with plugins too.
Tested-by: Xingtao Yao
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
tests/tcg/Makefile.target | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/tes
On 7/3/24 11:58, Richard Henderson wrote:
On 7/2/24 11:44, Pierrick Bouvier wrote:
Different code paths handle memory accesses:
- tcg generated code
- load/store helpers
- atomic helpers
This value is saved in cpu->plugin_state.
Atomic operations are doing read/write at the same time, so we ge
On Thu, 4 Jul 2024, Bernhard Beschow wrote:
Makes the code more comprehensible, matches the datasheet and the piix4 device
model.
Signed-off-by: Bernhard Beschow
---
hw/isa/vt82c686.c | 2 +-
hw/mips/fuloong2e.c | 2 +-
hw/ppc/amigaone.c | 4 ++--
hw/ppc/pegasos2.c | 4 ++--
4 files changed,
On Thu Jul 4, 2024 at 10:34 PM AEST, BALATON Zoltan wrote:
> On Thu, 4 Jul 2024, Nicholas Piggin wrote:
> > On Mon May 27, 2024 at 9:12 AM AEST, BALATON Zoltan wrote:
> >> This function is used only once, its return value is ignored and one
> >> of its parameter is a return value from a previous ca
On Thu Jul 4, 2024 at 9:48 PM AEST, Thomas Huth wrote:
> On 04/07/2024 13.20, Nicholas Piggin wrote:
> > On Tue Jul 2, 2024 at 8:33 PM AEST, Thomas Huth wrote:
> >> From: Nicholas Piggin
> >>
> >> s390x with TCG is more stable now. Enable it.
> >
> > Ah, you did a more complete version of my flic
On Thu Jul 4, 2024 at 9:23 PM AEST, Salil Mehta wrote:
> HI Nick,
>
> Thanks for taking time to review. Please find my replies inline.
>
> > From: Nicholas Piggin
> > Sent: Thursday, July 4, 2024 3:49 AM
> > To: Salil Mehta ; qemu-devel@nongnu.org;
> > qemu-...@nongnu.org; m...@redhat.com
> >
On 7/2/24 18:56, Xingtao Yao (Fujitsu) wrote:
Tested-by: Xingtao Yao
one small suggestion:
Keeping the addresses or values of fixed size in output message can improve the
readability of logs.
Ok, I'll do it for every size.
like:
+case QEMU_PLUGIN_MEM_VALUE_U8:
+g_string_append
On 7/4/24 09:30, Richard Henderson wrote:
On 7/2/24 11:44, Pierrick Bouvier wrote:
+case QEMU_PLUGIN_MEM_VALUE_U128:
+g_string_append_printf(out, "0x%.0"PRIx64"%"PRIx64,
+ value.data.u128.high, value.data.u128.low);
PRIx64 does not pad.
You need %016"P
Ping. It rebases onto master just fine.
r~
On 6/5/24 14:57, Richard Henderson wrote:
v1: 20220906101747.344559-1-richard.hender...@linaro.org
A lot has changed in the 20 months since, including generic
cleanups and splitting out the PER fixes.
r~
Richard Henderson (10):
target/s390x: C
On Thu, Jul 04, 2024 at 03:12:48PM +, CLEMENT MATHIEU--DRIF wrote:
> From: Clément Mathieu--Drif
>
> The 'level' field in vtd_iotlb_key is an unsigned integer.
> We don't need to store level as an int in vtd_lookup_iotlb.
>
> VTDIOTLBPageInvInfo.mask is used in binary operations with address
On 7/4/24 08:18, Richard Henderson wrote:
On 7/4/24 07:50, Ilya Leoshkevich wrote:
On Tue, 2024-07-02 at 16:41 -0700, Richard Henderson wrote:
While looking into Zoltan's attempt to speed up ppc64 DCBZ
(data cache block set to zero), I wondered what AArch64 was
doing differently. It turned out
On Thu, Jul 04, 2024 at 11:11:20PM +0200, Giacomo Parmeggiani wrote:
> PING
> Hello Li He, maintainers,
>
> Any chance to revive this thread?
> The patch series no longer applies to latest QEMU and it would be a useful
> feature to have.
>
> BR
> Giacomo
Not sure why I didn't apply this.
Care
Currently, if VIRTIO_BALLOON_F_FREE_PAGE_HINT is off but
VIRTIO_BALLOON_F_REPORTING is on, then the reporting vq
gets number 3 while spec says it's number 4.
It happens to work because the linux virtio pci driver
is *also* out of spec.
To fix:
1. add vq4 as per spec
2. to help out the buggy Linux
PING
Hello Li He, maintainers,
Any chance to revive this thread?
The patch series no longer applies to latest QEMU and it would be a useful
feature to have.
BR
Giacomo
> On 22 Jun 2022, at 11:15, Lei He wrote:
>
> 1. add test suite for ecdsa algorithm.
> 2. use qcrypto_akcihper_max_xxx_len t
On 24-07-03 17:54:10, Jeuk Kim wrote:
> The function ufs_is_mcq_reg() only evaluated the range of the
> mcq_op_reg offset, which is defined as a constant.
> Therefore, it was possible for ufs_is_mcq_reg() to return true
> despite ufs device is configured to not support the mcq.
> This could cause u
Am 3. Juli 2024 11:13:08 UTC schrieb BALATON Zoltan :
>On Wed, 3 Jul 2024, Bernhard Beschow wrote:
>> Am 3. Juli 2024 00:09:45 UTC schrieb BALATON Zoltan :
>>> On Tue, 2 Jul 2024, Bernhard Beschow wrote:
Am 2. Juli 2024 18:42:23 UTC schrieb Bernhard Beschow :
> Am 1. Juli 2024 12:58:15
From: Anton Johansson
For TBs crossing page boundaries, the 2nd page will never be
recorded/removed, as the index of the 2nd page is computed from the
address of the 1st page. This is due to a typo, fix it.
Cc: qemu-sta...@nongnu.org
Fixes: deba78709a ("accel/tcg: Always lock pages before transl
From: Kevin Wolf
One use case for 'qemu-img info' is verifying that untrusted images
don't reference an unwanted external file, be it as a backing file or an
external data file. To make sure that calling 'qemu-img info' can't
already have undesired side effects with a malicious image, just don't
From: Daniel P. Berrangé
Validate that it is possible to pass 'parameter=1' for any SMP topology
parameter, since unsupported parameters are implicitly considered to
always have a value of 1.
Signed-off-by: Daniel P. Berrangé
Reviewed-by: Zhao Liu
Reviewed-by: Ján Tomko
Message-ID: <202405131
From: Philippe Mathieu-Daudé
The VIRTIO Sound Device conforms with the Virtio spec v1.2,
thus only use little endianness.
Remove the suspicious target_words_bigendian() noticed during
code review.
Cc: qemu-sta...@nongnu.org
Fixes: eb9ad377bb ("virtio-sound: handle control messages and streams")
From: Dongwon Kim
Draw routine needs to be manually invoked in the next refresh
if there is a scanout blob from the guest. This is to prevent
a situation where there is a scheduled draw event but it won't
happen bacause the window is currently in inactive state
(minimized or tabified). If draw is
From: Richard Henderson
Input denormals cause the Javascript inexact bit
(output to Z) to be set.
Cc: qemu-sta...@nongnu.org
Fixes: 6c1f6f2733a ("target/arm: Implement ARMv8.3-JSConv")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2375
Reviewed-by: Peter Maydell
Signed-off-by: Richard
From: Ilya Leoshkevich
Like TARGET_NR_setuid, TARGET_NR_setgroups should affect only the
calling thread, and not the entire process. Therefore, implement it
using a syscall, and not a libc call.
Cc: qemu-sta...@nongnu.org
Fixes: 19b84f3c35d7 ("added setgroups and getgroups syscalls")
Signed-off-
From: Thomas Huth
RHEL 9 (and thus also the derivatives) have been available since two
years now, so according to QEMU's support policy, we can drop the active
support for the previous major version 8 now.
Another reason for doing this is that Centos Stream 8 will go EOL soon:
https://blog.cent
From: Kevin Wolf
We want to disable filename parsing for data files because it's too easy
to abuse in malicious image files. Make the test ready for the change by
passing the data file explicitly in command line options.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Kevin Wolf
Reviewed-by: Eric Bla
From: Kevin Wolf
When handling image filenames from legacy options such as -drive or from
tools, these filenames are parsed for protocol prefixes, including for
the json:{} pseudo-protocol.
This behaviour is intended for filenames that come directly from the
command line and for backing files, w
From: Richard Henderson
Argument ordering for setcond2 is:
output, a_low, a_high, b_low, b_high, cond
The test is supposed to be against b_low, not a_high.
Cc: qemu-sta...@nongnu.org
Fixes: ceb9ee06b71 ("tcg/optimize: Handle TCG_COND_TST{EQ,NE}")
Resolves: https://gitlab.com/qemu-project/qem
From: Chuang Xu
When QEMU is started with:
-cpu host,host-cache-info=on,l3-cache=off \
-smp 2,sockets=1,dies=1,cores=1,threads=2
Guest can't acquire maximum number of addressable IDs for processor cores in
the physical package from CPUID[04H].
When creating a CPU topology of 1 core per package,
From: Richard Henderson
The inner loop, bounded by eltspersegment, must not be
larger than the outer loop, bounded by elements.
Cc: qemu-sta...@nongnu.org
Fixes: 18fc2405781 ("target/arm: Implement SVE fp complex multiply add
(indexed)")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2
From: Gerd Hoffmann
In case the display surface uses a shared buffer (i.e. uses vga vram
directly instead of a shadow) go unshare the buffer before clearing it.
This avoids vga memory corruption, which in turn fixes unblanking not
working properly with X11.
Cc: qemu-sta...@nongnu.org
Resolves:
From: Kevin Wolf
We want to disable filename parsing for data files because it's too easy
to abuse in malicious image files. Make the test ready for the change by
passing the data file explicitly in command line options.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Kevin Wolf
Reviewed-by: Eric Bla
From: Daniel P. Berrangé
This effectively reverts
commit 54c4ea8f3ae614054079395842128a856a73dbf9
Author: Zhao Liu
Date: Sat Mar 9 00:01:37 2024 +0800
hw/core/machine-smp: Deprecate unsupported "parameter=1" SMP configurations
but is not done as a 'git revert' since the part of th
From: Stefan Hajnoczi
Commit 1f25c172f837 ("monitor: use aio_co_reschedule_self()") was a code
cleanup that uses aio_co_reschedule_self() instead of open coding
coroutine rescheduling.
Bug RHEL-34618 was reported and Kevin Wolf identified
the root cause. I missed that aio_co_reschedule_self() -
From: Fabiano Rosas
When the "file:" migration support was added we missed the special
case in the qemu_open_old implementation that allows for a particular
file name format to be used to refer to a set of file descriptors that
have been previously provided to QEMU via the add-fd QMP command.
Wh
From: Richard Henderson
Simplify the logic for two-part, 32-bit pc-relative addresses.
Rather than assume all such fit in int32_t, do some arithmetic
and assert a result, do some arithmetic first and then check
to see if the pieces are in range.
Cc: qemu-sta...@nongnu.org
Fixes: dacc51720db ("tc
From: Alexey Dobriyan
Reproducer from https://gitlab.com/qemu-project/qemu/-/issues/1451
creates small packet (1 segment, len = 10 == n->guest_hdr_len),
then destroys queue.
"if (n->host_hdr_len != n->guest_hdr_len)" is triggered, if body creates
zero length/zero segment packet as there is nothi
From: Clément Chigot
The result has to be done with the signed denominator (b32) instead of
the unsigned value passed in argument (b).
Cc: qemu-sta...@nongnu.org
Fixes: 1326010322d6 ("target/sparc: Remove CC_OP_DIV")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2319
Signed-off-by: Clé
The following patches are queued for QEMU stable v9.0.2:
https://gitlab.com/qemu-project/qemu/-/commits/staging-9.0
Patch freeze is 2024-07-14, and the release is planned for 2024-07-16:
https://wiki.qemu.org/Planning/9.0
Please respond here or CC qemu-sta...@nongnu.org on any additional pa
From: Mark Cave-Ayland
The calculation of FrameTemp is done using the size indicated by mo_pushpop()
before being written back to EBP, but the final writeback to EBP is done using
the size indicated by mo_stacksize().
In the case where mo_pushpop() is MO_32 and mo_stacksize() is MO_16 then the
f
When @cpu_intr is populated before vt82xx's realize(), it can be directly passed
to i8259_init(), avoiding the need for the intermediate
via_isa_request_i8259_irq() handler. The result is less code and runtime
overhead, and a fixed memory leak caused by qemu_allocate_irqs().
Inspired-by: Philippe
When @cpu_intr is populated before pixx4's realize(), it can be directly passed
to i8259_init(), avoiding the need for the intermediate piix_request_i8259_irq()
handler. The result is less code and runtime overhead, and a fixed memory leak
caused by qemu_allocate_irqs().
Inspired-by: Philippe Math
This series first turns vt82c686's "INTR" pin into a named GPIO for better
comprehensibility. It then continues fixing qemu_irq memory leaks in vt82c686
and piix4 by connecting out IRQs of the south bridges before they get realized.
This approach is already used in the pc machines after it had been
Makes the code more comprehensible, matches the datasheet and the piix4 device
model.
Signed-off-by: Bernhard Beschow
---
hw/isa/vt82c686.c | 2 +-
hw/mips/fuloong2e.c | 2 +-
hw/ppc/amigaone.c | 4 ++--
hw/ppc/pegasos2.c | 4 ++--
4 files changed, 6 insertions(+), 6 deletions(-)
diff --g
Richard Henderson writes:
> Supercedes: 20240629-tcg-v3-0-fa57918bd...@daynix.com
> ("[PATCH v3 0/7] tests/tcg/aarch64: Fix inline assemblies for clang")
>
> On top of Akihiko's patches for aarch64, additional changes are
> required for arm, both as a host and as a guest.
Queued to testing/next,
I will skip this since Klaus Jensen's review is required for NVMe anyway.
Stefan
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On Thu, Jun 13, 2024 at 03:13:27PM +0800, Changqi Lu wrote:
> Add persistent reservation in/out operations for iscsi driver.
> The following methods are implemented: bdrv_co_pr_read_keys,
> bdrv_co_pr_read_reservation, bdrv_co_pr_register, bdrv_co_pr_reserve,
> bdrv_co_pr_release, bdrv_co_pr_clear
On Thu, Jun 13, 2024 at 03:13:23PM +0800, Changqi Lu wrote:
> Add constants for the NVMe persistent command protocol.
> The constants include the reservation command opcode and
> reservation type values defined in section 7 of the NVMe
> 2.0 specification.
>
> Signed-off-by: Changqi Lu
> Signed-o
On Thu, Jun 13, 2024 at 03:13:25PM +0800, Changqi Lu wrote:
> This commit enables ONCS to support the reservation
> function at the controller level. Also enables rescap
> function in the namespace by detecting the supported reservation
> function in the backend driver.
>
> Signed-off-by: Changqi
On Thu, Jun 13, 2024 at 03:13:22PM +0800, Changqi Lu wrote:
> Add persistent reservation in/out operations in the
> SCSI device layer. By introducing the persistent
> reservation in/out api, this enables the SCSI device
> to perform reservation-related tasks, including querying
> keys, querying res
On Thu, Jun 13, 2024 at 03:13:22PM +0800, Changqi Lu wrote:
> Add persistent reservation in/out operations in the
> SCSI device layer. By introducing the persistent
> reservation in/out api, this enables the SCSI device
> to perform reservation-related tasks, including querying
> keys, querying res
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