On 13/08/2024 11.52, Richard Henderson wrote:
In the CI that we actually run (x86) we don't want to use ASan,
only UBSan, we jump through --extra-cflags hoops to make that
happen, and we fail to disable function sanitizer during normal
configuration.
In the CI that we don't run, we enable ASan a
Each virtual console in the SDL2 frontend has a key state map.
When switching windows with GUI keys we have to release all
pressed modifier keys in the currently active window, because
after the switch the now inactive window no longer receives the
key release events.
To reproduce the issue open a
Windows only:
The libSDL2 Windows message loop needs the libSDL2 Windows low
level keyboard hook procedure to grab the left and right Windows
keys correctly. Reenable the SDL2 Windows keyboard hook procedure.
Because the QEMU Windows keyboard hook procedure is still needed
to filter out the speci
Ignore GUI keys for SDL_TEXTINPUT events, just like GUI keys are
ignored for SDL_KEYDOWN events. This prevents unintended text input
in a text console when hiding the text console with the GUI keys.
The SDL_TEXTINPUT event always comes after the SDL_KEYDOWN event.
See libsdl-org/SDL issue #1659.
The Windows keys do not work properly with the SDL backend on Windows.
Patch 1/3 improves the situation. However, it's impossible to solve the
problem completely, as there is no way to grab the Windows keys. The
Windows keys are reserved for the operating system. In addition to
Ctrl-Alt-Del, there
08.09.2024 20:39, Richard Henderson wrote:
On 9/8/24 00:16, Michael Tokarev wrote:
For 32bit ARM fcntl64 syscall there are 2 possible argument types,
depending on cpu_env->eabi. For other architectures, it is plain
struct flock64 in all cases. In order to solve this, old code
used to take addr
On Mon, Aug 19, 2024 at 6:26 PM ~liuxu wrote:
>
> From: lxx <1733205...@qq.com>
>
> This patch adds support for the Zilsd and Zclsd extension,
> which is documented at
> https://github.com/riscv/riscv-zilsd/releases/tag/v0.9.0
>
> Co-developed-by: SUN Dongya
> Co-developed-by: LIU Xu
> Co-devel
On Sat, Sep 7, 2024 at 6:24 AM Tomasz Jeznach wrote:
>
> The IMSIC state variable eistate[] is modified by CSR instructions
> within a range dedicated to the local CPU and by MMIO writes from any CPU.
> Access to eistate from MMIO accessors is protected by the BQL, but
> read-modify-write (RMW) se
On Fri, Sep 6, 2024 at 7:50 PM Thomas Huth wrote:
>
> If QEMU has been configured with "--without-default-devices", the build
> is currently failing with:
>
> /usr/bin/ld: libqemu-riscv32-softmmu.a.p/target_riscv_cpu_helper.c.o:
> in function `riscv_cpu_do_interrupt':
> .../qemu/target/riscv/c
On Wed, Aug 28, 2024 at 6:37 PM Alexandre Ghiti wrote:
>
> The Svvptc extension describes a uarch that does not cache invalid TLB
> entries: that's the case for qemu so there is nothing particular to
> implement other than the introduction of this extension.
>
> Since qemu already exposes Svvptc b
On Wed, Aug 28, 2024 at 6:37 PM Alexandre Ghiti wrote:
>
> The Svvptc extension describes a uarch that does not cache invalid TLB
> entries: that's the case for qemu so there is nothing particular to
> implement other than the introduction of this extension.
>
> Since qemu already exposes Svvptc b
On Tue, Aug 6, 2024 at 7:05 AM Gregor Haas wrote:
>
> This patch series adds support for specifying OpenSBI domains on the QEMU
> command line. A simple example of what this looks like is below, including
> mapping the board's UART into the secondary domain:
Thanks for the patch, sorry it took me
The code 'ops = ACCEL_OPS_CLASS(module_object_class_by_name(ops_name));' is
unnecessary;
And, the following code :
1.has the same functionality;
2.includes error checking;
Signed-off-by: Andrew.Yuan
---
accel/accel-system.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/ac
在 2024/8/22 下午2:52, Bibo Mao 写道:
Add the support needed for creating prstatus elf notes. This allows
us to use QMP dump-guest-memory.
Now ELF notes of LoongArch only supports general elf notes, LSX and
LASX is not supported, since it is mainly used to dump guest memory.
Signed-off-by: Bibo M
On Mon, Aug 19, 2024 at 5:50 PM Andrew Jones wrote:
>
> On Mon, Aug 19, 2024 at 11:19:18AM GMT, Alistair Francis wrote:
> > On Sat, Aug 17, 2024 at 2:08 AM Andrew Jones
> > wrote:
> > >
> > > Older firmwares and OS kernels which use deprecated device tree
> > > properties or are missing support
On Tue, Aug 13, 2024 at 8:24 PM Andrew Jones wrote:
>
> On Tue, Aug 13, 2024 at 10:21:13AM GMT, Philippe Mathieu-Daudé wrote:
> > On 13/8/24 10:00, Andrew Jones wrote:
> > > On Tue, Aug 13, 2024 at 05:43:07PM GMT, Richard Henderson wrote:
> > > > On 8/13/24 17:13, Andrew Jones wrote:
> > > > > C d
On Fri, Sep 6, 2024 at 5:57 PM Michael S. Tsirkin wrote:
>
> On Thu, Sep 05, 2024 at 07:13:23PM +0100, Daniel P. Berrangé wrote:
> > The virtio-net code for eBPF RSS is still ignoring errors when
> > failing to load the eBPF RSS program passed in by the mgmt app
> > via pre-opened FDs.
> >
> > Thi
On Thu, Aug 8, 2024 at 6:21 PM Yong-Xuan Wang wrote:
>
> The section 4.5.2 of the RISC-V AIA specification says that any write
> to a sourcecfg register of an APLIC might (or might not) cause the
> corresponding interrupt-pending bit to be set to one if the rectified
> input value is high (= 1) un
在 2024/8/22 上午10:28, Bibo Mao 写道:
KVM provides interface KVM_REG_LOONGARCH_VCPU_RESET to reset vCPU,
it can be used to clear internal state about kvm kernel. vCPU reset
function is added here for kvm mode.
Signed-off-by: Bibo Mao
---
target/loongarch/cpu.c | 2 +-
target/loo
在 2024/8/23 下午3:30, Bibo Mao 写道:
For virtio VGA deivce libvirt will select VIRTIO_VGA firstly rather than
VIRTIO_GPU, VIRTIO_VGA device supports frame buffer however it requires
legacy VGA compatible support. Frame buffer area 0xa -- 0xc
conflicts with low memory area 0 -- 0x1000.
The current approach of using qemu_chr_fe_write() and ignoring the
return values results in dropped characters [1].
Let's update the SiFive UART to use a async sifive_uart_xmit() function
to transmit the characters and apply back pressure to the guest with
the SIFIVE_UART_TXFIFO_FULL status.
This
The current approach of using qemu_chr_fe_write() and ignoring the
return values results in dropped characters [1]. Ideally we want to
report FIFO status to the guest, but the HTIF isn't a real UART, so we
don't really have a way to do that.
Instead let's just use qemu_chr_fe_write_all() so at lea
This series fixes: https://gitlab.com/qemu-project/qemu/-/issues/2114
This converts the RISC-V charecter device callers of qemu_chr_fe_write()
to either use qemu_chr_fe_write_all() or to call qemu_chr_fe_write() async
and act on the return value.
v3:
- Fixup spelling
v2:
- Use Fifo8 for the Sif
On Sat, Aug 17, 2024 at 10:56 AM Samuel Holland
wrote:
>
> When riscv_load_firmware() loads an ELF, the ELF segment addresses are
> used, not the passed-in firmware_load_addr. The machine models assume
> the firmware entry point is what they provided for firmware_load_addr,
> and use that address
On Sat, Aug 17, 2024 at 10:56 AM Samuel Holland
wrote:
>
> When riscv_load_firmware() loads an ELF, the ELF segment addresses are
> used, not the passed-in firmware_load_addr. The machine models assume
> the firmware entry point is what they provided for firmware_load_addr,
> and use that address
New optional argument for 'blockdev-change-medium' QAPI command to allow
the caller to specify if they wish to enable file locking.
Signed-off-by: Joelle van Dyne
---
qapi/block.json| 23 ++-
block/monitor/block-hmp-cmds.c | 2 +-
block/qapi-sysemu.c
在 2024/9/9 上午9:41, Jason A. Donenfeld 写道:
On Mon, Sep 9, 2024 at 3:38 AM gaosong wrote:
在 2024/9/5 下午11:33, Jason A. Donenfeld 写道:
If the FDT contains /chosen/rng-seed, then the Linux RNG will use it to
initialize early. Set this using the usual guest random number
generation function.
在 2024/8/27 上午11:58, Bibo Mao 写道:
With edk2-stable202408 LoongArch UEFI bios, CSR PGD register is set only
if its value is equal to zero for boot cpu, it causes reboot issue. Since
CSR PGD register is changed with linux kernel, UEFI BIOS cannot use it.
Add workaround to clear CSR registers re
On Mon, Sep 9, 2024 at 3:38 AM gaosong wrote:
>
>
>
> 在 2024/9/5 下午11:33, Jason A. Donenfeld 写道:
> > If the FDT contains /chosen/rng-seed, then the Linux RNG will use it to
> > initialize early. Set this using the usual guest random number
> > generation function.
> >
> > This is the same procedur
在 2024/9/5 下午11:33, Jason A. Donenfeld 写道:
If the FDT contains /chosen/rng-seed, then the Linux RNG will use it to
initialize early. Set this using the usual guest random number
generation function.
This is the same procedure that's done in b91b6b5a2c ("hw/microblaze:
pass random seed to fdt"
在 2024/9/6 上午10:19, Bibo Mao 写道:
ACPI ged is used for power management on LoongArch virt platform, in
general it is parsed from acpi table. However if system boot directly from
elf kernel, no UEFI bios is provided and acpi table cannot be used also.
Here acpi ged pm register is exposed with F
On 2024/9/7 下午10:34, Jason A. Donenfeld wrote:
In order to support additional channels of communication using
`-serial`, add several serial ports, up to the standard 4 generally
supported by the 8250 driver.
Signed-off-by: Jason A. Donenfeld
---
hw/loongarch/acpi-build.c | 23
On Sat, Sep 7, 2024 at 1:25 PM Ajeet Singh wrote:
>
> Key Changes Compared to Version 4:
> Minor formatting changes
>
> Mark Corbin (15):
> bsd-user: Implement RISC-V CPU initialization and main loop
> bsd-user: Add RISC-V CPU execution loop and syscall handling
> bsd-user: Implement RISC-V
Ping.
On 8/13/24 02:52, Richard Henderson wrote:
In the CI that we actually run (x86) we don't want to use ASan,
only UBSan, we jump through --extra-cflags hoops to make that
happen, and we fail to disable function sanitizer during normal
configuration.
In the CI that we don't run, we enable AS
On 8/2/24 02:59, Ilya Leoshkevich wrote:
Copy XML files describing orig_ax from GDB and glue them with
CPUX86State.orig_ax.
Signed-off-by: Ilya Leoshkevich
---
configs/targets/i386-linux-user.mak | 2 +-
configs/targets/x86_64-linux-user.mak | 2 +-
gdb-xml/i386-32bit-linux.xml
On 8/2/24 02:59, Ilya Leoshkevich wrote:
@@ -248,6 +253,22 @@ static int x86_cpu_gdb_load_seg(X86CPU *cpu, X86Seg sreg,
uint8_t *mem_buf)
return 4;
}
+static int gdb_write_reg(CPUX86State *env, uint8_t *mem_buf, target_ulong *val)
+{
+if (TARGET_LONG_BITS == 64) {
+if (en
On 8/2/24 02:59, Ilya Leoshkevich wrote:
diff --git a/linux-user/qemu.h b/linux-user/qemu.h
index a2961f503f4..85ba5a53869 100644
--- a/linux-user/qemu.h
+++ b/linux-user/qemu.h
@@ -159,6 +159,11 @@ struct TaskState {
/* Start time of task after system boot in clock ticks */
uint6
Hi,
On Friday, August 30, 2024 4:18:31 PM GMT+5:30 Eugenio Perez Martin wrote:
> On Fri, Aug 30, 2024 at 12:20 PM Sahil wrote:
> > Hi,
> >
> > On Tuesday, August 27, 2024 9:00:36 PM GMT+5:30 Eugenio Perez Martin wrote:
> > > On Wed, Aug 21, 2024 at 2:20 PM Sahil wrote:
> > > > [...]
> > > > I h
On 8/2/24 02:59, Ilya Leoshkevich wrote:
It's the same as env_cpu(), but for const objects.
Signed-off-by: Ilya Leoshkevich
---
include/exec/cpu-common.h | 13 -
linux-user/elfload.c | 2 +-
2 files changed, 13 insertions(+), 2 deletions(-)
Reviewed-by: Richard Henderson
Ping.
On 7/4/24 15:26, Richard Henderson wrote:
Ping. It rebases onto master just fine.
r~
On 6/5/24 14:57, Richard Henderson wrote:
v1: 20220906101747.344559-1-richard.hender...@linaro.org
A lot has changed in the 20 months since, including generic
cleanups and splitting out the PER fixes.
Thank you, Manos.
I'm not discouraged by the difficulty. I guess I just didn't know where to
start from. Thanks for the direction.
On Sun, 08 Sept 2024, 09:51 Manos Pitsidianakis, <
manos.pitsidiana...@linaro.org> wrote:
> On Sun, 08 Sep 2024 10:28, Joseph Kurape wrote:
> >Hello,
> >
> >I'm ne
Signed-off-by: Richard Henderson
---
Based-on: <20240908022632.459477-1-richard.hender...@linaro.org>
("tcg: Improve support for cmpsel_vec")
---
tcg/i386/tcg-target.h | 2 +-
tcg/i386/tcg-target.c.inc | 31 ---
2 files changed, 29 insertions(+), 4 deletions(-)
Hi,
the Allwinner H3 USB port qemu emulation creates separate USB ports
for its EHCI and OHCI controllers, resulting in a total of 8 USB ports.
>From the orangepi-pc emulation:
# lsusb
Bus 005 Device 001: ID 1d6b:0002
Bus 003 Device 001: ID 1d6b:0002
Bus 001 Device 001: ID 1d6b:0002
Bus 008 Devic
On 9/8/24 00:16, Michael Tokarev wrote:
For 32bit ARM fcntl64 syscall there are 2 possible argument types,
depending on cpu_env->eabi. For other architectures, it is plain
struct flock64 in all cases. In order to solve this, old code
used to take address of the conversion function and and run i
>On Fri, Sep 06, 2024 at 10:10:45AM +0800, luzhixing12345 wrote:
>> Hi, can someone help review this patch?
>>
>> Signed-off-by: luzhixing12345
>
>You got comments Aug 5, pls address them.
ok, the comments are addressed.
>On Sun, Aug 04, 2024 at 01:04:20PM GMT, luzhixing12345 wrote:
>>add a ref
From: Peter Maydell
The TYPE_NUBUS_DEVICE class lets the user specify the nubus slot
using an int32 "slot" QOM property. Its realize method doesn't do
any range checking on this value, which Coverity notices by way of
the possibility that 'nd->slot * NUBUS_SUPER_SLOT_SIZE' might
overflow the 32-
From: Peter Maydell
The datasheets for the SoC and board we model here are still
available from the NXP website; add their URLs and titles for
future reference.
Signed-off-by: Peter Maydell
Reviewed-by: Thomas Huth
Message-ID: <20240830173452.2086140-3-peter.mayd...@linaro.org>
Signed-off-by:
From: Peter Maydell
In m5208_sys_read(), we have a loop of n from 0 to 31, and we
calculate (2u << n). For the n == 31 iteration this will shift off
the top of the unsigned 32 bit integer.
This is harmless, because we're going to stop the loop with n == 31
anyway, but we can avoid the error by
Hi!
The following changes since commit 1581a0bc928d61230ed6e43bcb83f2f6737d0bc0:
Merge tag 'pull-ufs-20240906' of https://gitlab.com/jeuk20.kim/qemu into
staging (2024-09-06 15:27:43 +0100)
are available in the Git repository at:
https://gitlab.com/huth/qemu.git tags/pull-request-2024-09-
06.09.2024 17:09, Daniel P. Berrangé wrote:
This fixes:
commit e28112d00703abd136e2411d23931f4f891c9244
Author: Daniel P. Berrangé
Date: Thu Jun 8 17:40:16 2023 +0100
gitlab: stable staging branches publish containers in a separate tag
Due to a copy+paste mistake, that commit
07.09.2024 13:44, Peter Maydell:
On Sat, 7 Sept 2024 at 07:39, Michael Tokarev wrote:
07.09.2024 02:59, Kenneth Adam Miller wrote:
Hello,
I'm on commit bd80b59 and my host is:
$ git desc bd80b59
v2.4.0-rc3-9-gbd80b5963f
Date: Mon Aug 3 11:44:07 2015 +0100
Wow, that is very old. So the
Add cache_supported flags in SMPCompatProps to allow machines to
configure various caches support.
And check the compatibility of the cache properties with the
machine support in machine_parse_smp_cache().
Signed-off-by: Zhao Liu
Tested-by: Yongwei Ma
---
Changes since Patch v1:
* Dropped mach
Allow user to configure l1d, l1i, l2 and l3 cache topologies for PC
machine.
Additionally, add the document of "-machine smp-cache" in
qemu-options.hx.
Signed-off-by: Zhao Liu
Tested-by: Yongwei Ma
---
Changes since Patch v1:
* Merged document into this patch. (Markus)
Changes since RFC v2:
With smp-cache object support, add smp cache topology for machine by
linking the smp-cache object.
Also add a helper to access cache topology level.
Signed-off-by: Zhao Liu
Tested-by: Yongwei Ma
---
Changes since Patch v1:
* Integrated cache properties list into MachineState and used -machine
User will configure smp cache topology via -machine smp-cache.
For this case, update the x86 CPUs' cache topology with user's
configuration in MachineState.
Signed-off-by: Zhao Liu
Tested-by: Yongwei Ma
---
Changes since RFC v2:
* Used smp_cache array to override cache topology.
* Wrapped the
Allow cache to be defined at the thread and module level. This
increases flexibility for x86 users to customize their cache topology.
Signed-off-by: Zhao Liu
Tested-by: Yongwei Ma
---
target/i386/cpu.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/target/i386/cp
Cache topology needs to be defined based on CPU topology levels. Thus,
define CPU topology enumeration in qapi/machine.json to make it generic
for all architectures.
To match the general topology naming style, rename CPU_TOPO_LEVEL_* to
CPU_TOPOLOGY_LEVEL_*, and rename SMT and package levels to th
The x86 and ARM need to allow user to configure cache properties
(current only topology):
* For x86, the default cache topology model (of max/host CPU) does not
always match the Host's real physical cache topology. Performance can
increase when the configured virtual topology is closer to th
Hi all,
Compared with previous Patch v1 [1], I've put the cache properties list
into -machine, this is to meet current needs and also remain compatible
with my future topology support (more discussion details, pls refer [2]).
This series is based on the commit 1581a0bc928d ("Merge tag 'pull-ufs-
On Sat, 7 Sep 2024, Kenneth Adam Miller wrote:
I found this:
https://qemu-project.gitlab.io/qemu/system/linuxboot.html
and this:
https://nickdesaulniers.github.io/blog/2018/10/24/booting-a-custom-linux-kernel-in-qemu-and-debugging-it-with-gdb/
So I now have serial output. But I still need to kno
On Sun, 08 Sep 2024 10:28, Joseph Kurape wrote:
Hello,
I'm new to open-source, but I've learned C and Python.
I've read the 'Getting Started' guide, but aside from signing up for the
mailing list and getting the source code, it doesn't provide much direction
for beginners.
I'm looking for som
Hello,
I'm new to open-source, but I've learned C and Python.
I've read the 'Getting Started' guide, but aside from signing up for the
mailing list and getting the source code, it doesn't provide much direction
for beginners.
I'm looking for somewhere I can contribute. Could any maintainer sugge
For 32bit ARM fcntl64 syscall there are 2 possible argument types,
depending on cpu_env->eabi. For other architectures, it is plain
struct flock64 in all cases. In order to solve this, old code
used to take address of the conversion function and and run it
through this pointer. Instead, introduc
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