On 8/9/24 04:26, Richard Henderson wrote:
Helper function to handle setting of VEXL based
on the type of the operation.
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.c.inc | 38 +++---
1 file changed, 15 insertions(+), 23 deletions(-)
Reviewed-by:
On 8/9/24 04:26, Richard Henderson wrote:
Add declaration to tcg-internal.h, making it available for
use from tcg backend vector expanders.
Signed-off-by: Richard Henderson
---
tcg/tcg-internal.h | 2 ++
tcg/tcg-op-vec.c | 4 ++--
2 files changed, 4 insertions(+), 2 deletions(-)
Reviewe
On 8/9/24 04:26, Richard Henderson wrote:
From: TANG Tiancheng
The loop in the 32-bit case of the vector compare operation
was incorrectly incrementing by 8 bytes per iteration instead
of 4 bytes. This caused the function to process only half of
the intended elements.
Cc: qemu-sta...@nongnu.or
Hi Zhou,
On 9/10/24 03:24, Zhou Wang via wrote:
> On 2024/9/9 22:31, Peter Maydell wrote:
>> On Mon, 9 Sept 2024 at 15:22, Zhou Wang via wrote:
>>> Hi All,
>>>
>>> When I tested mainline qemu(commit 7b87a25f49), it reports smmuv3 event 0x10
>>> during kernel booting up.
>> Does it still do this if
On 10/9/24 05:58, Richard Henderson wrote:
[rth@cfarm120 bld]$ make check-functional
[1/2] Generating tests/functional/func-precache-m68k-m68k_nextcube with
a custom command (wrapped by meson to set env)
FAILED: tests/functional/m68k-m68k_nextcube.tstamp
env
QEMU_TEST_PRECACHE=/home/rth/qemu/b
Hi Jacob,
On 10/9/24 06:34, Jacob Abrams wrote:
On 9/9/24 10:40, Philippe Mathieu-Daudé wrote:
Hi,
(Cc'ing Arnaud & Inès who are listed as maintainers)
On 6/9/24 18:12, Peter Maydell wrote:
On Mon, 2 Sept 2024 at 14:38, Jacob Abrams wrote:
These changes allow the official STM32L4xx HAL UA
On Tue, Sep 10, 2024 at 7:30 AM Si-Wei Liu wrote:
>
> Sorry for the delayed response, it seems I missed the email reply for
> some reason during the long weekend.
>
> On 9/2/2024 4:09 AM, Eugenio Perez Martin wrote:
> > On Fri, Aug 30, 2024 at 11:05 PM Si-Wei Liu wrote:
> >>
> >>
> >> On 8/30/202
In order to reduce the maintenance work of QMP.
Given that the focus of this patchset is huge VM migration, is
it possible to enable or disable these two features with a single
parameter, such as "cpu-aggressive-throttle"?
Yong
On Mon, Sep 9, 2024 at 10:26 PM Hyman Huang wrote:
> To enable the
On Tue, Sep 10, 2024 at 5:30 AM Peter Xu wrote:
> On Mon, Sep 09, 2024 at 10:25:36PM +0800, Hyman Huang wrote:
> > To activate the periodic CPU throttleing feature, introduce
> > the cpu-periodic-throttle.
> >
> > To control the frequency of throttling, introduce the
> > cpu-periodic-throttle-int
GitHub's CodeQL reports four critical errors which are fixed by this commit:
Unsigned difference expression compared to zero
An expression (u - v > 0) with unsigned values u, v is only false if u == v,
so all changed expressions did not work as expected.
Signed-off-by: Stefan Weil
---
I do
Sorry for the delayed response, it seems I missed the email reply for
some reason during the long weekend.
On 9/2/2024 4:09 AM, Eugenio Perez Martin wrote:
On Fri, Aug 30, 2024 at 11:05 PM Si-Wei Liu wrote:
On 8/30/2024 1:05 AM, Eugenio Perez Martin wrote:
On Fri, Aug 30, 2024 at 6:20 AM S
On Sat, Sep 7, 2024 at 6:24 AM Tomasz Jeznach wrote:
>
> The IMSIC state variable eistate[] is modified by CSR instructions
> within a range dedicated to the local CPU and by MMIO writes from any CPU.
> Access to eistate from MMIO accessors is protected by the BQL, but
> read-modify-write (RMW) se
On Fri, Sep 6, 2024 at 7:50 PM Thomas Huth wrote:
>
> If QEMU has been configured with "--without-default-devices", the build
> is currently failing with:
>
> /usr/bin/ld: libqemu-riscv32-softmmu.a.p/target_riscv_cpu_helper.c.o:
> in function `riscv_cpu_do_interrupt':
> .../qemu/target/riscv/c
The current approach of using qemu_chr_fe_write() and ignoring the
return values results in dropped characters [1].
Let's update the SiFive UART to use a async sifive_uart_xmit() function
to transmit the characters and apply back pressure to the guest with
the SIFIVE_UART_TXFIFO_FULL status.
This
This series fixes: https://gitlab.com/qemu-project/qemu/-/issues/2114
This converts the RISC-V charecter device callers of qemu_chr_fe_write()
to either use qemu_chr_fe_write_all() or to call qemu_chr_fe_write() async
and act on the return value.
v4:
- Drop the unused char_tx_time
- Update the
The current approach of using qemu_chr_fe_write() and ignoring the
return values results in dropped characters [1]. Ideally we want to
report FIFO status to the guest, but the HTIF isn't a real UART, so we
don't really have a way to do that.
Instead let's just use qemu_chr_fe_write_all() so at lea
On 9/9/24 10:40, Philippe Mathieu-Daudé wrote:
> Hi,
>
> (Cc'ing Arnaud & Inès who are listed as maintainers)
>
> On 6/9/24 18:12, Peter Maydell wrote:
>> On Mon, 2 Sept 2024 at 14:38, Jacob Abrams wrote:
>>>
>>> These changes allow the official STM32L4xx HAL UART driver to function
>>> prope
On 9/9/24 19:46, LIU Zhiwei wrote:
lmul = type - riscv_lg2_vlenb;
if (lmul < -3) {
/* Host VLEN >= 1024 bits. */
vlmul = VLMUL_M1;
I am not sure if we should use VLMUL_MF8,
Perhaps. See below.
} else if (lmul < 3) {
/* 1/8 ... 1 ... 8 */
vlmul = l
On 2024/09/09 23:18, Joelle van Dyne wrote:
On Mon, Sep 9, 2024 at 12:36 AM Akihiko Odaki wrote:
On 2024/09/09 10:58, Joelle van Dyne wrote:
New optional argument for 'blockdev-change-medium' QAPI command to allow
the caller to specify if they wish to enable file locking.
Signed-off-by: Joel
When a new listener for an address space is registered, the hypervisor must be
informed of all existing eventfds for that address space by calling
eventfd_add() for that listener. Similarly, when a listener is de-registered
from an address space, the hypervisor must be informed of all existing even
[rth@cfarm120 bld]$ make check-functional
[1/2] Generating tests/functional/func-precache-m68k-m68k_nextcube with a custom command
(wrapped by meson to set env)
FAILED: tests/functional/m68k-m68k_nextcube.tstamp
env QEMU_TEST_PRECACHE=/home/rth/qemu/bld/tests/functional/m68k-m68k_nextcube.tstamp
On Tue, Sep 10, 2024 at 11:41 AM Si-Wei Liu wrote:
>
> Hi Jason,
>
> It seems this series wasn't applied successfully, I still cannot see it
> from the latest tree. Any idea?
It breaks make check.
Eugenio, would you want to fix and resend the series?
Thanks
>
> In any case the fix LGTM.
>
> Re
On Mon, Sep 9, 2024 at 6:33 PM Andrew Jones wrote:
>
> C doesn't extend the sign bit for unsigned types since there isn't a
> sign bit to extend. This means a promotion of a u32 to a u64 results
> in the upper 32 bits of the u64 being zero. If that result is then
> used as a mask on another u64 th
Hi Jason,
It seems this series wasn't applied successfully, I still cannot see it
from the latest tree. Any idea?
In any case the fix LGTM.
Reviewed-by: Si-Wei Liu
Thanks,
-Siwei
On 1/31/2024 9:43 PM, Jason Wang wrote:
On Mon, Jan 29, 2024 at 9:24 PM Eugenio Pérez wrote:
Commit a0d7215e
On 2024/9/5 14:39, Richard Henderson wrote:
On 9/4/24 07:27, LIU Zhiwei wrote:
@@ -811,31 +849,52 @@ static void tcg_out_extrl_i64_i32(TCGContext
*s, TCGReg ret, TCGReg arg)
tcg_out_ext32s(s, ret, arg);
}
-static void tcg_out_ldst(TCGContext *s, RISCVInsn opc, TCGReg data,
-
On 2024/9/6 7:46, Alistair Francis wrote:
On Thu, Sep 5, 2024 at 12:29 AM LIU Zhiwei wrote:
From: TANG Tiancheng
Can you please mention RISC-V in the cover letter title. Otherwise
it's not obvious that this is RISC-V specific
Sorry. I miss it.
Thanks,
Zhiwei
Alistair
This patch set i
On Mon, Sep 9, 2024 at 6:33 PM Andrew Jones wrote:
>
> C doesn't extend the sign bit for unsigned types since there isn't a
> sign bit to extend. This means a promotion of a u32 to a u64 results
> in the upper 32 bits of the u64 being zero. If that result is then
> used as a mask on another u64 th
On 2024/9/5 12:05, Richard Henderson wrote:
On 9/4/24 07:27, LIU Zhiwei wrote:
From: Swung0x48
The RISC-V vector instruction set utilizes the LMUL field to group
multiple registers, enabling variable-length vector registers. This
implementation uses only the first register number of each gro
On 2024/9/9 23:45, Richard Henderson wrote:
On 9/9/24 00:18, LIU Zhiwei wrote:
On 2024/9/5 11:34, Richard Henderson wrote:
On 9/4/24 07:27, LIU Zhiwei wrote:
+ if (info & CPUINFO_ZVE64X) {
+ /*
+ * Get vlenb for Vector: vsetvli rd, x0, e64.
+ * VLMAX = LMUL * VLEN
On 2024/9/5 14:03, Richard Henderson wrote:
On 9/4/24 07:27, LIU Zhiwei wrote:
From: TANG Tiancheng
In RISC-V, vector operations require initial configuration using
the vset{i}vl{i} instruction.
This instruction:
1. Sets the vector length (vl) in bytes
2. Configures the vtype register
> -Original Message-
> From: Stefan Weil
> Sent: Tuesday, September 10, 2024 4:43 AM
> To: Zhang, Chen ; Li Zhijian ;
> Jason Wang
> Cc: qemu-devel@nongnu.org; Stefan Weil
> Subject: [PATCH] Fix calculation of minimum in colo_compare_tcp
>
> GitHub's CodeQL reports a critical error w
On 2024/9/9 下午9:13, gaosong wrote:
在 2024/9/9 下午7:52, gaosong 写道:
在 2024/9/4 下午2:18, Bibo Mao 写道:
Six registers scr0 - scr3, eflags and ftop are added in percpu vmstate.
And two functions kvm_loongarch_get_lbt/kvm_loongarch_put_lbt are added
to save/restore lbt registers.
Signed-off-by: B
On 9/10/24 04:18, Keith Busch wrote:
On Mon, Sep 09, 2024 at 07:34:45PM +0800, Changqi Lu wrote:
+static int coroutine_fn GRAPH_RDLOCK
+raw_co_pr_register(BlockDriverState *bs, uint64_t old_key,
+ uint64_t new_key, BlockPrType type,
+ bool ptpl, bool ignore
On 2024/9/9 22:47, Mostafa Saleh wrote:
> Hi Zhou,
>
> On Mon, Sep 9, 2024 at 3:22 PM Zhou Wang via wrote:
>>
>> Hi All,
>>
>> When I tested mainline qemu(commit 7b87a25f49), it reports smmuv3 event 0x10
>> during kernel booting up.
>>
>> qemu command which I use is as below:
>>
>> qemu-system-aa
On 2024/9/9 22:31, Peter Maydell wrote:
> On Mon, 9 Sept 2024 at 15:22, Zhou Wang via wrote:
>>
>> Hi All,
>>
>> When I tested mainline qemu(commit 7b87a25f49), it reports smmuv3 event 0x10
>> during kernel booting up.
>
> Does it still do this if you either:
> (1) use the v9.1.0 release (commit
On 2024/9/5 15:12, Richard Henderson wrote:
On 9/4/24 07:27, LIU Zhiwei wrote:
@@ -2322,6 +2411,51 @@ static void tcg_out_vec_op(TCGContext *s,
TCGOpcode opc,
riscv_set_vec_config_vl(s, type);
tcg_out_opc_vi(s, OPC_VXOR_VI, a0, a1, -1, true);
break;
+ case IND
On 2024/9/5 14:56, Richard Henderson wrote:
On 9/4/24 07:27, LIU Zhiwei wrote:
@@ -698,6 +704,21 @@ static bool tcg_out_mov(TCGContext *s, TCGType
type, TCGReg ret, TCGReg arg)
case TCG_TYPE_I64:
tcg_out_opc_imm(s, OPC_ADDI, ret, arg, 0);
break;
+ case TCG_TYPE_V6
On 9/9/24 16:19, Philippe Mathieu-Daudé wrote:
From: Richard Henderson
Signed-off-by: Richard Henderson
Message-ID: <20240605215739.4758-7-richard.hender...@linaro.org>
[PMD: Split patch, part 3/4]
Signed-off-by: Philippe Mathieu-Daudé
---
target/s390x/tcg/translate.c | 8 +---
1 file
On 9/9/24 16:19, Philippe Mathieu-Daudé wrote:
From: Richard Henderson
Signed-off-by: Richard Henderson
Message-ID: <20240605215739.4758-7-richard.hender...@linaro.org>
[PMD: Split patch, part 2/4]
Signed-off-by: Philippe Mathieu-Daudé
---
target/s390x/tcg/translate.c | 12
1
On 9/7/24 19:26, Richard Henderson wrote:
In order for that to happen, the tcg/i386 backend must be changed
so that it does not rely upon choices that it made during early
expansion, before optimization changes things.
FYI, tcg/ppc and tcg/s390x need similar changes.
But that doesn't affect rev
On Wed, Jul 17, 2024 at 7:41 AM Fabiano Rosas wrote:
>
> Yichen Wang writes:
>
> > From: Hao Xiang
> >
> > Multifd sender path gets an array of pages queued by the migration
> > thread. It performs zero page checking on every page in the array.
> > The pages are classfied as either a zero page o
From: Richard Henderson
Signed-off-by: Richard Henderson
Message-ID: <20240605215739.4758-7-richard.hender...@linaro.org>
[PMD: Split patch, part 2/4]
Signed-off-by: Philippe Mathieu-Daudé
---
target/s390x/tcg/translate.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff
From: Richard Henderson
Signed-off-by: Richard Henderson
Message-ID: <20240605215739.4758-7-richard.hender...@linaro.org>
[PMD: Split patch, part 3/4]
Signed-off-by: Philippe Mathieu-Daudé
---
target/s390x/tcg/translate.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --gi
From: Richard Henderson
Signed-off-by: Richard Henderson
Message-ID: <20240605215739.4758-7-richard.hender...@linaro.org>
[PMD: Split patch, part 4/4]
Signed-off-by: Philippe Mathieu-Daudé
---
target/s390x/tcg/translate.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff -
From: Richard Henderson
To simplify the following commits, rename 't' as 't2'.
Signed-off-by: Richard Henderson
Message-ID: <20240605215739.4758-7-richard.hender...@linaro.org>
[PMD: Split patch, part 1/4]
Signed-off-by: Philippe Mathieu-Daudé
---
target/s390x/tcg/translate.c | 21 +++
Nicholas Piggin writes:
> The move to decodetree flipped the inequality test for the VEC / VSX
> MSR facility check.
>
> This caused application crashes under Linux, where these facility
> unavailable interrupts are used for lazy-switching of VEC/VSX register
> sets. Getting the incorrect interru
On 9/9/24 18:22, Richard Henderson wrote:
Reviewed-by: Peter Maydell
I wonder, maybe you mispasted my previous R-b tags
with Peter's?
https://lore.kernel.org/qemu-devel/37096dc8-7827-4a4c-a27b-4f8343aa9...@linaro.org/
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-a64.c | 7
Reviewed:
https://lore.kernel.org/qemu-devel/37096dc8-7827-4a4c-a27b-4f8343aa9...@linaro.org/
On 9/9/24 18:22, Richard Henderson wrote:
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-a64.c | 47 ++
target/arm/tcg/a64.
On 9/9/24 18:22, Richard Henderson wrote:
Pre-reviewed:
https://lore.kernel.org/qemu-devel/10eb7805-6de3-45ec-8d2a-f5af5f635...@linaro.org/
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-a64.c | 121 +
target/arm/tcg
On 9/9/24 18:22, Richard Henderson wrote:
The extract2 tcg op performs the same operation
as the do_ext64 function.
I remember this one:
https://lore.kernel.org/qemu-devel/60f76a76-709a-4f32-974c-c771a724d...@linaro.org/
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
targ
On 9/9/24 19:28, Richard Henderson wrote:
These need not be exported beyond cpu.c.
Fix a typo in vmstate_fpu.
Signed-off-by: Richard Henderson
---
target/m68k/cpu.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 9/9/24 19:28, Richard Henderson wrote:
This enables the exceptions raised by the actual store
to be reflected as a failure.
Signed-off-by: Richard Henderson
---
target/m68k/translate.c | 107
1 file changed, 53 insertions(+), 54 deletions(-)
Revi
On 9/9/24 19:28, Richard Henderson wrote:
This enables the exceptions raised by the actual load
to be reflected as a failure.
Signed-off-by: Richard Henderson
---
target/m68k/translate.c | 104
1 file changed, 51 insertions(+), 53 deletions(-)
Revie
On 9/9/24 19:28, Richard Henderson wrote:
Move the exception to be raised into the helpers.
This in preparation for raising other exceptions,
and still wanting to return failure.
Signed-off-by: Richard Henderson
---
target/m68k/translate.c | 10 ++
1 file changed, 6 insertions(+), 4
On 9/9/24 19:28, Richard Henderson wrote:
Replace with gen_load_mode_fp and gen_store_mode_fp.
Return bool for success from the new functions.
Remove gen_ldst_fp and ea_what as unused.
Signed-off-by: Richard Henderson
---
target/m68k/translate.c | 125 +---
On 9/9/24 19:28, Richard Henderson wrote:
Use the env pointer in DisasContext.
Signed-off-by: Richard Henderson
---
target/m68k/translate.c | 21 ++---
1 file changed, 10 insertions(+), 11 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 9/9/24 19:28, Richard Henderson wrote:
Use the env pointer in DisasContext.
Signed-off-by: Richard Henderson
---
target/m68k/translate.c | 31 ---
1 file changed, 12 insertions(+), 19 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 9/9/24 19:28, Richard Henderson wrote:
Use the env pointer in DisasContext.
Signed-off-by: Richard Henderson
---
target/m68k/translate.c | 23 +++
1 file changed, 11 insertions(+), 12 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 9/9/24 19:28, Richard Henderson wrote:
Use the env pointer in DisasContext.
Signed-off-by: Richard Henderson
---
target/m68k/translate.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 9/9/24 19:28, Richard Henderson wrote:
Use the env pointer in DisasContext.
Signed-off-by: Richard Henderson
---
target/m68k/translate.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 9/9/24 19:28, Richard Henderson wrote:
The mode argument is extracted from 3 bits, and all cases are covered.
Signed-off-by: Richard Henderson
---
target/m68k/translate.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 9/9/24 19:28, Richard Henderson wrote:
This will enable further cleanups further down the call chain.
Signed-off-by: Richard Henderson
---
target/m68k/translate.c | 24 ++--
1 file changed, 10 insertions(+), 14 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 9/9/24 19:28, Richard Henderson wrote:
Call cpu_m68k_set_fpcr to make sure softfloat internals
are up-to-date with the restored FPCR.
Signed-off-by: Richard Henderson
---
target/m68k/cpu.c | 1 +
1 file changed, 1 insertion(+)
Reviewed-by: Philippe Mathieu-Daudé
On 9/9/24 20:07, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
target/sparc/cpu.h | 8 +++-
target/sparc/translate.c | 10 +++---
2 files changed, 14 insertions(+), 4 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
Peter Xu writes:
> On Mon, Sep 09, 2024 at 03:02:57PM +0100, Peter Maydell wrote:
>> On Mon, 9 Sept 2024 at 14:51, Hyman Huang wrote:
>> >
>> > Despite the fact that the responsive CPU throttle is enabled,
>> > the dirty sync count may not always increase because this is
>> > an optimization tha
On 9/9/24 13:21, Alex Bennée wrote:
Pierrick Bouvier writes:
On 9/9/24 03:00, Alex Bennée wrote:
Pierrick Bouvier writes:
On 9/5/24 08:21, Alex Bennée wrote:
Pierrick Bouvier writes:
This series allows plugins to know which value is read/written during a memory
access.
For every memor
On Mon, Sep 09, 2024 at 10:25:36PM +0800, Hyman Huang wrote:
> To activate the periodic CPU throttleing feature, introduce
> the cpu-periodic-throttle.
>
> To control the frequency of throttling, introduce the
> cpu-periodic-throttle-interval.
>
> Signed-off-by: Hyman Huang
Considering that I w
From: Glenn Miles
Adds support for single byte writes to offset 0xC38 of the TIMA address
space. When this offset is written to, the hardware disables the thread
context and copies the current state information to the odd cache line of
the pair specified by the NVT structure indexed by the THREA
From: Glenn Miles
Current code was updating the PIPR inside the xive_tctx_accept() function
instead of the xive_tctx_set_cppr function, which is where the HW would
have it updated.
Moved the update to the xive_tctx_set_cppr function which required
additional support for pool interrupts.
Fixes:
From: Glenn Miles
Adds support for single byte writes to offset 0x15 of the TIMA address
space. This offset holds the Logical Server Group Size (LGS) field.
The field is used to evenly distribute the interrupt load among the
members of a group, but is unused in the current implementation so we
j
From: Frederic Barrat
The OGEN field at offset 0x1F is a new field for Gen2 TIMA. This
patch defines it.
Signed-off-by: Frederic Barrat
Signed-off-by: Michael Kowal
Reviewed-by: Cédric Le Goater
---
include/hw/ppc/xive_regs.h | 1 +
hw/intc/xive.c | 4
2 files changed, 5 ins
Some of the TIMA Special CI operations perform the same operation at
alternative byte offsets and lengths. The following
xive2_tm_opertions[] table entries are missing when they exist for
other offsets/sizes and have been added:
- lwz@0x810 Pull/Invalidate O/S Context to registeradded
lwz@0x
In XIVE Gen 2 there are many operations that were not modeled and are
needed for PowerVM. These changes are associated with the following Thread
Interrupt Management Area subjects:
- OS context
- Thread context
- Pulling contexts to 'cache lines'
- Pool targets
- Enhaced trace data for XIVE G
From: Glenn Miles
PHYP uses 8-byte writes to the 2nd doubleword of the OS context
line when dispatching an OS level virtual processor. This
support was not used by OPAL/Linux and so was never added.
Without this support, the XIVE code doesn't notice that a new
context is being pushed and fails
From: Glenn Miles
Hypervisor "pool" targets do not get their own interrupt line and instead
must share an interrupt line with the hypervisor "physical" targets.
This also means that the pool ring must use some of the registers from the
physical ring in the TIMA. Specifically, the NSR, PIPR and C
From: Glenn Miles
When running PowerVM, the console is littered with XIVE traces regarding
invalid writes to TIMA address 0x100b6 due to a lack of support for writes
to the "TARGET" field which was added for XIVE GEN2. To fix this, we add
special op support for 1-byte writes to this field.
Sign
From: Glenn Miles
Adds support for single byte read of offset 0x838 of the TIMA address
space. According to the XIVE2 Specification, this causes the hardware
to atomically:
1. Read the number of bytes requested (lbz or lhz are supported).
2. Reset the valid bit of the thread context.
3. Re
Some the functions that have been created are specific to a ring or context.
Some
of these same functions are being changed to operate on any ring/context. This
will
simplify the next patch sets that are adding additional ring/context operations.
Signed-off-by: Michael Kowal
---
include/hw/pp
From: Frederic Barrat
The 'info pic' HMP command dumps the state of the interrupt controller.
Add the dump of the NVG and NVC tables to its output to ease debug.
Signed-off-by: Frederic Barrat
Signed-off-by: Michael Kowal
---
include/hw/ppc/xive2.h | 12
include/hw/ppc/xive2_reg
From: Michael Kowal
Making some pre-requisite alignment changes ahead of the following patch
sets. Making these changes now will ease the review of the patch sets.
Checkpatch wants the closing comment '*/' on a separate line, unless it is
on the same line as the starting comment '/*'.
There ar
From: Frederic Barrat
The 'PGoFirst' field of a Notify Virtual Processor tells if the NVP
belongs to a VP group.
Also, print the Reporting Cache Line address, if defined.
Signed-off-by: Frederic Barrat
Signed-off-by: Michael Kowal
---
include/hw/ppc/xive2_regs.h | 1 +
hw/intc/xive2.c
From: Frederic Barrat
Adds support for single byte writes to offset 0xC18 of the TIMA address
space. When this offset is written to, the hardware disables the OS
context and copies the current state information to the odd cache line
of the pair specified by the NVT structure indexed by the OS CA
GitHub's CodeQL reports a critical error which is fixed by using the MIN macro:
Unsigned difference expression compared to zero
Signed-off-by: Stefan Weil
---
net/colo-compare.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/net/colo-compare.c b/net/colo-compare.c
ind
Pierrick Bouvier writes:
> On 9/9/24 03:00, Alex Bennée wrote:
>> Pierrick Bouvier writes:
>>
>>> On 9/5/24 08:21, Alex Bennée wrote:
Pierrick Bouvier writes:
> This series allows plugins to know which value is read/written during a
> memory
> access.
>
> For eve
On Mon, Sep 09, 2024 at 07:34:45PM +0800, Changqi Lu wrote:
> +static int coroutine_fn GRAPH_RDLOCK
> +raw_co_pr_register(BlockDriverState *bs, uint64_t old_key,
> + uint64_t new_key, BlockPrType type,
> + bool ptpl, bool ignore_key)
> +{
> +return bdrv_co_pr
From: Bryan Zhang
Adds support for migration parameters to control QATzip compression
level.
Acked-by: Markus Armbruster
Signed-off-by: Bryan Zhang
Signed-off-by: Hao Xiang
Signed-off-by: Yichen Wang
Reviewed-by: Fabiano Rosas
Reviewed-by: Prasad Pandit
Link: https://lore.kernel.org/r/2024
From: Fabiano Rosas
The vmstate-checker-script test has a bug that makes it flaky. It was
also committed by mistake and will be removed.
Since the migration-compat job takes the tests from the build-previous
job instead of the current HEAD, neither a fix or a removal of the
test will take effect
From: Mattias Nissler
When DMA memory can't be directly accessed, as is the case when
running the device model in a separate process without shareable DMA
file descriptors, bounce buffering is used.
It is not uncommon for device models to request mapping of several DMA
regions at the same time.
From: Bryan Zhang
Adds support for 'qatzip' as an option for the multifd compression
method parameter, and implements using QAT for 'qatzip' compression and
decompression.
Acked-by: Markus Armbruster
Reviewed-by: Fabiano Rosas
Reviewed-by: Prasad Pandit
Signed-off-by: Bryan Zhang
Signed-off-
From: "Denis V. Lunev"
Right now migration_throttle() tracepoint lacks very important
important information, i.e. no one could easily say how much the guest
is throttled. This makes difficult to debug guest quality of service
during migration.
This patch adds one more tracepoint into cpu_throttl
The following changes since commit f2aee60305a1e40374b2fc1093e4d04404e780ee:
Merge tag 'pull-request-2024-09-08' of https://gitlab.com/huth/qemu into
staging (2024-09-09 10:47:24 +0100)
are available in the Git repository at:
https://gitlab.com/peterx/qemu.git tags/migration-202
From: Yuan Liu
add Intel QATzip compression method introduction
Reviewed-by: Nanhai Zou
Reviewed-by: Peter Xu
Reviewed-by: Fabiano Rosas
Signed-off-by: Yuan Liu
Signed-off-by: Yichen Wang
Link: https://lore.kernel.org/r/20240830232722.58272-2-yichen.w...@bytedance.com
Signed-off-by: Peter X
From: Bryan Zhang
Add a 'qatzip' feature, which is automatically disabled, and which
depends on the QATzip library if enabled.
Reviewed-by: Fabiano Rosas
Signed-off-by: Bryan Zhang
Signed-off-by: Hao Xiang
Signed-off-by: Yichen Wang
Link: https://lore.kernel.org/r/20240830232722.58272-3-yich
From: David Hildenbrand
As reported by Peter, we might be leaking memory when removing the
highest RAMBlock (in the weird ram_addr_t space), and adding a new one.
We will fail to realize that we already allocated bitmaps for more
dirty memory blocks, and effectively discard the pointers to them.
From: Bryan Zhang
Adds an integration test for 'qatzip'.
Reviewed-by: Fabiano Rosas
Signed-off-by: Bryan Zhang
Signed-off-by: Hao Xiang
Signed-off-by: Yichen Wang
Link: https://lore.kernel.org/r/20240830232722.58272-6-yichen.w...@bytedance.com
Signed-off-by: Peter Xu
---
tests/qtest/migrat
On Tue, Aug 27, 2024 at 07:54:27PM +0200, Maciej S. Szmigiero wrote:
> From: "Maciej S. Szmigiero"
>
> load_finish SaveVMHandler allows migration code to poll whether
> a device-specific asynchronous device state loading operation had finished.
>
> In order to avoid calling this handler needless
On Mon, Sep 02, 2024 at 10:12:01PM +0200, Maciej S. Szmigiero wrote:
> > > diff --git a/migration/multifd.h b/migration/multifd.h
> > > index a3e35196d179..a8f3e4838c01 100644
> > > --- a/migration/multifd.h
> > > +++ b/migration/multifd.h
> > > @@ -45,6 +45,12 @@ MultiFDRecvData *multifd_get_recv_
On Fri, Aug 30, 2024 at 10:02:40AM -0300, Fabiano Rosas wrote:
> >>> @@ -397,20 +404,16 @@ bool multifd_send(MultiFDSendData **send_data)
> >>>
> >>> p = &multifd_send_state->params[i];
> >>> /*
> >>> - * Lockless read to p->pending_job is safe, because only multifd
>
Am 09.09.24 um 09:26 schrieb Marc-André Lureau:
> Hi
>
> On Mon, Sep 9, 2024 at 10:22 AM Volker Rümelin wrote:
>> Windows only:
>>
>> The libSDL2 Windows message loop needs the libSDL2 Windows low
>> level keyboard hook procedure to grab the left and right Windows
>> keys correctly. Reenable the S
On Mon, Sep 09, 2024 at 03:08:40PM -0400, Peter Xu wrote:
> On Mon, Sep 09, 2024 at 08:32:45PM +0200, Maciej S. Szmigiero wrote:
> > On 9.09.2024 19:59, Peter Xu wrote:
> > > On Thu, Sep 05, 2024 at 04:45:48PM +0300, Avihai Horon wrote:
> > > >
> > > > On 27/08/2024 20:54, Maciej S. Szmigiero wrot
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