>-Original Message-
>From: Jason Wang
>Subject: Re: [PATCH v3 15/17] intel_iommu: Modify x-scalable-mode to be
>string option to expose scalable modern mode
>
>On Wed, Sep 11, 2024 at 1:27 PM Zhenzhong Duan
> wrote:
>>
>> From: Yi Liu
>>
>> Intel VT-d 3.0 introduces scalable mode, and i
>-Original Message-
>From: Jason Wang
>Subject: Re: [PATCH v3 14/17] intel_iommu: Set default aw_bits to 48 in
>scalable modern mode
>
>On Wed, Sep 11, 2024 at 1:27 PM Zhenzhong Duan
> wrote:
>>
>> According to VTD spec, stage-1 page table could support 4-level and
>> 5-level paging.
>>
>-Original Message-
>From: Jason Wang
>Subject: Re: [PATCH v3 08/17] intel_iommu: Set accessed and dirty bits
>during first stage translation
>
>On Wed, Sep 11, 2024 at 1:26 PM Zhenzhong Duan
> wrote:
>>
>> From: Clément Mathieu--Drif
>>
>> Signed-off-by: Clément Mathieu--Drif
>> Signe
>-Original Message-
>From: Jason Wang
>Subject: Re: [PATCH v3 04/17] intel_iommu: Flush stage-2 cache in PASID-
>selective PASID-based iotlb invalidation
>
>On Wed, Sep 11, 2024 at 1:26 PM Zhenzhong Duan
> wrote:
>>
>> Per spec 6.5.2.4, PADID-selective PASID-based iotlb invalidation will
Hi Cedric,
> Subject: Re: [PATCH v3 0/6] Support GPIO for AST2700
>
> Hello Jamin,
>
> >> Could you please to add tests in tests/qtest/aspeed_gpio-test.c for
> >> this changes ? At least one with the ast2700-evb machine if possible.
> >>
> >
> > Will add
> Thanks for the effort. I appreciate.
>
When no -l/-a/-c/-d specified, assume -l (list).
Use the same values for SNAPSHOT_LIST/etc constants as the
option chars (lacd), this makes it possible to simplify
option handling a lot, combining cases for 4 options into
one.
Also remove bdrv_oflags handling (only list can use RO mode).
Signed-
Signed-off-by: Michael Tokarev
Reviewed-by: Daniel P. Berrangé
---
qemu-img.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/qemu-img.c b/qemu-img.c
index 1bd88fcf63..9157a6b45d 100644
--- a/qemu-img.c
+++ b/qemu-img.c
@@ -859,8 +859,9 @@ static int img_check(const img_
Add missing long options and --help output.
Signed-off-by: Michael Tokarev
---
qemu-img.c | 34 ++
1 file changed, 26 insertions(+), 8 deletions(-)
diff --git a/qemu-img.c b/qemu-img.c
index 688c01722c..76000c485c 100644
--- a/qemu-img.c
+++ b/qemu-img.c
@@ -4559
Add missing long options and --help output.
Signed-off-by: Michael Tokarev
---
qemu-img.c | 44
1 file changed, 36 insertions(+), 8 deletions(-)
diff --git a/qemu-img.c b/qemu-img.c
index 9157a6b45d..7a111bce72 100644
--- a/qemu-img.c
+++ b/qemu-img.
For consistency with other commands, and since it already
accepts --image-opts, allow specifying -f fmt too.
Signed-off-by: Michael Tokarev
Reviewed-by: Daniel P. Berrangé
---
docs/tools/qemu-img.rst | 2 +-
qemu-img-cmds.hx| 4 ++--
qemu-img.c | 9 ++---
3 files change
Signed-off-by: Michael Tokarev
---
qemu-img.c | 45 +
1 file changed, 37 insertions(+), 8 deletions(-)
diff --git a/qemu-img.c b/qemu-img.c
index 7a111bce72..ea66bfa195 100644
--- a/qemu-img.c
+++ b/qemu-img.c
@@ -1488,25 +1488,52 @@ static int img_com
Add missing long options and --help output.
Also add -s short option for --size (and remove OPTION_SIZE).
Signed-off-by: Michael Tokarev
---
qemu-img.c | 53 -
1 file changed, 40 insertions(+), 13 deletions(-)
diff --git a/qemu-img.c b/qemu-i
Hello Jamin,
Could you please to add tests in tests/qtest/aspeed_gpio-test.c for this
changes ? At least one with the ast2700-evb machine if possible.
Will add
Thanks for the effort. I appreciate.
Also, your emails have an invalid "From" field set to
"qemu-devel@nongnu.org" when retrieved w
This info will be used to generate --help output.
Signed-off-by: Michael Tokarev
Reviewed-by: Daniel P. Berrangé
---
qemu-img.c | 34 +-
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/qemu-img.c b/qemu-img.c
index 130188e287..e8234104e5 100644
--
also add short description to each command and use it in --help
Signed-off-by: Michael Tokarev
Reviewed-by: Daniel P. Berrangé
---
qemu-img.c | 40 ++--
1 file changed, 34 insertions(+), 6 deletions(-)
diff --git a/qemu-img.c b/qemu-img.c
index 39dfaa5144..6
Add missing long options and --help output.
Signed-off-by: Michael Tokarev
---
qemu-img.c | 38 +-
1 file changed, 29 insertions(+), 9 deletions(-)
diff --git a/qemu-img.c b/qemu-img.c
index da10fafffc..688c01722c 100644
--- a/qemu-img.c
+++ b/qemu-img.c
@@ -
cvtnum() expects input string to specify some sort of size
(optionally with KMG... suffix). However, there are a lot
of other number conversions in there (using qemu_strtol &Co),
also, not all conversions which use cvtnum, actually expects
size, - like dd count=nn.
Add bool issize argument to cvt
Initializing an unsigned as -1, or using temporary
sval for conversion is awkward. Since we don't allow
other "negative" values anyway, use signed value and
pass it to bdrv_img_create() (where it is properly
converted to unsigned), simplifying code.
Signed-off-by: Michael Tokarev
Reviewed-by: Da
Add missing long options and --help output.
Signed-off-by: Michael Tokarev
---
qemu-img.c | 38 ++
1 file changed, 30 insertions(+), 8 deletions(-)
diff --git a/qemu-img.c b/qemu-img.c
index 08536553c7..1bd88fcf63 100644
--- a/qemu-img.c
+++ b/qemu-img.c
@@ -
now once all individual subcommands has --help support, remove
the large unreadable help() thing and replace it with small
global --help, which refers to individual command --help for
more info.
While at it, also line-wrap list of formats after 75 chars.
Since missing_argument() and unrecognized_
Add missing long options and --help output.
While at it, remove unused option_index variable.
Signed-off-by: Michael Tokarev
---
qemu-img.c | 34 --
1 file changed, 24 insertions(+), 10 deletions(-)
diff --git a/qemu-img.c b/qemu-img.c
index 34c4cd86de..84e2e53f
Add missing long options and --help output.
Signed-off-by: Michael Tokarev
---
qemu-img.c | 40
1 file changed, 32 insertions(+), 8 deletions(-)
diff --git a/qemu-img.c b/qemu-img.c
index fff537df26..7c20a5772d 100644
--- a/qemu-img.c
+++ b/qemu-img.c
@@
Use common code and simplify error message
Signed-off-by: Michael Tokarev
Reviewed-by: Daniel P. Berrangé
---
qemu-img.c | 63 --
1 file changed, 18 insertions(+), 45 deletions(-)
diff --git a/qemu-img.c b/qemu-img.c
index 7ed5e6d1a8..0853655
Add missing long options and --help output.
Signed-off-by: Michael Tokarev
---
qemu-img.c | 64 +-
1 file changed, 54 insertions(+), 10 deletions(-)
diff --git a/qemu-img.c b/qemu-img.c
index 76000c485c..fff537df26 100644
--- a/qemu-img.c
+++
Add missing long options and --help output.
Signed-off-by: Michael Tokarev
---
qemu-img.c | 45 -
1 file changed, 36 insertions(+), 9 deletions(-)
diff --git a/qemu-img.c b/qemu-img.c
index 967f6343de..62f9ce4069 100644
--- a/qemu-img.c
+++ b/qemu-img
Add missing long options and --help output.
Options added:
--format, --cache - for the image in question
--backing, --backing-format, --backing-cache, --backing-unsafe -
for the new backing file
(was eg CACHE vs SRC_CACHE, which is unclear).
Probably should rename local variables.
Signed-of
Add missing long options and --help output.
Signed-off-by: Michael Tokarev
---
qemu-img.c | 39 +--
1 file changed, 29 insertions(+), 10 deletions(-)
diff --git a/qemu-img.c b/qemu-img.c
index 7c20a5772d..b3e521bc09 100644
--- a/qemu-img.c
+++ b/qemu-img.c
@@
Add missing long options and --help output.
convert uses -B for --backing, - why not -b?
Signed-off-by: Michael Tokarev
---
qemu-img.c | 90 --
1 file changed, 81 insertions(+), 9 deletions(-)
diff --git a/qemu-img.c b/qemu-img.c
index ea66bf
This is a re-send of this patchset from Apr-24, after multiple pings.
I rebased it on top of current qemu/master, though nothing has really
changed - it is still the same changes. We should either apply it or
drop it if it is not appropriate for some reason. Complete silence
for half a year isn't
'qemu-img resize --help' does not work, since it wants more
arguments. Also -size is only recognized as a very last
argument, but it is common for tools to handle other options
after positional arguments too.
Tell getopt_long() to return non-options together with options,
and process filename and
Add missing long options and --help output.
Also add -b short option for --backing-chain, and remove
now-unused OPTION_BACKING_CHAIN.
While at it, remove unused option_index variable.
Signed-off-by: Michael Tokarev
---
qemu-img.c | 40 +++-
1 file changed, 27
qemu_opt_set_number() expects signed int64_t.
Use int64_t instead of uint64_t for img_size, use -1 as "unset"
value instead of UINT64_MAX, and do not require temporary sval
for conversion from string.
Signed-off-by: Michael Tokarev
Reviewed-by: Daniel P. Berrangé
---
qemu-img.c | 19 +++---
Create helper function cmd_help() to display command-specific
help text, and use it to print --help for 'create' subcommand.
Add missing long options (eg --format) in img_create().
Remove usage of missing_argument()/unrecognized_option() in
img_create().
Signed-off-by: Michael Tokarev
---
qemu
On Wed, Sep 11, 2024 at 1:26 PM Zhenzhong Duan wrote:
>
> From: Clément Mathieu--Drif
>
> Signed-off-by: Clément Mathieu--Drif
> Signed-off-by: Zhenzhong Duan
> ---
> hw/i386/intel_iommu_internal.h | 3 +++
> hw/i386/intel_iommu.c | 25 -
> 2 files changed, 27
On Wed, Sep 11, 2024 at 1:27 PM Zhenzhong Duan wrote:
>
> From: Clément Mathieu--Drif
>
> Signed-off-by: Clément Mathieu--Drif
> Signed-off-by: Zhenzhong Duan
> ---
> hw/i386/intel_iommu_internal.h | 11
> hw/i386/intel_iommu.c | 50 ++
> 2 fil
On Wed, Sep 11, 2024 at 1:26 PM Zhenzhong Duan wrote:
>
> From: Clément Mathieu--Drif
>
> This will be used to implement the device IOTLB invalidation
>
> Signed-off-by: Clément Mathieu--Drif
> Signed-off-by: Zhenzhong Duan
> ---
Acked-by: Jason Wang
Thanks
On Wed, Sep 11, 2024 at 1:27 PM Zhenzhong Duan wrote:
>
> According to VTD spec, stage-1 page table could support 4-level and
> 5-level paging.
>
> However, 5-level paging translation emulation is unsupported yet.
> That means the only supported value for aw_bits is 48.
>
> So default aw_bits to 4
On Wed, Sep 11, 2024 at 1:27 PM Zhenzhong Duan wrote:
>
> This gives user flexibility to turn off FS1GP for debug purpose.
>
> It is also useful for future nesting feature. When host IOMMU doesn't
> support FS1GP but vIOMMU does, nested page table on host side works
> after turn FS1GP off in vIOMM
On Wed, Sep 11, 2024 at 1:26 PM Zhenzhong Duan wrote:
>
> According to spec, Page-Selective-within-Domain Invalidation (11b):
>
> 1. IOTLB entries caching second-stage mappings (PGTT=010b) or pass-through
> (PGTT=100b) mappings associated with the specified domain-id and the
> input-address range
On Wed, Sep 11, 2024 at 1:27 PM Zhenzhong Duan wrote:
>
> From: Yi Liu
>
> Intel VT-d 3.0 introduces scalable mode, and it has a bunch of capabilities
> related to scalable mode translation, thus there are multiple combinations.
> While this vIOMMU implementation wants to simplify it for user by
On Wed, Sep 11, 2024 at 1:26 PM Zhenzhong Duan wrote:
>
> PASID-based iotlb (piotlb) is used during walking Intel
> VT-d stage-1 page table.
>
> This emulates the stage-1 page table iotlb invalidation requested
> by a PASID-based IOTLB Invalidate Descriptor (P_IOTLB).
>
> Signed-off-by: Yi Liu
>
On Wed, Sep 11, 2024 at 1:27 PM Zhenzhong Duan wrote:
>
> Add the framework to test the intel-iommu device.
>
> Currently only tested cap/ecap bits correctness in scalable
> modern mode. Also tested cap/ecap bits consistency before
> and after system reset.
>
> Signed-off-by: Zhenzhong Duan
> Ack
On Wed, Sep 11, 2024 at 1:26 PM Zhenzhong Duan wrote:
>
> From: Yi Liu
>
> This adds stage-1 page table walking to support stage-1 only
> transltion in scalable modern mode.
>
> Signed-off-by: Yi Liu
> Co-developed-by: Clément Mathieu--Drif
> Signed-off-by: Clément Mathieu--Drif
> Signed-off-b
On Wed, Sep 11, 2024 at 1:26 PM Zhenzhong Duan wrote:
>
> From: Clément Mathieu--Drif
>
> First stage translation must fail if the address to translate is
> not canonical.
>
> Signed-off-by: Clément Mathieu--Drif
> Signed-off-by: Zhenzhong Duan
> ---
Acked-by: Jason Wang
Thanks
On Wed, Sep 11, 2024 at 1:26 PM Zhenzhong Duan wrote:
>
> From: Yi Liu
>
> Because we will support both FST(a.k.a, FLT) and SST(a.k.a, SLT) translation,
> rename variable and functions from slpte to pte whenever possible.
>
> But some are SST only, they are renamed with sl_ prefix.
>
> Signed-off
On Wed, Sep 11, 2024 at 1:26 PM Zhenzhong Duan wrote:
>
> Per spec 6.5.2.4, PADID-selective PASID-based iotlb invalidation will
> flush stage-2 iotlb entries with matching domain id and pasid.
>
> With scalable modern mode introduced, guest could send PASID-selective
> PASID-based iotlb invalidati
From: Jared Rossi
Remove panic-on-error from IPL functions such that a return code is propagated
back to the main IPL calling function (rather than terminating immediately),
which facilitates possible error recovery in the future.
A select few panics remain, which indicate fatal non-devices erro
Hi Andrew,
>
> On Thu, 2024-09-26 at 15:45 +0800, Jamin Lin wrote:
> > AST2700 integrates two set of Parallel GPIO Controller with maximum
> > 212 control pins, which are 27 groups.
> > (H, exclude pin: H7 H6 H5 H4)
> >
> > In the previous design of ASPEED SOCs, one register is used for
> > setti
Alex Bennée writes:
[snip]
>
> Another potential area for conversion was the VirtIO device and
> vhost-user code which could expect to re-use a lot of the crates from
> the rust-vmm project. However this did bring up the point of maintainer
> buy in. Stefan brought up the example of the simple
On Fri, Sep 27, 2024 at 3:55 AM Peter Xu wrote:
> On Fri, Sep 27, 2024 at 02:13:47AM +0800, Yong Huang wrote:
> > On Thu, Sep 26, 2024 at 3:17 AM Peter Xu wrote:
> >
> > > On Fri, Sep 20, 2024 at 10:43:31AM +0800, Yong Huang wrote:
> > > > Yes, invoke migration_bitmap_sync_precopy more frequentl
On Thu, 2024-09-26 at 15:45 +0800, Jamin Lin wrote:
> The interrupt status field is W1C, where a set bit on read indicates an
> interrupt is pending. If the bit extracted from data is set it should
> clear the corresponding bit in group_value. However, if the extracted
> bit is clear then the value
Hi Cedric,
> Subject: Re: [PATCH v3 6/6] aspeed/soc: Support GPIO for AST2700
>
> On 9/26/24 09:45, Jamin Lin wrote:
> > Add GPIO model for AST2700 GPIO support.
> > The GPIO controller registers base address is start at
> > 0x14C0_B000 and its address space is 0x1000.
> >
> > The AST2700 GPIO co
Hi Cedric,
> Subject: Re: [PATCH v3 0/6] Support GPIO for AST2700
>
> Hello Jamin,
>
> On 9/26/24 09:45, Jamin Lin wrote:
> > v1: Support GPIO for AST2700
> > v2: Fix clear incorrect interrupt status and adds reviewer suggestions
> > v3: remove nested conditionals and adds reviewer suggestions
>
On Thu, 2024-09-26 at 15:45 +0800, Jamin Lin wrote:
> AST2700 integrates two set of Parallel GPIO Controller
> with maximum 212 control pins, which are 27 groups.
> (H, exclude pin: H7 H6 H5 H4)
>
> In the previous design of ASPEED SOCs,
> one register is used for setting one function for one set
Hi Andres,
> Subject: Re: [PATCH v3 4/6] hw/gpio/aspeed: Fix clear incorrect interrupt
> status
> for GPIO index mode
>
> On Thu, 2024-09-26 at 15:45 +0800, Jamin Lin wrote:
> > The interrupt status field is W1C, where a set bit on read indicates
> > an interrupt is pending. If the bit extracted
From: Jared Rossi
We are going to link the SLOF libc into the s390-ccw.img, and this
libc needs more memory for providing space for malloc() and friends.
Thus bump the memory size that we reserve for the bios to 3 MiB
instead of only 2 MiB. While we're at it, add a proper check that
there is real
From: Jared Rossi
Now that the netboot code has been merged into the main s390-ccw.img,
it also does not make sense to keep the build rules in a separate
file. Thus let's merge netboot.mak into the main Makefile.
Co-authored by: Thomas Huth
Signed-off-by: Jared Rossi
---
pc-bios/s390-ccw/net
On Wed, Sep 11, 2024 at 1:26 PM Zhenzhong Duan wrote:
>
> When guest configures Nested Translation(011b) or First-stage Translation only
> (001b), type check passed unaccurately.
>
> Fails the type check in those cases as their simulation isn't supported yet.
>
> Fixes: fb43cf739e1 ("intel_iommu:
From: Jared Rossi
Allow attempts to boot from multiple IPL devices. If the first device fails to
IPL, select the pre-built IPLB for the next device in the boot order and attempt
to IPL from it. Continue this process until IPL is successful or there are no
devices left to try.
Signed-off-by: Jare
From: Jared Rossi
Update docs to show that s390x PC BIOS can support more than one boot device.
Signed-off-by: Jared Rossi
---
docs/system/bootindex.rst | 7 ---
docs/system/s390x/bootdevices.rst | 9 ++---
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/docs/s
On Fri, Sep 27, 2024 at 12:34:31AM +0200, Maciej S. Szmigiero wrote:
> On 20.09.2024 18:45, Peter Xu wrote:
> > On Fri, Sep 20, 2024 at 05:23:08PM +0200, Maciej S. Szmigiero wrote:
> > > On 19.09.2024 23:11, Peter Xu wrote:
> > > > On Thu, Sep 19, 2024 at 09:49:10PM +0200, Maciej S. Szmigiero wrote
From: Jared Rossi
Remove panic-on-error from IPL ISO El Torito specific functions so that error
recovery may be possible in the future.
Functions that would previously panic now provide a return code.
Signed-off-by: Jared Rossi
---
pc-bios/s390-ccw/bootmap.h | 17 +++---
pc-bios/s390-cc
From: Jared Rossi
Remove the information about the separate s390-netboot.img from
the documentation.
Co-authored by: Thomas Huth
Signed-off-by: Jared Rossi
---
docs/system/s390x/bootdevices.rst | 20 +++-
1 file changed, 7 insertions(+), 13 deletions(-)
diff --git a/docs/sys
From: Jared Rossi
Remove panic-on-error from ECKD block device IPL specific functions so that
error recovery may be possible in the future.
Functions that would previously panic now provide a return code.
Signed-off-by: Jared Rossi
---
pc-bios/s390-ccw/bootmap.c | 183 +++
From: Jared Rossi
We are already using the libc from SLOF for the s390-netboot.img, and
this libc implementation is way more complete and accurate than the
simple implementation that we currently use for the s390-ccw.img binary.
Since we are now always assuming that the SLOF submodule is availabl
From: Jared Rossi
Remove panic-on-error from virtio-scsi IPL specific functions so that error
recovery may be possible in the future.
Functions that would previously panic now provide a return code.
Signed-off-by: Jared Rossi
---
pc-bios/s390-ccw/bootmap.c | 88 +++-
pc-
From: Jared Rossi
We originally built a separate binary for the netboot code since it
was considered as experimental and we could not be sure that the
necessary SLOF module had been checked out. Time passed, the code
proved its usefulness, and the build system nowadays makes sure that
the SLOF mo
From: Jared Rossi
Remove panic-on-error from DASD IPL specific functions so that error recovery
may be possible in the future.
Functions that would previously panic now provide a return code.
Signed-off-by: Jared Rossi
---
pc-bios/s390-ccw/dasd-ipl.h | 2 +-
pc-bios/s390-ccw/dasd-ipl.c | 66
From: Jared Rossi
Currently, structures defined in both hw/s390x/ipl.h and pc-bios/s390-ccw/iplb.h
must be kept in sync, which is prone to error. Instead, create a new directory
at include/hw/s390x/ipl/ to contain the definitions that must be shared.
Signed-off-by: Jared Rossi
---
hw/s390x/ip
From: Jared Rossi
Because virtio-scsi type devices use a non-architected IPLB pbt code they cannot
be set and stored normally. Instead, the IPLB must be rebuilt during re-ipl.
As s390x does not natively support multiple boot devices, the devno field is
used to store the position in the boot orde
From: Jared Rossi
Add a loadparm property to the VirtioCcwDevice object so that different
loadparms can be defined on a per-device basis for CCW boot devices.
The machine/global loadparm is still supported. If both a global and per-device
loadparm are defined, the per-device value will override
On Wed, Sep 11, 2024 at 1:26 PM Zhenzhong Duan wrote:
>
> Add an new element scalable_mode in IntelIOMMUState to mark scalable
> modern mode, this element will be exposed as an intel_iommu property
> finally.
>
> For now, it's only a placehholder and used for address width
> compatibility check an
From: Jared Rossi
Remove panic-on-error from Netboot specific functions so that error recovery
may be possible in the future.
Functions that would previously panic now provide a return code.
Signed-off-by: Jared Rossi
---
pc-bios/s390-ccw/s390-ccw.h | 2 +-
pc-bios/s390-ccw/bootmap.c|
From: Jared Rossi
Since the netboot code has now been merged into the main s390-ccw.img
binary, we don't need the separate s390-netboot.img anymore. Remove
it and the code that was responsible for loading it.
Co-authored by: Thomas Huth
Signed-off-by: Jared Rossi
---
hw/s390x/ipl.h
From: Jared Rossi
Build an IPLB for any device with a bootindex (up to a maximum of 8 devices).
The IPLB chain is placed immediately before the BIOS in memory. Because this
is not a fixed address, the location of the next IPLB and number of remaining
boot devices is stored in the QIPL global var
From: Jared Rossi
Loosely a v2, this updated patch set is a significant rework to most aspects of
the initially proposed multi-device boot order. Of particular note, the
original patch set used code jumps to restart the IPL while this version
does not. In order to remove the code jumps, two signi
On Wed, Sep 11, 2024 at 1:26 PM Zhenzhong Duan wrote:
>
> From: Yu Zhang
>
> Spec revision 3.0 or above defines more detailed fault reasons for
> scalable mode. So introduce them into emulation code, see spec
> section 7.1.2 for details.
>
> Note spec revision has no relation with VERSION registe
On 20.09.2024 18:45, Peter Xu wrote:
On Fri, Sep 20, 2024 at 05:23:08PM +0200, Maciej S. Szmigiero wrote:
On 19.09.2024 23:11, Peter Xu wrote:
On Thu, Sep 19, 2024 at 09:49:10PM +0200, Maciej S. Szmigiero wrote:
On 9.09.2024 22:03, Peter Xu wrote:
On Tue, Aug 27, 2024 at 07:54:27PM +0200, Mac
On 9/19/24 2:50 AM, LIU Zhiwei wrote:
make check-avocado AVOCADO_TESTS=tests/avocado/tuxrun_baselines.py: \
TuxRunBaselineTest:test_riscv64_rv32
Signed-off-by: LIU Zhiwei
Suggested-by: Daniel Henrique Barboza
---
Reviewed-by: Daniel Henrique Barboza
tests/avocado/tuxrun_baselines.py
On 9/19/24 2:50 AM, LIU Zhiwei wrote:
We may need 32-bit max for RV64 QEMU. Thus we add these two CPUs
for RV64 QEMU.
The reason we don't expose them to RV32 QEMU is that we already have
max cpu with the same configuration. Another reason is that we want
to follow the RISC-V custom where addw
Adds support for the controller atomic parameters: AWUN and AWUPF. Atomic
Compare and Write Unit (ACWU) is not currently supported.
Writes that adhere to the ACWU and AWUPF parameters are guaranteed to be atomic.
New NVMe QEMU Parameters (See NVMe Specification for details):
atomic.dn (def
Changelog:
v3: - Use cpu_to_le16() to properly handle endianness.
- Use 'continue' rather than'break' when walking SQs.
- No need to lock all the SQs when walking them so remove atomic_lock
since it is running from the main loop.
v2: - Include changes suggested by
On Thu, 26 Sept 2024 at 18:05, Chao Liu wrote:
>
> > The ignore_memory_transaction_failures is used for compatibility
> > with legacy board models.
> >
> > I attempted to remove this property from the
> > xilink_zynq board and replace it with unimplemented devices to
> > handle devices that are no
On Fri, Sep 27, 2024 at 02:13:47AM +0800, Yong Huang wrote:
> On Thu, Sep 26, 2024 at 3:17 AM Peter Xu wrote:
>
> > On Fri, Sep 20, 2024 at 10:43:31AM +0800, Yong Huang wrote:
> > > Yes, invoke migration_bitmap_sync_precopy more frequently is also my
> > > first idea but it involves bitmap updati
On 9/26/24 09:45, Jamin Lin wrote:
According to the datasheet of ASPEED SOCs,
a GPIO controller owns 4KB of register space for AST2700,
AST2500, AST2400 and AST1030; owns 2KB of register space
for AST2600 1.8v and owns 2KB of register space for AST2600 3.3v.
It set the memory region size 2KB by
On Thu, Sep 26, 2024 at 3:17 AM Peter Xu wrote:
> On Fri, Sep 20, 2024 at 10:43:31AM +0800, Yong Huang wrote:
> > Yes, invoke migration_bitmap_sync_precopy more frequently is also my
> > first idea but it involves bitmap updating and interfere with the
> behavior
> > of page sending, it also affe
On 9/24/24 5:15 AM, Klaus Jensen wrote:
On Sep 19 17:07, Alan Adamson wrote:
Adds support for the controller atomic parameters: AWUN and AWUPF. Atomic
Compare and Write Unit (ACWU) is not currently supported.
Writes that adhere to the ACWU and AWUPF parameters are guaranteed to be atomic.
Ne
> The ignore_memory_transaction_failures is used for compatibility
> with legacy board models.
>
> I attempted to remove this property from the
> xilink_zynq board and replace it with unimplemented devices to
> handle devices that are not implemented on the board.
>
> Chao Liu (2):
> xilink_z
> The ignore_memory_transaction_failures is used for compatibility
> with legacy board models.
>
> I attempted to remove this property from the
> xilink_zynq board and replace it with unimplemented devices to
> handle devices that are not implemented on the board.
>
> Chao Liu (2):
> xilink_z
Hello Zhi,
On 9/21/24 09:14, Zhi Wang wrote:
Compute Express Link (CXL) is an open standard interconnect built upon
industrial PCI layers to enhance the performance and efficiency of data
centers by enabling high-speed, low-latency communication between CPUs
and various types of devices such as
On Thu, Sep 26, 2024 at 03:23:11PM +0100, Alex Bennée wrote:
> During the various conversations I didn't hear anyone speak against the
> proposed migration although some concerns where raised about review and
> knowledge gaps.
Yep, this apparent broad acceptance (or at least tolerance) for use of
On 9/26/24 09:45, Jamin Lin wrote:
It set "aspeed_gpio_ops" struct which containing
read and write callbacks to be used when I/O is performed
on the GPIO region.
Besides, in the previous design of ASPEED SOCs,
one register is used for setting one function for 32 GPIO pins.
ex: GPIO000 is used fo
Hello Jamin,
On 9/26/24 09:45, Jamin Lin wrote:
v1: Support GPIO for AST2700
v2: Fix clear incorrect interrupt status and adds reviewer suggestions
v3: remove nested conditionals and adds reviewer suggestions
Jamin Lin (6):
hw/gpio/aspeed: Fix coding style
hw/gpio/aspeed: Support to set t
Hi Cornelia and Ganapatrao,
On 9/25/24 14:54, Cornelia Huck wrote:
On Fri, Sep 20 2024, Ganapatrao Kulkarni
wrote:
Mostly nit-picking below, otherwise LGTM.
Extend the 'mte' property for the virt machine to cover KVM as
well. For KVM, we don't allocate tag memory, but instead enable
the cap
On 9/26/24 09:45, Jamin Lin wrote:
Add GPIO model for AST2700 GPIO support.
The GPIO controller registers base address is start at
0x14C0_B000 and its address space is 0x1000.
The AST2700 GPIO controller interrupt is connected to
GICINT130_INTC at bit 18.
Signed-off-by: Jamin Lin
---> hw/arm
On 9/26/24 09:45, Jamin Lin wrote:
Fix coding style issues from checkpatch.pl
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/gpio/aspeed_gpio.c | 6 +++---
include/hw/gpio/aspeed_gpio.h | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff
Hi Ganapatrao,
On 9/25/24 19:40, Ganapatrao Kulkarni wrote:
Hi Gustavo,
On 25-09-2024 09:17 pm, Gustavo Romero wrote:
Hi Ganapatrao,
Sorry for the delay on replying it. I was attending KVM Forum and
commuting.
On 9/20/24 09:37, Ganapatrao Kulkarni wrote:
Extend the 'mte' property for the
On Thu, 26 Sept 2024 at 10:24, Alex Bennée wrote:
> What are candidates for conversion?
"Conversion" means "rewrite in Rust" to me. There are other ways of
integrating Rust without converting existing code:
- Writing new subsystems in Rust where there is no existing C code.
- Adding Rust binding
On 9/26/24 4:59 AM, Bernhard Beschow wrote:
Signed-off-by: Bernhard Beschow
---
Reviewed-by: Daniel Henrique Barboza
MAINTAINERS | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index ffacd60f40..0a191a03db 100644
--- a/MAINTAINERS
++
Em Thu, 26 Sep 2024 13:09:09 +0100
Jonathan Cameron escreveu:
> On Wed, 25 Sep 2024 06:04:17 +0200
> Mauro Carvalho Chehab wrote:
>
> > Instead, produce an error and continue working
> >
> > Signed-off-by: Mauro Carvalho Chehab
> Make sense as defense in depth. Can we actually hit this for
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