From: David Reiss
Follows a fairly similar pattern to the existing special register debug
support. Only reading is implemented, but it should be possible to
implement writes.
Signed-off-by: David Reiss
---
target/arm/cpu.h | 15 +-
target/arm/gdbstub.c | 116
New in v4: Moved arm_v7m_mrs_control out of the `#ifdef
CONFIG_USER_ONLY` block, unbreaking the user-only build. The downside
is that this function is now taking up space in the user-only binary,
but it can (presumably?) never be used because there are no user modes
for v8m cores. Let me know if
From: David Reiss
Follows a fairly similar pattern to the existing special register debug
support. Only reading is implemented, but it should be possible to
implement writes.
`v7m_mrs_control` was renamed `arm_v7m_mrs_control` and made
non-static so this logic could be shared between the MRS
Rebased and updated to use NULL as a sentinel.
David Reiss (2):
target/arm/gdbstub: Support reading M system registers from GDB
target/arm/gdbstub: Support reading M security extension registers
from GDB
target/arm/cpu.h | 25 +++-
target/arm/gdbstub.c | 241
From: David Reiss
Follows a fairly similar pattern to the existing special register debug
support. Only reading is implemented, but it should be possible to
implement writes.
`v7m_mrs_control` was renamed `arm_v7m_mrs_control` and made
non-static so this logic could be shared between the MRS
From: David Reiss
Follows a fairly similar pattern to the existing special register debug
support. Only reading is implemented, but it should be possible to
implement writes.
Signed-off-by: David Reiss
---
target/arm/cpu.h | 15 +-
target/arm/gdbstub.c | 116
From: David Reiss
BASEPRI, FAULTMASK, and their _NS equivalents only exist on devices with
the Main Extension. However, the MRS instruction did not check this,
and the MSR instruction handled it inconsistently (warning BASEPRI, but
silently ignoring writes to BASEPRI_NS). Unify this behavior
From: David Reiss
Follows a fairly similar pattern to the existing special register debug
support. Only reading is implemented, but it should be possible to
implement writes.
`v7m_mrs_control` was renamed `arm_v7m_mrs_control` and made
non-static so this logic could be shared between the MRS
From: David Reiss
Follows a fairly similar pattern to the existing special register debug
support. Only reading is implemented, but it should be possible to
implement writes.
Signed-off-by: David Reiss
---
target/arm/cpu.h | 15 +-
target/arm/gdbstub.c | 116
Patch 1/3 was already accepted, but it seems is not in master yet.
Comments addressed in patches 2 and 3.
Let me know if you'd like me to split out a separate commit
for renaming arm_v7m_get_sp_ptr.
David Reiss (3):
target/arm: Unify checking for M Main Extension in MRS/MSR
From: David Reiss
Follows a fairly similar pattern to the existing special register debug
support. Only reading is implemented, but it should be possible to
implement writes.
Signed-off-by: David Reiss
---
target/arm/cpu.h | 4 +-
target/arm/gdbstub.c | 149
From: David Reiss
Follows a fairly similar pattern to the existing special register debug
support. Only reading is implemented, but it should be possible to
implement writes.
`v7m_mrs_control` was renamed `arm_v7m_mrs_control` and made
non-static so this logic could be shared between the MRS
From: David Reiss
BASEPRI, FAULTMASK, and their _NS equivalents only exist on devices with
the Main Extension. However, the MRS instruction did not check this,
and the MSR instruction handled it inconsistently (warning BASEPRI, but
silently ignoring writes to BASEPRI_NS). Unify this behavior
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