[PATCH qemu v6 05/10] target/riscv: rvv: Add mask agnostic for vector integer comparison instructions

From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/insn_trans/trans_rvv.c.inc | 1 + target/riscv/vector_helper.c| 10 ++ 2 files changed, 11 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.i

[PATCH qemu v6 08/10] target/riscv: rvv: Add mask agnostic for vector mask instructions

From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/insn_trans/trans_rvv.c.inc | 3 +++ target/riscv/vector_helper.c| 11 +++ 2 files changed, 14 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.

[PATCH qemu v6 09/10] target/riscv: rvv: Add mask agnostic for vector permutation instructions

From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/insn_trans/trans_rvv.c.inc | 1 + target/riscv/vector_helper.c| 26 +++-- 2 files changed, 25 insertions(+), 2 deletions(-) diff --git a/target

[PATCH qemu v6 01/10] target/riscv: rvv: Add mask agnostic for vv instructions

From: Yueh-Ting (eop) Chen According to v-spec, mask agnostic behavior can be either kept as undisturbed or set elements' bits to all 1s. To distinguish the difference of mask policies, QEMU should be able to simulate the mask agnostic behavior as "set mask elements' bits to all 1s". There are m

[PATCH qemu v6 00/10] Add mask agnostic behavior for rvv instructions

fix-point arithmetic instructions target/riscv: rvv: Add mask agnostic for vector floating-point instructions target/riscv: rvv: Add mask agnostic for vector mask instructions target/riscv: rvv: Add mask agnostic for vector permutation instructions eopXD (1): target/riscv: rvv: Add optio

[PATCH qemu v6 06/10] target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic instructions

From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/vector_helper.c | 26 -- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c inde

[PATCH qemu v6 10/10] target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable optional mask agnostic behavior

From: eopXD According to v-spec, mask agnostic behavior can be either kept as undisturbed or set elements' bits to all 1s. To distinguish the difference of mask policies, QEMU should be able to simulate the mask agnostic behavior as "set mask elements' bits to all 1s".

[PATCH qemu v6 02/10] target/riscv: rvv: Add mask agnostic for vector load / store instructions

From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/insn_trans/trans_rvv.c.inc | 5 target/riscv/vector_helper.c| 35 + 2 files changed, 29 insertions(+), 11 deletions(-) diff --git a/ta

[PATCH qemu v6 03/10] target/riscv: rvv: Add mask agnostic for vx instructions

From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/insn_trans/trans_rvv.c.inc | 2 ++ target/riscv/vector_helper.c| 3 +++ 2 files changed, 5 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/tar

[PATCH qemu v6 07/10] target/riscv: rvv: Add mask agnostic for vector floating-point instructions

From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/insn_trans/trans_rvv.c.inc | 12 target/riscv/vector_helper.c| 26 + 2 files changed, 38 insertions(+) diff --git a/target/risc

[PATCH qemu v6 04/10] target/riscv: rvv: Add mask agnostic for vector integer shift instructions

From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/insn_trans/trans_rvv.c.inc | 1 + target/riscv/vector_helper.c| 7 +++ 2 files changed, 8 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/

[PATCH qemu v19 12/16] target/riscv: rvv: Add tail agnostic for vector floating-point instructions

From: eopXD Compares write mask registers, and so always operate under a tail- agnostic policy. Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 17 + target/riscv/vector_helper.c

[PATCH qemu v19 10/16] target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 12 target/riscv/vector_helper.c| 20 2 files changed, 28 insertions(+), 4 deletions

[PATCH qemu v19 07/16] target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions

From: eopXD `vmadc` and `vmsbc` produces a mask value, they always operate with a tail agnostic policy. Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 13 +- target/riscv/internals.h

[PATCH qemu v19 16/16] target/riscv: rvv: Add option 'rvv_ta_all_1s' to enable optional tail agnostic behavior

From: eopXD According to v-spec, tail agnostic behavior can be either kept as undisturbed or set elements' bits to all 1s. To distinguish the difference of tail policies, QEMU should be able to simulate the tail agnostic behavior as "set tail elements' bits to all 1s".

[PATCH qemu v19 15/16] target/riscv: rvv: Add tail agnostic for vector permutation instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 7 +++-- target/riscv/vector_helper.c| 40 + 2 files changed, 45 insertions(+), 2 deletions

[PATCH qemu v19 09/16] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions

From: eopXD Compares write mask registers, and so always operate under a tail- agnostic policy. Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis --- target/riscv/vector_helper.c | 18 ++ 1 file changed, 18 insertions

[PATCH qemu v19 11/16] target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis --- target/riscv/vector_helper.c | 220 ++- 1 file changed, 114 insertions(+), 106 deletions(-) diff --git a/target/riscv/vector_helper.c b/target

[PATCH qemu v19 04/16] target/riscv: rvv: Early exit when vstart >= vl

From: eopXD According to v-spec (section 5.4): When vstart ≥ vl, there are no body elements, and no elements are updated in any destination vector register group, including that no tail elements are updated with agnostic values. vmsbf.m, vmsif.m, vmsof.m, viota.m, vcompress instructions

[PATCH qemu v19 14/16] target/riscv: rvv: Add tail agnostic for vector mask instructions

From: eopXD The tail elements in the destination mask register are updated under a tail-agnostic policy. Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 6 + target/riscv/vector_helper.c

[PATCH qemu v19 06/16] target/riscv: rvv: Add tail agnostic for vector load / store instructions

From: eopXD Destination register of unit-stride mask load and store instructions are always written with a tail-agnostic policy. A vector segment load / store instruction may contain fractional lmul with nf * lmul > 1. The rest of the elements in the last register should be treated as t

[PATCH qemu v19 08/16] target/riscv: rvv: Add tail agnostic for vector integer shift instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 3 ++- target/riscv/vector_helper.c| 11 +++ 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a

[PATCH qemu v19 05/16] target/riscv: rvv: Add tail agnostic for vv instructions

From: eopXD According to v-spec, tail agnostic behavior can be either kept as undisturbed or set elements' bits to all 1s. To distinguish the difference of tail policies, QEMU should be able to simulate the tail agnostic behavior as "set tail elements' bits to all 1s".

[PATCH qemu v19 13/16] target/riscv: rvv: Add tail agnostic for vector reduction instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis --- target/riscv/vector_helper.c | 20 1 file changed, 20 insertions(+) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index

[PATCH qemu v19 00/16] Add tail agnostic behavior for rvv instructions

e functions. v18 updates: - Don't use `is_load` parameter in vector helper. Don't let vta pass through in `trans_rvv.inc` v19 updates: - Tag Alistair as Reviewed by for commit 02 - Rebase to alistair23/qemu/riscv-to-apply.next eopXD (16): target/riscv: rvv: Prune redundant ESZ, DSZ p

[PATCH qemu v19 03/16] target/riscv: rvv: Rename ambiguous esz

From: eopXD No functional change intended in this commit. Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/vector_helper.c | 76 ++-- 1 file changed, 38 insertions(+), 38 deletions

[PATCH qemu v19 02/16] target/riscv: rvv: Prune redundant access_type parameter passed

From: eopXD No functional change intended in this commit. Signed-off-by: eop Chen Reviewed-by: Alistair Francis --- target/riscv/vector_helper.c | 35 --- 1 file changed, 16 insertions(+), 19 deletions(-) diff --git a/target/riscv/vector_helper.c b/target

[PATCH qemu v19 01/16] target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed

From: eopXD No functional change intended in this commit. Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/vector_helper.c | 1132 +- 1 file changed, 565 insertions(+), 567 deletions

[PATCH qemu v5 07/10] target/riscv: rvv: Add mask agnostic for vector floating-point instructions

From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/insn_trans/trans_rvv.c.inc | 12 target/riscv/vector_helper.c| 26 + 2 files changed, 38 insertions(+) diff --git a/target/risc

[PATCH qemu v5 06/10] target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic instructions

From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/vector_helper.c | 26 -- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c inde

[PATCH qemu v5 05/10] target/riscv: rvv: Add mask agnostic for vector integer comparison instructions

From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/insn_trans/trans_rvv.c.inc | 1 + target/riscv/vector_helper.c| 10 ++ 2 files changed, 11 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.i

[PATCH qemu v5 10/10] target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable optional mask agnostic behavior

From: eopXD According to v-spec, mask agnostic behavior can be either kept as undisturbed or set elements' bits to all 1s. To distinguish the difference of mask policies, QEMU should be able to simulate the mask agnostic behavior as "set mask elements' bits to all 1s".

[PATCH qemu v5 02/10] target/riscv: rvv: Add mask agnostic for vector load / store instructions

From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/insn_trans/trans_rvv.c.inc | 5 target/riscv/vector_helper.c| 35 + 2 files changed, 29 insertions(+), 11 deletions(-) diff --git a/ta

[PATCH qemu v5 08/10] target/riscv: rvv: Add mask agnostic for vector mask instructions

From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/insn_trans/trans_rvv.c.inc | 3 +++ target/riscv/vector_helper.c| 11 +++ 2 files changed, 14 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.

[PATCH qemu v5 09/10] target/riscv: rvv: Add mask agnostic for vector permutation instructions

From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/insn_trans/trans_rvv.c.inc | 1 + target/riscv/vector_helper.c| 26 +++-- 2 files changed, 25 insertions(+), 2 deletions(-) diff --git a/target

[PATCH qemu v5 00/10] Add mask agnostic behavior for rvv instructions

vv: Add mask agnostic for vector fix-point arithmetic instructions target/riscv: rvv: Add mask agnostic for vector floating-point instructions target/riscv: rvv: Add mask agnostic for vector mask instructions target/riscv: rvv: Add mask agnostic for vector permutation instructions

[PATCH qemu v5 03/10] target/riscv: rvv: Add mask agnostic for vx instructions

From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/insn_trans/trans_rvv.c.inc | 2 ++ target/riscv/vector_helper.c| 3 +++ 2 files changed, 5 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/tar

[PATCH qemu v5 01/10] target/riscv: rvv: Add mask agnostic for vv instructions

From: Yueh-Ting (eop) Chen According to v-spec, mask agnostic behavior can be either kept as undisturbed or set elements' bits to all 1s. To distinguish the difference of mask policies, QEMU should be able to simulate the mask agnostic behavior as "set mask elements' bits to all 1s". There are m

[PATCH qemu v5 04/10] target/riscv: rvv: Add mask agnostic for vector integer shift instructions

From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/insn_trans/trans_rvv.c.inc | 1 + target/riscv/vector_helper.c| 7 +++ 2 files changed, 8 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/

[PATCH qemu v4 10/10] target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable optional mask agnostic behavior

From: eopXD According to v-spec, mask agnostic behavior can be either kept as undisturbed or set elements' bits to all 1s. To distinguish the difference of mask policies, QEMU should be able to simulate the mask agnostic behavior as "set mask elements' bits to all 1s".

[PATCH qemu v4 07/10] target/riscv: rvv: Add mask agnostic for vector floating-point instructions

From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/insn_trans/trans_rvv.c.inc | 12 target/riscv/vector_helper.c| 26 + 2 files changed, 38 insertions(+) diff --git a/target/risc

[PATCH qemu v4 00/10] Add mask agnostic behavior for rvv instructions

ctions target/riscv: rvv: Add mask agnostic for vector floating-point instructions target/riscv: rvv: Add mask agnostic for vector mask instructions target/riscv: rvv: Add mask agnostic for vector permutation instructions eopXD (1): target/riscv: rvv: Add option 'rvv_ma_all

[PATCH qemu v4 09/10] target/riscv: rvv: Add mask agnostic for vector permutation instructions

From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/insn_trans/trans_rvv.c.inc | 1 + target/riscv/vector_helper.c| 26 +++-- 2 files changed, 25 insertions(+), 2 deletions(-) diff --git a/target

[PATCH qemu v4 03/10] target/riscv: rvv: Add mask agnostic for vx instructions

From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/insn_trans/trans_rvv.c.inc | 2 ++ target/riscv/vector_helper.c| 3 +++ 2 files changed, 5 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/tar

[PATCH qemu v18 16/16] target/riscv: rvv: Add option 'rvv_ta_all_1s' to enable optional tail agnostic behavior

From: eopXD According to v-spec, tail agnostic behavior can be either kept as undisturbed or set elements' bits to all 1s. To distinguish the difference of tail policies, QEMU should be able to simulate the tail agnostic behavior as "set tail elements' bits to all 1s".

[PATCH qemu v4 08/10] target/riscv: rvv: Add mask agnostic for vector mask instructions

From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/insn_trans/trans_rvv.c.inc | 3 +++ target/riscv/vector_helper.c| 11 +++ 2 files changed, 14 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.

[PATCH qemu v18 14/16] target/riscv: rvv: Add tail agnostic for vector mask instructions

From: eopXD The tail elements in the destination mask register are updated under a tail-agnostic policy. Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 6 + target/riscv/vector_helper.c

[PATCH qemu v4 06/10] target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic instructions

From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/vector_helper.c | 26 -- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c inde

[PATCH qemu v18 15/16] target/riscv: rvv: Add tail agnostic for vector permutation instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 7 +++-- target/riscv/vector_helper.c| 40 + 2 files changed, 45 insertions(+), 2 deletions

[PATCH qemu v18 09/16] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions

From: eopXD Compares write mask registers, and so always operate under a tail- agnostic policy. Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis --- target/riscv/vector_helper.c | 18 ++ 1 file changed, 18 insertions

[PATCH qemu v4 05/10] target/riscv: rvv: Add mask agnostic for vector integer comparison instructions

From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/insn_trans/trans_rvv.c.inc | 1 + target/riscv/vector_helper.c| 10 ++ 2 files changed, 11 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.i

[PATCH qemu v4 04/10] target/riscv: rvv: Add mask agnostic for vector integer shift instructions

From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/insn_trans/trans_rvv.c.inc | 1 + target/riscv/vector_helper.c| 7 +++ 2 files changed, 8 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/

[PATCH qemu v4 02/10] target/riscv: rvv: Add mask agnostic for vector load / store instructions

From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 5 target/riscv/vector_helper.c| 35 + 2 files changed, 29 insertions(+), 11 deletions(-) diff --git a/target/riscv/insn_trans/tr

[PATCH qemu v18 11/16] target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis --- target/riscv/vector_helper.c | 220 ++- 1 file changed, 114 insertions(+), 106 deletions(-) diff --git a/target/riscv/vector_helper.c b/target

[PATCH qemu v18 13/16] target/riscv: rvv: Add tail agnostic for vector reduction instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis --- target/riscv/vector_helper.c | 20 1 file changed, 20 insertions(+) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index

[PATCH qemu v18 07/16] target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions

From: eopXD `vmadc` and `vmsbc` produces a mask value, they always operate with a tail agnostic policy. Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 13 +- target/riscv/internals.h

[PATCH qemu v4 01/10] target/riscv: rvv: Add mask agnostic for vv instructions

From: Yueh-Ting (eop) Chen According to v-spec, mask agnostic behavior can be either kept as undisturbed or set elements' bits to all 1s. To distinguish the difference of mask policies, QEMU should be able to simulate the mask agnostic behavior as "set mask elements' bits to all 1s". There are m

[PATCH qemu v18 12/16] target/riscv: rvv: Add tail agnostic for vector floating-point instructions

From: eopXD Compares write mask registers, and so always operate under a tail- agnostic policy. Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 17 + target/riscv/vector_helper.c

[PATCH qemu v18 06/16] target/riscv: rvv: Add tail agnostic for vector load / store instructions

From: eopXD Destination register of unit-stride mask load and store instructions are always written with a tail-agnostic policy. A vector segment load / store instruction may contain fractional lmul with nf * lmul > 1. The rest of the elements in the last register should be treated as t

[PATCH qemu v18 05/16] target/riscv: rvv: Add tail agnostic for vv instructions

From: eopXD According to v-spec, tail agnostic behavior can be either kept as undisturbed or set elements' bits to all 1s. To distinguish the difference of tail policies, QEMU should be able to simulate the tail agnostic behavior as "set tail elements' bits to all 1s".

[PATCH qemu v18 01/16] target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed

From: eopXD No functional change intended in this commit. Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/vector_helper.c | 1132 +- 1 file changed, 565 insertions(+), 567 deletions

[PATCH qemu v18 10/16] target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 12 target/riscv/vector_helper.c| 20 2 files changed, 28 insertions(+), 4 deletions

[PATCH qemu v18 00/16] Add tail agnostic behavior for rvv instructions

load/store functions. v18 updates: - Don't use `is_load` parameter in vector helper. Don't let vta pass through in `trans_rvv.inc` eopXD (16): target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed target/riscv: rvv: Prune redundant access_type parameter passed target

[PATCH qemu v18 03/16] target/riscv: rvv: Rename ambiguous esz

From: eopXD No functional change intended in this commit. Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/vector_helper.c | 76 ++-- 1 file changed, 38 insertions(+), 38 deletions

[PATCH qemu v18 04/16] target/riscv: rvv: Early exit when vstart >= vl

From: eopXD According to v-spec (section 5.4): When vstart ≥ vl, there are no body elements, and no elements are updated in any destination vector register group, including that no tail elements are updated with agnostic values. vmsbf.m, vmsif.m, vmsof.m, viota.m, vcompress instructions

[PATCH qemu v18 08/16] target/riscv: rvv: Add tail agnostic for vector integer shift instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 3 ++- target/riscv/vector_helper.c| 11 +++ 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a

[PATCH qemu v18 02/16] target/riscv: rvv: Prune redundant access_type parameter passed

From: eopXD No functional change intended in this commit. Signed-off-by: eop Chen --- target/riscv/vector_helper.c | 35 --- 1 file changed, 16 insertions(+), 19 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index

[PATCH qemu v3 08/10] target/riscv: rvv: Add mask agnostic for vector mask instructions

From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/insn_trans/trans_rvv.c.inc | 3 +++ target/riscv/vector_helper.c| 11 +++ 2 files changed, 14 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.

[PATCH qemu v3 05/10] target/riscv: rvv: Add mask agnostic for vector integer comparison instructions

From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/insn_trans/trans_rvv.c.inc | 1 + target/riscv/vector_helper.c| 10 ++ 2 files changed, 11 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.i

[PATCH qemu v3 04/10] target/riscv: rvv: Add mask agnostic for vector integer shift instructions

From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/insn_trans/trans_rvv.c.inc | 1 + target/riscv/vector_helper.c| 7 +++ 2 files changed, 8 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/

[PATCH qemu v3 07/10] target/riscv: rvv: Add mask agnostic for vector floating-point instructions

From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/insn_trans/trans_rvv.c.inc | 12 target/riscv/vector_helper.c| 26 + 2 files changed, 38 insertions(+) diff --git a/target/risc

[PATCH qemu v3 09/10] target/riscv: rvv: Add mask agnostic for vector permutation instructions

From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/insn_trans/trans_rvv.c.inc | 1 + target/riscv/vector_helper.c| 26 +++-- 2 files changed, 25 insertions(+), 2 deletions(-) diff --git a/target

[PATCH qemu v3 02/10] target/riscv: rvv: Add mask agnostic for vector load / store instructions

From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 9 +++ target/riscv/vector_helper.c| 35 + 2 files changed, 33 insertions(+), 11 deletions(-) diff --git a/target/riscv/insn_trans

[PATCH qemu v3 10/10] target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable optional mask agnostic behavior

From: eopXD According to v-spec, mask agnostic behavior can be either kept as undisturbed or set elements' bits to all 1s. To distinguish the difference of mask policies, QEMU should be able to simulate the mask agnostic behavior as "set mask elements' bits to all 1s".

[PATCH qemu v3 00/10] Add mask agnostic behavior for rvv instructions

oint instructions target/riscv: rvv: Add mask agnostic for vector mask instructions target/riscv: rvv: Add mask agnostic for vector permutation instructions eopXD (1): target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable optional mask agnostic behavior target/ri

[PATCH qemu v3 06/10] target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic instructions

From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/vector_helper.c | 26 -- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c inde

[PATCH qemu v3 03/10] target/riscv: rvv: Add mask agnostic for vx instructions

From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/insn_trans/trans_rvv.c.inc | 2 ++ target/riscv/vector_helper.c| 3 +++ 2 files changed, 5 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/tar

[PATCH qemu v3 01/10] target/riscv: rvv: Add mask agnostic for vv instructions

From: Yueh-Ting (eop) Chen According to v-spec, mask agnostic behavior can be either kept as undisturbed or set elements' bits to all 1s. To distinguish the difference of mask policies, QEMU should be able to simulate the mask agnostic behavior as "set mask elements' bits to all 1s". There are m

[PATCH qemu v17 11/16] target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis --- target/riscv/vector_helper.c | 220 ++- 1 file changed, 114 insertions(+), 106 deletions(-) diff --git a/target/riscv/vector_helper.c b/target

[PATCH qemu v17 12/16] target/riscv: rvv: Add tail agnostic for vector floating-point instructions

From: eopXD Compares write mask registers, and so always operate under a tail- agnostic policy. Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 17 + target/riscv/vector_helper.c

[PATCH qemu v17 10/16] target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 12 target/riscv/vector_helper.c| 20 2 files changed, 28 insertions(+), 4 deletions

[PATCH qemu v17 15/16] target/riscv: rvv: Add tail agnostic for vector permutation instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 7 +++-- target/riscv/vector_helper.c| 40 + 2 files changed, 45 insertions(+), 2 deletions

[PATCH qemu v17 13/16] target/riscv: rvv: Add tail agnostic for vector reduction instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis --- target/riscv/vector_helper.c | 20 1 file changed, 20 insertions(+) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index

[PATCH qemu v17 16/16] target/riscv: rvv: Add option 'rvv_ta_all_1s' to enable optional tail agnostic behavior

From: eopXD According to v-spec, tail agnostic behavior can be either kept as undisturbed or set elements' bits to all 1s. To distinguish the difference of tail policies, QEMU should be able to simulate the tail agnostic behavior as "set tail elements' bits to all 1s".

[PATCH qemu v17 14/16] target/riscv: rvv: Add tail agnostic for vector mask instructions

From: eopXD The tail elements in the destination mask register are updated under a tail-agnostic policy. Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 6 + target/riscv/vector_helper.c

[PATCH qemu v17 09/16] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions

From: eopXD Compares write mask registers, and so always operate under a tail- agnostic policy. Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis --- target/riscv/vector_helper.c | 18 ++ 1 file changed, 18 insertions

[PATCH qemu v17 01/16] target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed

From: eopXD No functional change intended in this commit. Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/vector_helper.c | 1132 +- 1 file changed, 565 insertions(+), 567 deletions

[PATCH qemu v17 07/16] target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions

From: eopXD `vmadc` and `vmsbc` produces a mask value, they always operate with a tail agnostic policy. Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 13 +- target/riscv/internals.h

[PATCH qemu v17 02/16] target/riscv: rvv: Prune redundant access_type parameter passed

From: eopXD No functional change intended in this commit. Signed-off-by: eop Chen --- target/riscv/vector_helper.c | 35 --- 1 file changed, 16 insertions(+), 19 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index

[PATCH qemu v17 05/16] target/riscv: rvv: Add tail agnostic for vv instructions

From: eopXD According to v-spec, tail agnostic behavior can be either kept as undisturbed or set elements' bits to all 1s. To distinguish the difference of tail policies, QEMU should be able to simulate the tail agnostic behavior as "set tail elements' bits to all 1s".

[PATCH qemu v17 06/16] target/riscv: rvv: Add tail agnostic for vector load / store instructions

From: eopXD Destination register of unit-stride mask load and store instructions are always written with a tail-agnostic policy. A vector segment load / store instruction may contain fractional lmul with nf * lmul > 1. The rest of the elements in the last register should be treated as t

[PATCH qemu v17 00/16] Add tail agnostic behavior for rvv instructions

ying to simulate all 1s for agnostic and use vector helpers instead. v17 updates: - Add "Prune access_type parameter" commit to cleanup vector load/ store functions. Then add parameter `is_load` in vector helper functions to enable vta behavior in the commit for adding vta on vecto

[PATCH qemu v17 04/16] target/riscv: rvv: Early exit when vstart >= vl

From: eopXD According to v-spec (section 5.4): When vstart ≥ vl, there are no body elements, and no elements are updated in any destination vector register group, including that no tail elements are updated with agnostic values. vmsbf.m, vmsif.m, vmsof.m, viota.m, vcompress instructions

[PATCH qemu v17 08/16] target/riscv: rvv: Add tail agnostic for vector integer shift instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 3 ++- target/riscv/vector_helper.c| 11 +++ 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a

[PATCH qemu v17 03/16] target/riscv: rvv: Rename ambiguous esz

From: eopXD No functional change intended in this commit. Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/vector_helper.c | 76 ++-- 1 file changed, 38 insertions(+), 38 deletions

[PATCH qemu v16 08/15] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions

From: eopXD Compares write mask registers, and so always operate under a tail- agnostic policy. Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis --- target/riscv/vector_helper.c | 18 ++ 1 file changed, 18 insertions

[PATCH qemu v16 14/15] target/riscv: rvv: Add tail agnostic for vector permutation instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 7 +++-- target/riscv/vector_helper.c| 40 + 2 files changed, 45 insertions(+), 2 deletions

[PATCH qemu v16 13/15] target/riscv: rvv: Add tail agnostic for vector mask instructions

From: eopXD The tail elements in the destination mask register are updated under a tail-agnostic policy. Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 6 + target/riscv/vector_helper.c

[PATCH qemu v16 11/15] target/riscv: rvv: Add tail agnostic for vector floating-point instructions

From: eopXD Compares write mask registers, and so always operate under a tail- agnostic policy. Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 17 + target/riscv/vector_helper.c

[PATCH qemu v16 12/15] target/riscv: rvv: Add tail agnostic for vector reduction instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis --- target/riscv/vector_helper.c | 20 1 file changed, 20 insertions(+) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index

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