20.06.2016 17:39, Paolo Bonzini wrote:
An asserted pirq can be disabled and the corresponding GSIs
should then go down to 0. However, because of the conditional in
ich9_lpc_update_by_pirq, the legacy 8259 pin could remain stuck to 1.
Signed-off-by: Paolo Bonzini
---
hw/isa/lpc_ich9.c | 3 ---
20.06.2016 17:39, Paolo Bonzini wrote:
ich9->pic and ich9->ioapic differ for the first 16 GSIs (because
ich9->pic is wired to 8259+IOAPIC but ich9->ioapic is wired to
IOAPIC only). However, ich9->ioapic is never used for the first
16 GSIs, so the two vectors can be merged.
Signed-off-by: Paolo
20.06.2016 17:39, Paolo Bonzini wrote:
Make ich9_lpc_update_pic take care only of GSIs 0-15, and
ich9_lpc_update_apic take care only of GSIs 16-23. Assert
that they are called with the correct GSI indices.
Signed-off-by: Paolo Bonzini
---
hw/isa/lpc_ich9.c | 39 --
20.06.2016 17:40, Paolo Bonzini wrote:
I've sent a patch series for you to rebase patch 10 and 11 on. Let me
know what you think!
I see no problems with the patch series. In second version, I'll create
named GPIO ("gsi") for the new IRQ vector gsi (patch 10). The vector
will be used to set up
07.09.2015 15:50, Paolo Bonzini пишет:
Hi Vasily,
I agree that this patch is an improvement compared to the earlier
versions, but it's still a bit of an abstraction violation and I'm not
sure if it works with KVM.
It does not work with KVM. BIOS freezes on 0xCAA26 on
mov %ax,%es
instruction (a
Ping
Vasily
22.07.2015 19:37, Kevin O'Connor пишет:
Hi,
Hi,
Is the motivation of this patch to improve the correctness of the
hardware emulation or is there some feature that the current QEMU
implementation prevents?
The motivation is to improve correctness. The current QEMU PAM
implementation prevents ex
21.07.2015 10:46, Paolo Bonzini пишет:
Out of curiosity, would it be necessary to flush the TLB when the PAM
registers change?
In QEMU, the TLB also has the function of a cache in some sense
(because, by pointing to a ram_addr_t, it prevents reads, writes or
fetches from going through the slow
16.07.2015 20:52, Paolo Bonzini пишет:
On 16/07/2015 16:41, Ефимов Василий wrote:
The main problem is rendering memory tree to FlatView.
I don't believe it's necessary to render a memory tree to the FlatView.
You can use existing AddressSpaces.
+/* Read from RAM and wr
16.07.2015 14:10, Paolo Bonzini wrote:
>
>
> On 16/07/2015 12:51, Ефимов Василий wrote:
>> The rest of code looks up destination or source region or child region
>> offset in memory sub-tree which root is PCI or RAM region provided on
>> PAM creation. We cannon use com
16.07.2015 12:05, Paolo Bonzini пишет:
On 16/07/2015 10:35, Efimov Vasily wrote:
This patch improves PAM emulation.
PAM defines 4 memory access redirection modes. In mode 1 reads are directed to
RAM and writes are directed to PCI. In mode 2 it is contrary. In mode 0 all
access is directed to
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