On Oct 16 17:04, Richard Henderson wrote:
> On 10/10/18 1:37 PM, Aaron Lindsay wrote:
> > + * Return the underlying cycle count for the PMU cycle counters. If we're
> > in
> > + * usermode, simply return 0.
> > + */
> > +static uint64_t cycles_get_count
On Oct 17 12:34, Richard Henderson wrote:
> On 10/17/18 12:20 PM, Aaron Lindsay wrote:
> > On Oct 16 17:09, Richard Henderson wrote:
> >> On 10/10/18 1:37 PM, Aaron Lindsay wrote:
> >>> This both advertises that we support four counters and enables them
> >>
On Oct 17 14:12, Richard Henderson wrote:
> On 10/17/18 12:47 PM, Aaron Lindsay wrote:
> > On Oct 16 17:04, Richard Henderson wrote:
> >> On 10/10/18 1:37 PM, Aaron Lindsay wrote:
> >>> + * Return the underlying cycle count for the PMU cycle counters. If
> >&g
On Oct 17 14:14, Richard Henderson wrote:
> On 10/17/18 1:25 PM, Aaron Lindsay wrote:
> > I suppose pmcrn (the local variable) should've been set to 0 before this
> > patch and updated here to be 4.
>
> That's plausible.
>
> > Anyway, by splitting
On Oct 18 11:27, Richard Henderson wrote:
> @@ -2761,12 +2763,12 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
>.fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0,
> },
> { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
>.opc0 = 3, .opc1 = 0, .crn = 2
On Oct 18 11:27, Richard Henderson wrote:
> The EL3 version of this register does not include an ASID,
> and so the tlb_flush performed by vmsa_ttbr_write is not needed.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Aaron Lindsay
f flushes by 30%, or nearly 600k instances.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Aaron Lindsay
Ping, just in case this got buried over the holidays...
-Aaron
On Dec 11 10:20, Aaron Lindsay wrote:
> The ARM PMU implementation currently contains a basic cycle counter, but
> it is often useful to gather counts of other events, filter them based
> on execution mode, and/or be no
On Jan 18 07:26, Richard Henderson wrote:
> On 12/12/18 2:20 AM, Aaron Lindsay wrote:
> > Setup a QEMUTimer to get a callback when we expect counters to next
> > overflow and trigger an interrupt at that time.
> >
> > Signed-off-by: Aaron Lindsay
>
On Feb 09 15:11, Alistair Francis wrote:
> On Tue, Feb 9, 2016 at 9:19 AM, Peter Maydell
> wrote:
> > On 6 February 2016 at 00:55, Alistair Francis
> > wrote:
> >> Signed-off-by: Aaron Lindsay
> >> Signed-off-by: Alistair Francis
> >> Tested-by:
Alistair,
On Feb 03 16:34, Alistair Francis wrote:
> This patch set is based on the patch sent by Christopher Covington and
> written by Aaron Lindsay which was sent as an RFC (Implement remaining
> PMU functionality).
These patches look like a good start to improving the PMU support,
t
On Feb 04 10:52, Alistair Francis wrote:
> On Thu, Feb 4, 2016 at 5:39 AM, Aaron Lindsay wrote:
> > Please add my
> > Signed-off-by: Aaron Lindsay
> > to all three.
>
> Ok, I wasn't sure what you wanted to do there. I'll add them all and
> they will be th
A53 advertises ARM_FEATURE_PMU, but wasn't initializing pmceid[01]
Signed-off-by: Aaron Lindsay
---
target/arm/cpu.c | 2 +-
target/arm/cpu64.c | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 04b062c..921b028 100644
--- a/t
ut it doesn't
seem like the right way to handle this.
I would like to eventually add sending interrupts on counter overflow.
Suggestions for the best direction to handle this are most welcome.
Thanks for any feedback,
Aaron
Aaron Lindsay (13):
target/arm: A53: Initialize PMCEID[0]
Signed-off-by: Aaron Lindsay
---
target/arm/helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 8cb7a94..391 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -964,7 +964,7 @@ static inline bool
pmccntr_read and pmccntr_write contained duplicate code that was already
being handled by pmccntr_sync. This also moves the calls to get the
clock inside the 'if' statement so they are not executed if not needed.
Signed-off-by: Aaron Lindsay
---
target/arm/hel
This is in preparation for enabling counters other than PMCCNTR
Signed-off-by: Aaron Lindsay
---
target/arm/helper.c | 24 +++-
1 file changed, 15 insertions(+), 9 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 390256b..e8189b8 100644
--- a/target
Also modify it to be stored as a uint64_t
Signed-off-by: Aaron Lindsay
---
target/arm/cpu.h| 2 +-
target/arm/helper.c | 27 ---
2 files changed, 25 insertions(+), 4 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index ae2a294..f3524f6 100644
--- a
Also fix the existing bitmask for writes.
Signed-off-by: Aaron Lindsay
---
target/arm/helper.c | 23 ++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index e8189b8..530fc7c 100644
--- a/target/arm/helper.c
+++ b
Signed-off-by: Aaron Lindsay
---
target/arm/helper.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 9c01269..5d07f72 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -975,17 +975,22 @@ static
mechanism for handling this?
Signed-off-by: Aaron Lindsay
---
target/arm/cpu.c | 4 +++
target/arm/cpu.h | 15 +++
target/arm/helper.c| 73 +++---
target/arm/kvm64.c | 2 ++
target/arm/machine.c | 2 ++
target/arm/op_helper.c
Signed-off-by: Aaron Lindsay
---
target/arm/helper.c | 40 ++--
1 file changed, 38 insertions(+), 2 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index a15b932..2c51f92 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -907,6
This commit doesn't add any supported events, but provides the framework
for adding them. We store the pm_event structs in a simple array, and
provide the mapping from the event numbers to array indexes in
the supported_event_map array.
Signed-off-by: Aaron Lindsay
---
target/arm/cpu.c
Add arrays to hold the registers, the definitions themselves, access
functions, and add logic to reset counters when PMCR.P is set.
Signed-off-by: Aaron Lindsay
---
target/arm/cpu.h| 7 +-
target/arm/helper.c | 187
2 files changed, 179
The instruction event is only enabled when icount is used, cycles are
always supported.
Note: Setting can_do_io=1 should not be done here. It is ugly and wrong,
but I am not sure of the proper way to handle this (See 'target/arm:
Filter cycle counter based on PMCCFILTR_EL0')
Signed-off
This both advertises that we support four counters and adds them to the
implementation because the PMU_NUM_COUNTERS macro reads this value from
the PMCR.
Signed-off-by: Aaron Lindsay
---
target/arm/helper.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/arm
On Jun 10 12:16, Dr. David Alan Gilbert (git) wrote:
> From: "Dr. David Alan Gilbert"
>
> Use the avx2 primitives during the test, thus making sure that the
> compiler and assembler could actually use avx2.
>
> This also detects the failure case on gcc 4.8.x with -save-temps
> and avoids the nee
On Jul 14 14:33, Dr. David Alan Gilbert wrote:
> * Aaron Lindsay (alind...@codeaurora.org) wrote:
> > I'm configuring with:
> > # ./configure \
> > --static \
> > --disable-gtk \
> > --target-list=aarch64-softmmu
>
> Does it work if you co
On Jul 14 14:23, Peter Maydell wrote:
> On 14 July 2016 at 14:15, Paolo Bonzini wrote:
> > On 14/07/2016 15:13, Aaron Lindsay wrote:
> >> I'm configuring with:
> >> # ./configure \
> >> --static \
> >> --disable-gtk \
> >>
On Jul 14 15:35, Peter Maydell wrote:
> On 14 July 2016 at 15:27, Aaron Lindsay wrote:
> > On Jul 14 14:23, Peter Maydell wrote:
> >> On 14 July 2016 at 14:15, Paolo Bonzini wrote:
> >> > On 14/07/2016 15:13, Aaron Lindsay wrote:
> >> >>
On Jul 14 16:05, Dr. David Alan Gilbert wrote:
> * Aaron Lindsay (alind...@codeaurora.org) wrote:
> > On Jul 14 14:33, Dr. David Alan Gilbert wrote:
> > > * Aaron Lindsay (alind...@codeaurora.org) wrote:
> > > > I'm configuring with:
> >
{
(gdb) bt
#0 buffer_find_nonzero_offset_ifunc () at ./util/cutils.c:333
#1 0x00939c58 in __libc_start_main ()
#2 0x00419337 in _start ()
Signed-off-by: Aaron Lindsay
---
configure | 17 ++---
1 file changed, 10 insertions(+), 7 deletions
Wei, Peter,
On Feb 10 18:07, Peter Maydell wrote:
> From: Wei Huang
>
> This patch adds access support for PMINTENSET_EL1.
>
> Signed-off-by: Wei Huang
> Reviewed-by: Peter Maydell
> Message-id: 1486504171-26807-4-git-send-email-...@redhat.com
> Signed-off-by: Peter Maydell
> ---
> target/a
I am interested in implementing an instruction counter to augment the
ongoing (mostly cycle-counter) PMU work on AArch64. The icount
infrastructure seems like the logical source for the instruction counts,
but I have a couple of implementation-related questions:
1. It looks like cpu_get_icount_raw
: Aaron Lindsay
---
target/arm/helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index dc9c29f998..c69a2baf1d 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -2269,13 +2269,13 @@ static const ARMCPRegInfo
On Feb 25 17:08, Peter Maydell wrote:
> On Fri, 1 Feb 2019 at 16:07, Peter Maydell wrote:
> >
> > From: Aaron Lindsay OS
> >
> > Whenever we notice that a counter overflow has occurred, send an
> > interrupt. This is made more reliable with the addition of
This check was backwards when introduced in commit
033614c47de78409ad3fb39bb7bd1483b71c6789:
target/arm: Filter cycle counter based on PMCCFILTR_EL0
Signed-off-by: Aaron Lindsay
---
target/arm/helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/helper.c
On Aug 24 17:33, Peter Maydell wrote:
> On Fri, 18 Jan 2019 at 14:58, Peter Maydell wrote:
> >
> > From: Aaron Lindsay
> >
> > Rename arm_ccnt_enabled to pmu_counter_enabled, and add logic to only
> > return 'true' if the specified counter is ena
On Oct 17 14:15, Alex Bennée wrote:
> This provides a limited amount of info to plugins about the guest
> system that will allow them to make some additional decisions on
> setup.
>
> Signed-off-by: Alex Bennée
>
> ---
> v6
> - split and move to pre example plugins
> - checkpatch fixes
> ---
On Mar 22 17:23, Andrew Jones wrote:
> cortex-a7 and cortex-a15 have pmus (PMUv2) and they advertise
> them in ID_DFR0. Let's allow them to function. This also enables
> the pmu cpu property to work with these cpu types, i.e. we can
> now do '-cpu cortex-a15,pmu=off' to remove the pmu.
I'm a littl
gt; overflow")
> Signed-off-by: Andrew Jones
Reviewed-by: Aaron Lindsay
> ---
> target/arm/helper.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index c8d3c213b6b7..fc73488f6cc0 100644
> --- a/target/a
On Mar 22 17:23, Andrew Jones wrote:
> These functions are not used outside helper.c
>
> Signed-off-by: Andrew Jones
I'm late to the party, but:
Reviewed-by: Aaron Lindsay
> ---
> target/arm/cpu.h| 11 ---
> target/arm/helper.c | 4 ++--
> 2 files ch
On Feb 04 20:22, Laurent Desnogues wrote:
> Hello,
>
> On Tue, Dec 11, 2018 at 4:25 PM Aaron Lindsay
> wrote:
> >
> > Add arrays to hold the registers, the definitions themselves, access
> > functions, and logic to reset counters when PMCR.P is set. Update
> >
This bug was introduced in:
commit 5ecdd3e47cadae83a62dc92b472f1fe163b56f59
target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER
Signed-off-by: Aaron Lindsay
Reported-by: Laurent Desnogues
---
target/arm/helper.c | 8
1 file changed, 4 insertions(+), 4 deletions
: Aaron Lindsay
---
target/arm/cpu.c| 3 +--
target/arm/cpu.h| 11 +--
target/arm/helper.c | 27 ---
3 files changed, 22 insertions(+), 19 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 7e1f3dd637..d6da3f4fed 100644
--- a/target/arm
On Jan 18 14:13, Peter Maydell wrote:
> On Tue, 11 Dec 2018 at 15:20, Aaron Lindsay
> wrote:
> >
> > The ARM PMU implementation currently contains a basic cycle counter, but
> > it is often useful to gather counts of other events, filter them based
> > on executi
gnu.org/archive/html/qemu-devel/2019-01/msg05996.html
Aaron Lindsay (2):
target/arm: Send interrupts on PMU counter overflow
target/arm: Add a timer to predict PMU counter overflow
target/arm/cpu.c| 12
target/arm/cpu.h| 10
target/arm
Whenever we notice that a counter overflow has occurred, send an
interrupt. This is made more reliable with the addition of a timer in a
follow-on commit.
Signed-off-by: Aaron Lindsay
---
target/arm/helper.c | 61 +
1 file changed, 51 insertions
Make PMU overflow interrupts more accurate by using a timer to predict
when they will overflow rather than waiting for an event to occur which
allows us to otherwise check them.
Signed-off-by: Aaron Lindsay
---
target/arm/cpu.c| 12
target/arm/cpu.h| 10 +++
target/arm
On Jan 23 15:37, Richard Henderson wrote:
> On 1/23/19 1:32 PM, Aaron Lindsay OS wrote:
> > +uint64_t overflow_mask = env->cp15.c9_pmcr & PMCRLC ? \
> > + INT64_MIN : INT32_MIN;
>
> With type promotion,
Most of this patchset implementing the PMU has been merged already, but
the interrupt-on-overflow behavior had some additional review comments.
This most recent version fixes a type promotion issue and adds Richard's
Reviewed-by's.
Aaron Lindsay (2):
target/arm: Send interrupts on P
Make PMU overflow interrupts more accurate by using a timer to predict
when they will overflow rather than waiting for an event to occur which
allows us to otherwise check them.
Signed-off-by: Aaron Lindsay
Reviewed-by: Richard Henderson
---
target/arm/cpu.c| 12
target/arm/cpu.h
Whenever we notice that a counter overflow has occurred, send an
interrupt. This is made more reliable with the addition of a timer in a
follow-on commit.
Signed-off-by: Aaron Lindsay
Reviewed-by: Richard Henderson
---
target/arm/helper.c | 61 +
1
On Feb 14 17:55, Peter Maydell wrote:
> On Mon, 28 Jan 2019 at 18:11, Peter Maydell wrote:
> >
> > From: Aaron Lindsay OS
> >
> > A bug was introduced during a respin of:
> >
> > commit 57a4a11b2b281bb548b419ca81bfafb214e4c77a
> > t
On Feb 19 14:33, Peter Maydell wrote:
> On Tue, 19 Feb 2019 at 14:23, Aaron Lindsay OS
> wrote:
> > I registered for a Coverity account and am awaiting approval for adding
> > me to the QEMU project so I can test this myself (let me know if this
> > isn't t
This was introduced by
commit bf8d09694ccc07487cd73d7562081fdaec3370c8
target/arm: Don't clear supported PMU events when initializing PMCEID1
and identified by Coverity (CID 1398645).
Signed-off-by: Aaron Lindsay
Reported-by: Peter Maydell
---
target/arm/helper.c | 2 +-
1 file ch
On Oct 17 14:16, Alex Bennée wrote:
> Having the plugins grab stdout and spew stuff there is a bit ugly and
> certainly makes the tests look ugly. Provide a hook back into QEMU
> which can be redirected as needed.
>
> Signed-off-by: Alex Bennée
Reviewed-by: Aaron Lindsay
On Oct 18 16:54, Alex Bennée wrote:
>
> Aaron Lindsay OS writes:
>
> > On Oct 17 14:15, Alex Bennée wrote:
> >> +const char *target_name;
> >> +/* is this a full system emulation? */
> >> +bool system_emulation;
> >
> >
On Oct 17 14:16, Alex Bennée wrote:
> It's quite common to have a mini comment inside braces to acknowledge
> we know it's empty. Expand the inline detection to allow closing
> braces before the end of line.
>
> Signed-off-by: Alex Bennée
Reviewed-by: Aaron Lindsay
Treat EM_AARCH64 as a valid value when checking the ELF's machine-type
header.
Signed-off-by: Aaron Lindsay
---
include/hw/elf_ops.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/include/hw/elf_ops.h b/include/hw/elf_ops.h
index 690f9238c8..f12faa90a1 100644
--- a/inclu
On Aug 12 16:02, Peter Maydell wrote:
> On Mon, 12 Aug 2019 at 15:46, Aaron Lindsay OS via Qemu-arm
> wrote:
> >
> > Treat EM_AARCH64 as a valid value when checking the ELF's machine-type
> > header.
> >
> > Signed-off-by: Aaron Lindsay
> > ---
&
On Jul 31 17:06, Alex Bennée wrote:
> Now we do all our checking and use a common EXCP_SEMIHOST for
> semihosting operations we can make helper code a lot simpler.
>
> Signed-off-by: Alex Bennée
>
> ---
> v2
> - fix re-base conflicts
> - hoist EXCP_SEMIHOST check
> - comment cleanups
> ---
On Jul 31 17:06, Alex Bennée wrote:
> We need to keep a local per-cpu copy of the data as other threads may
> be running. We use a automatically growing array and re-use the space
> for subsequent queries.
[...]
> +bool tlb_plugin_lookup(CPUState *cpu, target_ulong addr, int mmu_idx,
> +
On Jul 31 17:07, Alex Bennée wrote:
> + * Attempt to measure the amount of vectorisation that has been done
> + * on some code by counting classes of instruction. This is very much
> + * ARM specific.
I suspect some of my plugins will also be architecture-specific. Does it
make sense to have a plu
One thing I would find useful is the ability to access register values
during an execution-time callback. I think the easiest way to do that
generically would be to expose them via the gdb functionality (like
Pavel's earlier patchset did [1]), though that (currently) limits you to
the general-purpo
On Sep 06 20:52, Alex Bennée wrote:
>
> Markus Armbruster writes:
> > Please advise why TCG plugins don't undermine the GPL. Any proposal to
> > add a plugin interface needs to do that.
>
> I'm not sure what we can say about this apart from "ask your lawyer".
> I'm certainly not proposing we ad
On Sep 06 20:31, Alex Bennée wrote:
> Aaron Lindsay OS writes:
>
> > One thing I would find useful is the ability to access register values
> > during an execution-time callback. I think the easiest way to do that
> > generically would be to expose them via the
On Jun 28 21:52, Alex Bennée wrote:
> Aaron Lindsay OS writes:
> > To make sure I understand - you're implying that one such query will
> > return the PA from the guest's perspective, right?
>
> Yes - although it will be two queries:
>
> struct qemu_plugi
On Jul 01 16:00, Alex Bennée wrote:
> Aaron Lindsay OS writes:
> > - a way for a plugin to reset any instrumentation decisions made in the
> > past (essentially calls `tb_flush(cpu);` under the covers). We found
> > this critical for plugins which undergo state changes du
On Jun 14 18:11, Alex Bennée wrote:
> From: "Emilio G. Cota"
>
> Here the trickiest feature is passing the host address to
> memory callbacks that request it. Perhaps it would be more
> appropriate to pass a "physical" address to plugins, but since
> in QEMU host addr ~= guest physical, I'm going
On Jun 28 18:11, Alex Bennée wrote:
> Aaron Lindsay OS writes:
> > On Jun 14 18:11, Alex Bennée wrote:
> >> From: "Emilio G. Cota"
> >>
> >> Here the trickiest feature is passing the host address to
> >> memory callbacks that request
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