On Oct 17 14:16, Alex Bennée wrote:
> It's quite common to have a mini comment inside braces to acknowledge
> we know it's empty. Expand the inline detection to allow closing
> braces before the end of line.
>
> Signed-off-by: Alex Bennée
Reviewed-by: Aaron Lindsay
On Oct 18 16:54, Alex Bennée wrote:
>
> Aaron Lindsay OS writes:
>
> > On Oct 17 14:15, Alex Bennée wrote:
> >> +const char *target_name;
> >> +/* is this a full system emulation? */
> >> +bool system_emulation;
> >
> >
On Oct 17 14:16, Alex Bennée wrote:
> Having the plugins grab stdout and spew stuff there is a bit ugly and
> certainly makes the tests look ugly. Provide a hook back into QEMU
> which can be redirected as needed.
>
> Signed-off-by: Alex Bennée
Reviewed-by: Aaron Lindsay
On Oct 17 14:15, Alex Bennée wrote:
> This provides a limited amount of info to plugins about the guest
> system that will allow them to make some additional decisions on
> setup.
>
> Signed-off-by: Alex Bennée
>
> ---
> v6
> - split and move to pre example plugins
> - checkpatch fixes
> ---
On Sep 06 20:31, Alex Bennée wrote:
> Aaron Lindsay OS writes:
>
> > One thing I would find useful is the ability to access register values
> > during an execution-time callback. I think the easiest way to do that
> > generically would be to expose them via the
On Sep 06 20:52, Alex Bennée wrote:
>
> Markus Armbruster writes:
> > Please advise why TCG plugins don't undermine the GPL. Any proposal to
> > add a plugin interface needs to do that.
>
> I'm not sure what we can say about this apart from "ask your lawyer".
> I'm certainly not proposing we ad
On Aug 12 16:02, Peter Maydell wrote:
> On Mon, 12 Aug 2019 at 15:46, Aaron Lindsay OS via Qemu-arm
> wrote:
> >
> > Treat EM_AARCH64 as a valid value when checking the ELF's machine-type
> > header.
> >
> > Signed-off-by: Aaron Lindsay
> > ---
&
Treat EM_AARCH64 as a valid value when checking the ELF's machine-type
header.
Signed-off-by: Aaron Lindsay
---
include/hw/elf_ops.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/include/hw/elf_ops.h b/include/hw/elf_ops.h
index 690f9238c8..f12faa90a1 100644
--- a/include/hw/elf_ops.
One thing I would find useful is the ability to access register values
during an execution-time callback. I think the easiest way to do that
generically would be to expose them via the gdb functionality (like
Pavel's earlier patchset did [1]), though that (currently) limits you to
the general-purpo
On Jul 31 17:07, Alex Bennée wrote:
> + * Attempt to measure the amount of vectorisation that has been done
> + * on some code by counting classes of instruction. This is very much
> + * ARM specific.
I suspect some of my plugins will also be architecture-specific. Does it
make sense to have a plu
On Jul 31 17:06, Alex Bennée wrote:
> We need to keep a local per-cpu copy of the data as other threads may
> be running. We use a automatically growing array and re-use the space
> for subsequent queries.
[...]
> +bool tlb_plugin_lookup(CPUState *cpu, target_ulong addr, int mmu_idx,
> +
On Jul 31 17:06, Alex Bennée wrote:
> Now we do all our checking and use a common EXCP_SEMIHOST for
> semihosting operations we can make helper code a lot simpler.
>
> Signed-off-by: Alex Bennée
>
> ---
> v2
> - fix re-base conflicts
> - hoist EXCP_SEMIHOST check
> - comment cleanups
> ---
On Jul 01 16:00, Alex Bennée wrote:
> Aaron Lindsay OS writes:
> > - a way for a plugin to reset any instrumentation decisions made in the
> > past (essentially calls `tb_flush(cpu);` under the covers). We found
> > this critical for plugins which undergo state changes du
On Jun 28 21:52, Alex Bennée wrote:
> Aaron Lindsay OS writes:
> > To make sure I understand - you're implying that one such query will
> > return the PA from the guest's perspective, right?
>
> Yes - although it will be two queries:
>
> struct qemu_plugi
On Jun 28 18:11, Alex Bennée wrote:
> Aaron Lindsay OS writes:
> > On Jun 14 18:11, Alex Bennée wrote:
> >> From: "Emilio G. Cota"
> >>
> >> Here the trickiest feature is passing the host address to
> >> memory callbacks that request
On Jun 14 18:11, Alex Bennée wrote:
> From: "Emilio G. Cota"
>
> Here the trickiest feature is passing the host address to
> memory callbacks that request it. Perhaps it would be more
> appropriate to pass a "physical" address to plugins, but since
> in QEMU host addr ~= guest physical, I'm going
On Mar 22 17:23, Andrew Jones wrote:
> These functions are not used outside helper.c
>
> Signed-off-by: Andrew Jones
I'm late to the party, but:
Reviewed-by: Aaron Lindsay
> ---
> target/arm/cpu.h| 11 ---
> target/arm/helper.c | 4 ++--
> 2 files changed, 2 insertions(+), 13 de
On Mar 22 17:23, Andrew Jones wrote:
> Fix a QEMU NULL derefence that occurs when the guest attempts to
> enable PMU counters with a non-v8 cpu model or a v8 cpu model
> which has not configured a PMU.
>
> Fixes: 4e7beb0cc0f3 ("target/arm: Add a timer to predict PMU counter
> overflow")
> Signed-
On Mar 22 17:23, Andrew Jones wrote:
> cortex-a7 and cortex-a15 have pmus (PMUv2) and they advertise
> them in ID_DFR0. Let's allow them to function. This also enables
> the pmu cpu property to work with these cpu types, i.e. we can
> now do '-cpu cortex-a15,pmu=off' to remove the pmu.
I'm a littl
This was introduced by
commit bf8d09694ccc07487cd73d7562081fdaec3370c8
target/arm: Don't clear supported PMU events when initializing PMCEID1
and identified by Coverity (CID 1398645).
Signed-off-by: Aaron Lindsay
Reported-by: Peter Maydell
---
target/arm/helper.c | 2 +-
1 file changed,
On Feb 19 14:33, Peter Maydell wrote:
> On Tue, 19 Feb 2019 at 14:23, Aaron Lindsay OS
> wrote:
> > I registered for a Coverity account and am awaiting approval for adding
> > me to the QEMU project so I can test this myself (let me know if this
> > isn't t
On Feb 14 17:55, Peter Maydell wrote:
> On Mon, 28 Jan 2019 at 18:11, Peter Maydell wrote:
> >
> > From: Aaron Lindsay OS
> >
> > A bug was introduced during a respin of:
> >
> > commit 57a4a11b2b281bb548b419ca81bfafb214e4c77a
> > t
This bug was introduced in:
commit 5ecdd3e47cadae83a62dc92b472f1fe163b56f59
target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER
Signed-off-by: Aaron Lindsay
Reported-by: Laurent Desnogues
---
target/arm/helper.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
On Feb 04 20:22, Laurent Desnogues wrote:
> Hello,
>
> On Tue, Dec 11, 2018 at 4:25 PM Aaron Lindsay
> wrote:
> >
> > Add arrays to hold the registers, the definitions themselves, access
> > functions, and logic to reset counters when PMCR.P is set. Update
> > filtering code to support counters o
Whenever we notice that a counter overflow has occurred, send an
interrupt. This is made more reliable with the addition of a timer in a
follow-on commit.
Signed-off-by: Aaron Lindsay
Reviewed-by: Richard Henderson
---
target/arm/helper.c | 61 +
1 fi
Make PMU overflow interrupts more accurate by using a timer to predict
when they will overflow rather than waiting for an event to occur which
allows us to otherwise check them.
Signed-off-by: Aaron Lindsay
Reviewed-by: Richard Henderson
---
target/arm/cpu.c| 12
target/arm/cpu.h
Most of this patchset implementing the PMU has been merged already, but
the interrupt-on-overflow behavior had some additional review comments.
This most recent version fixes a type promotion issue and adds Richard's
Reviewed-by's.
Aaron Lindsay (2):
target/arm: Send interrupts on PMU counter ov
On Jan 23 15:37, Richard Henderson wrote:
> On 1/23/19 1:32 PM, Aaron Lindsay OS wrote:
> > +uint64_t overflow_mask = env->cp15.c9_pmcr & PMCRLC ? \
> > + INT64_MIN : INT32_MIN;
>
> With type promotion,
Make PMU overflow interrupts more accurate by using a timer to predict
when they will overflow rather than waiting for an event to occur which
allows us to otherwise check them.
Signed-off-by: Aaron Lindsay
---
target/arm/cpu.c| 12
target/arm/cpu.h| 10 +++
target/arm/helpe
Most of this patchset to implement the PMU has been merged already, but
the interrupt-on-overflow behavior had some additional review comments.
In addition to improving the overflow detection and bit-clearing logic,
I split the previous patch [1] into two to (hopefully) make it more
digestable.
Th
Whenever we notice that a counter overflow has occurred, send an
interrupt. This is made more reliable with the addition of a timer in a
follow-on commit.
Signed-off-by: Aaron Lindsay
---
target/arm/helper.c | 61 +
1 file changed, 51 insertions(+), 10
On Jan 18 14:13, Peter Maydell wrote:
> On Tue, 11 Dec 2018 at 15:20, Aaron Lindsay
> wrote:
> >
> > The ARM PMU implementation currently contains a basic cycle counter, but
> > it is often useful to gather counts of other events, filter them based
> > on execution mode, and/or be notified on coun
A bug was introduced during a respin of:
commit 57a4a11b2b281bb548b419ca81bfafb214e4c77a
target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0
This patch introduced two calls to get_pmceid() during CPU
initialization - one each for PMCEID0 and PMCEID1. In additio
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