Re: [PATCH v9] target/riscv/kvm/kvm-cpu.c: kvm_riscv_handle_sbi() fail with vendor-specific SBI

2024-09-18 Thread Aleksei Filippov
we're no long aborting the SBI call, but returning non-supported instead. I agreed, I'll split commits, but do you want me to resend patch as 2 patch series or 2 separate patches? Thanks, drew -- Sincerely, Aleksei Filippov

Re: [PATCH v2] target/riscv: Add support for machine specific pmu's events

2024-09-11 Thread Aleksei Filippov
On 08.07.2024 16:42, Philippe Mathieu-Daudé wrote: Hi Aleksei, On 8/7/24 11:46, Aleksei Filippov wrote: On 25.06.2024 21:18, Richard Henderson wrote: On 6/25/24 07:46, Alexei Filippov wrote: Was added call backs for machine specific pmu events. Simplify monitor functions by adding new

Re: [PATCH v2] target/riscv: Add support for machine specific pmu's events

2024-07-08 Thread Aleksei Filippov
t device. What do you think about it? (I'll send it in the few days). -- Sincerely, Aleksei Filippov

Re: [PATCH v6] target/riscv/kvm/kvm-cpu.c: kvm_riscv_handle_sbi() fail with vendor-specific SBI

2024-05-03 Thread Aleksei Filippov
RE is -1 anyway. Defines was added at first place just to came along with Linux kernel SBI related defines. -- Sincerely, Aleksei Filippov } else { -run->riscv_sbi.ret[0] = -1; +ret = -1; } -ret = 0; break; default:

Re: [PATCH v5] target/riscv/kvm/kvm-cpu.c: kvm_riscv_handle_sbi() fail with vendor-specific sbi.

2024-04-22 Thread Aleksei Filippov
LABLE -6 #define SBI_ERR_ALREADY_STARTED -7 #define SBI_ERR_ALREADY_STOPPED -8 +#define SBI_ERR_NO_SHMEM-9 #endif Oh, my bad, wrong patch. Will resend properly. -- Sincerely, Aleksei Filippov

Re: [PATCH for-9.0] target/riscv: prioritize pmp errors in raise_mmu_exception()

2024-04-12 Thread Aleksei Filippov
e know what do you think. If you agree I can re-send both patches together. Thanks, Daniel Oh, I actually missed that, thx, you are right. I could prepare patch to fix this, do you want it in this thread or in previous with only my patch in? -- Sincerely, Aleksei Filippov

Re: [PATCH for-9.0] target/riscv: prioritize pmp errors in raise_mmu_exception()

2024-04-12 Thread Aleksei Filippov
est_phys_fault_addr in context of riscv_cpu_tlb_fill()) as this was a guest-page-fault, but it didn't and mtval2 should be zero, according to RISCV privileged spec sect. 9.4.4: When a guest page-fault is taken into M-mode, mtval2 is written with either zero or guest physical address that faulted, shifted by 2 bits. *For other traps, mtval2 is set to zero...* -- Sincerely, Aleksei Filippov