On Fri, Sep 13, 2024 at 10:04:29AM +0200, Markus Armbruster wrote:
> Alexandre Ratchov writes:
>
> > On Tue, Sep 10, 2024 at 03:28:57PM +0100, Daniel P. Berrangé wrote:
> >> >
> >> > This is the single use of the ISC license in the more than 10k
> >
On Tue, Sep 10, 2024 at 03:28:57PM +0100, Daniel P. Berrangé wrote:
> >
> > This is the single use of the ISC license in the more than 10k
> > files in the repository. Just checking IIUC this document:
> > https://www.gnu.org/licenses/quick-guide-gplv3.en.html
> >
> > ISC -> LGPLv2.1 -> GPLv2 ->
allows to drastically reduce the number of sfence.vma emitted
by S-mode.
Signed-off-by: Alexandre Ghiti
---
Changes in v3:
- Rebase on top of master
- Change 1.12 to 1.13 spec version (drew)
Changes in v2:
- Rebase on top of master
- Enable Svvptc by default
target/riscv/cpu.c | 2 ++
target/riscv
Reviewed-by: Alexandre Iooss
sh I reported here:
https://gitlab.com/qemu-project/qemu/-/issues/2489
Reviewed-by: Alexandre Iooss
Thanks,
--
Alexandre
allows to drastically reduce the number of sfence.vma emitted
by S-mode.
Signed-off-by: Alexandre Ghiti
---
Changes in v2:
- Rebase on top of master
- Enable Svvptc by default
target/riscv/cpu.c | 2 ++
target/riscv/cpu_cfg.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/target/riscv/cpu.
Some people are wondering why they get an empty string as disassembly.
Most of the time, they configured QEMU without Capstone support.
Let's document this behaviour to help users.
Signed-off-by: Alexandre Iooss
---
docs/devel/tcg-plugins.rst | 4 +++-
1 file changed, 3 insertions(
Hi Zhiwei,
On Tue, May 28, 2024 at 8:57 AM LIU Zhiwei wrote:
>
> Hi Alexandre,
>
> I have sent the patch set about Zabha before last week.
Sorry I did not check!
>
> https://lore.kernel.org/all/fed99165-58da-458c-b68f-a9717fc15...@linux.alibaba.com/T/
>
> Welcome to rev
From: Gianluca Guida
Add Zabha implementation.
Signed-off-by: Gianluca Guida
Signed-off-by: Alexandre Ghiti
---
target/riscv/cpu.c | 2 +
target/riscv/cpu_cfg.h | 1 +
target/riscv/insn32.decode | 22 +++
target/riscv
Hi Andrew,
Sorry for the very late reply, I was (and still am) off!
On Tue, Feb 13, 2024 at 4:33 PM Andrew Jones wrote:
>
> On Tue, Feb 13, 2024 at 03:53:08PM +0100, Alexandre Ghiti wrote:
> > The Svvptc extension describes a uarch that does not cache invalid TLB
> > entrie
The Svvptc extension describes a uarch that does not cache invalid TLB
entries: that's the case for qemu so there is nothing particular to
implement other than the introduction of this extension, which is done
here.
Signed-off-by: Alexandre Ghiti
---
That's an RFC since the extensi
On Tue, Feb 6, 2024 at 9:39 PM Daniel Henrique Barboza
wrote:
>
>
>
> On 2/6/24 12:40, Alexandre Ghiti wrote:
> > Currently, the initrd is placed at 128MB, which overlaps with the kernel
> > when it is large (for example syzbot kernels are). From the kernel side,
> &g
ideal solution would have been to place the initrd based on the
kernel size but we actually can't since the bss size is not known when
the image is loaded by load_image_targphys_as() and the initrd would
then overlap with this section.
Signed-off-by: Alexandre Ghiti
---
Changes in v2:
- Fix typ
Hi Daniel,
On Mon, Feb 5, 2024 at 2:36 PM Alexandre Ghiti wrote:
>
> Hi Daniel,
>
> On Mon, Feb 5, 2024 at 1:17 PM Daniel Henrique Barboza
> wrote:
> >
> >
> >
> > On 2/5/24 04:00, Alexandre Ghiti wrote:
> > > Currently, the initrd is placed at
Hi Daniel,
On Mon, Feb 5, 2024 at 1:17 PM Daniel Henrique Barboza
wrote:
>
>
>
> On 2/5/24 04:00, Alexandre Ghiti wrote:
> > Currently, the initrd is placed at 128MB, which overlaps with the kernel
> > when it is large (for example syzbot kernels are). From the kern
-off-by: Alexandre Ghiti
---
hw/riscv/boot.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 0ffca05189..9a367af2fa 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -188,13 +188,13 @@ static void riscv_load_initrd
=f103 stm32f1-soc.density=medium
(alias stm32-nucleo-f103rb)
- stm32f1-soc.family=f103 stm32f1-soc.density=high
- stm32f1-soc.family=f103 stm32f1-soc.density=xl
@Alistair: Would such modification make also sense regarding stm32f2 and
stm32f4 families?
Thanks,
--
Alexandre
OpenPGP_signature
Description: OpenPGP digital signature
On Thu, Apr 20, 2023 at 1:31 AM Alistair Francis wrote:
>
> On Wed, Apr 19, 2023 at 8:48 PM Alexandre Ghiti
> wrote:
> >
> > As per the privileged specification, in 64-bit, if any of the pte reserved
> > bits 60-54 is set an exception should be triggered, and the sam
Signed-off-by: Alexandre Ghiti
Reviewed-by: Alistair Francis
---
Changes in v3:
- Rebase on top of https://github.com/alistair23/qemu/tree/riscv-to-apply.next
Changes in v2:
- Handle napot and pbmt exception
target/riscv/cpu_bits.h | 1 +
target/riscv/cpu_helper.c | 15 +++
2 fil
ned-off-by: Alexandre Ghiti
---
target/riscv/cpu_bits.h | 1 +
target/riscv/cpu_helper.c | 15 +++
2 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index fca7ef0cef..8d9ba2ce11 100644
--- a/target/riscv/cpu_bits.h
+++ b/ta
Hi Alistair,
Sorry for the late reply, I was on PTO.
On Tue, Apr 18, 2023 at 4:22 AM Alistair Francis wrote:
>
> On Mon, Apr 17, 2023 at 8:47 PM Andrea Parri wrote:
> >
> > Hi Alistair,
> >
> > > > @@ -936,6 +936,11 @@ restart:
> > > > return TRANSLATE_FAIL;
> > > > }
> >
As per the specification, in 64-bit, if any of the pte reserved bits 60-54
is set, an exception should be triggered (see 4.4.1, "Addressing and Memory
Protection"), so implement this behaviour in the address translation process.
Reported-by: Andrea Parri
Signed-off-by: Alexa
hat could support FSMC or have more than 8KB of on-chip SRAM.
However, could it be a good idea to implement a generic STM32F100xx
machine in QEMU that is "high-density" by default and that could be
configured using command line options ? This could cover a wide range of
cases with a single machine.
Thanks,
--
Alexandre
OpenPGP_signature
Description: OpenPGP digital signature
gt;
> > v4:
> > - Use custom boolean properties instead of OnOffAuto properties, based
> > on ARMVQMap, as suggested by Andrew
> >
> > v3:
> > - Free sv_name as pointed by Bin
> > - Replace satp-mode with boolean properties as suggested by Andrew
> > - Removed
The 'mmu-type' should reflect what the hardware is capable of so use the
new satp_mode field in RISCVCPUConfig to do that.
Signed-off-by: Alexandre Ghiti
Reviewed-by: Andrew Jones
Reviewed-by: Alistair Francis
Reviewed-by: Bin Meng
Reviewed-by: Frank Chang
---
hw/riscv/v
r may select
- the user's selection then constrains what's available to the guest
OS.
Signed-off-by: Alexandre Ghiti
Reviewed-by: Andrew Jones
Reviewed-by: Bin Meng
Reviewed-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/r
cpu rv64,sv48=on,sv48=off # Linux will boot using sv39 scheme
Co-Developed-by: Ludovic Henry
Signed-off-by: Ludovic Henry
Signed-off-by: Alexandre Ghiti
Reviewed-by: Andrew Jones
Reviewed-by: Bin Meng
Acked-by: Alistair Francis
Reviewed-by: Frank Chang
---
target/riscv/cpu.c | 214 ++
This array is actually used as a boolean so swap its current char type
to a boolean and at the same time, change the type of validate_vm to
bool since it returns valid_vm_1_10_[32|64].
Suggested-by: Andrew Jones
Signed-off-by: Alexandre Ghiti
Reviewed-by: Andrew Jones
Reviewed-by: Alistair
One can extract the DeviceState pointer from the Object pointer, so pass
the Object for future commits to access other fields of Object.
No functional changes intended.
Signed-off-by: Alexandre Ghiti
Reviewed-by: Alistair Francis
Reviewed-by: Frank Chang
Reviewed-by: Andrew Jones
Reviewed-by
uggested by Alistair
- Add RB from Atish
- Fixed checkpatch issues missed in v1
- Replaced Ludovic email address with the rivos one
Alexandre Ghiti (5):
riscv: Pass Object to register_cpu_props instead of DeviceState
riscv: Change type of valid_vm_1_10_[32|64] to bool
riscv: Allow user to set t
at I believe you can choose to fix in-tree if you want to.
>
> Update: patch 1 is not applicable anymore due to changes in current master.
> All
> other patches have conflicts as well.
>
> I guess it's easier to Alexandre to rebase and re-send it when possible.
> Frank&
The 'mmu-type' should reflect what the hardware is capable of so use the
new satp_mode field in RISCVCPUConfig to do that.
Signed-off-by: Alexandre Ghiti
Reviewed-by: Andrew Jones
Reviewed-by: Alistair Francis
Reviewed-by: Bin Meng
Reviewed-by: Frank Chang
---
hw/riscv/v
r may select
- the user's selection then constrains what's available to the guest
OS.
Signed-off-by: Alexandre Ghiti
Reviewed-by: Andrew Jones
Reviewed-by: Bin Meng
---
target/riscv/cpu.c | 91 +-
target/riscv/cpu.h | 8 +++-
2 files changed
cpu rv64,sv48=on,sv48=off # Linux will boot using sv39 scheme
Co-Developed-by: Ludovic Henry
Signed-off-by: Ludovic Henry
Signed-off-by: Alexandre Ghiti
Reviewed-by: Andrew Jones
Reviewed-by: Bin Meng
Acked-by: Alistair Francis
---
target/riscv/cpu.c | 215 +++
This array is actually used as a boolean so swap its current char type
to a boolean and at the same time, change the type of validate_vm to
bool since it returns valid_vm_1_10_[32|64].
Suggested-by: Andrew Jones
Signed-off-by: Alexandre Ghiti
Reviewed-by: Andrew Jones
Reviewed-by: Alistair
One can extract the DeviceState pointer from the Object pointer, so pass
the Object for future commits to access other fields of Object.
No functional changes intended.
Signed-off-by: Alexandre Ghiti
Reviewed-by: Alistair Francis
Reviewed-by: Frank Chang
Reviewed-by: Andrew Jones
Reviewed-by
from Atish as the patch considerably changed
v2:
- Use error_setg + return as suggested by Alistair
- Add RB from Atish
- Fixed checkpatch issues missed in v1
- Replaced Ludovic email address with the rivos one
Alexandre Ghiti (5):
riscv: Pass Object to register_cpu_props instead of DeviceSta
Hi Frank,
On Wed, Feb 1, 2023 at 4:49 PM Frank Chang wrote:
>
> On Tue, Jan 31, 2023 at 10:36 PM Alexandre Ghiti
> wrote:
>>
>> Currently, the max satp mode is set with the only constraint that it must be
>> implemented in QEMU, i.e. set in valid_vm_1_10_[32|64].
&g
On Mon, Jan 30, 2023 at 5:29 AM Bin Meng wrote:
>
> On Thu, Jan 26, 2023 at 12:24 AM Alexandre Ghiti
> wrote:
> >
> > Currently, the max satp mode is set with the only constraint that it must be
> > implemented in qemu, i.e. set in valid_vm_1_10_[32|64].
cpu rv64,sv48=on,sv48=off # Linux will boot using sv39 scheme
Co-Developed-by: Ludovic Henry
Signed-off-by: Ludovic Henry
Signed-off-by: Alexandre Ghiti
Reviewed-by: Andrew Jones
---
target/riscv/cpu.c | 207 +
target/riscv/cpu.h | 19 +
ta
On Wed, Jan 25, 2023 at 5:52 PM Andrew Jones wrote:
>
> On Wed, Jan 25, 2023 at 05:20:08PM +0100, Alexandre Ghiti wrote:
> > RISC-V specifies multiple sizes for addressable memory and Linux probes for
> > the machine's support at startup via the satp CSR register (done i
r may select
- the user's selection then constrains what's available to the guest
OS.
Signed-off-by: Alexandre Ghiti
Reviewed-by: Andrew Jones
---
target/riscv/cpu.c | 79 +++---
target/riscv/cpu.h | 8 +++--
2 files changed, 60 insertions(+
- Replace satp-mode with boolean properties as suggested by Andrew
- Removed RB from Atish as the patch considerably changed
v2:
- Use error_setg + return as suggested by Alistair
- Add RB from Atish
- Fixed checkpatch issues missed in v1
- Replaced Ludovic email address with the rivos one
Alexandre
One can extract the DeviceState pointer from the Object pointer, so pass
the Object for future commits to access other fields of Object.
No functional changes intended.
Signed-off-by: Alexandre Ghiti
Reviewed-by: Alistair Francis
Reviewed-by: Frank Chang
Reviewed-by: Andrew Jones
Reviewed-by
The 'mmu-type' should reflect what the hardware is capable of so use the
new satp_mode field in RISCVCPUConfig to do that.
Signed-off-by: Alexandre Ghiti
Reviewed-by: Andrew Jones
Reviewed-by: Alistair Francis
Reviewed-by: Bin Meng
---
hw/riscv/virt.c | 19 ++-
1 fi
This array is actually used as a boolean so swap its current char type
to a boolean and at the same time, change the type of validate_vm to
bool since it returns valid_vm_1_10_[32|64].
Suggested-by: Andrew Jones
Signed-off-by: Alexandre Ghiti
Reviewed-by: Andrew Jones
Reviewed-by: Alistair
Hi Bin,
On Mon, Jan 30, 2023 at 5:22 AM Bin Meng wrote:
>
> On Thu, Jan 26, 2023 at 12:23 AM Alexandre Ghiti
> wrote:
> >
> > RISC-V specifies multiple sizes for addressable memory and Linux probes for
> > the machine's support at startup vi
The 'mmu-type' should reflect what the hardware is capable of so use the
new satp_mode field in RISCVCPUConfig to do that.
Signed-off-by: Alexandre Ghiti
Reviewed-by: Andrew Jones
Reviewed-by: Alistair Francis
---
hw/riscv/virt.c | 19 ++-
1 file changed, 10 insert
r may select
- the user's selection then constrains what's available to the guest
OS.
Signed-off-by: Alexandre Ghiti
Reviewed-by: Andrew Jones
---
target/riscv/cpu.c | 74 +++---
target/riscv/cpu.h | 8 +++--
2 files changed, 56 insertions(+
cpu rv64,sv48=on,sv48=off # Linux will boot using sv39 scheme
Co-Developed-by: Ludovic Henry
Signed-off-by: Ludovic Henry
Signed-off-by: Alexandre Ghiti
---
target/riscv/cpu.c | 206 +
target/riscv/cpu.h | 19 +
target/riscv/csr.c | 12 ++-
3
This array is actually used as a boolean so swap its current char type
to a boolean and at the same time, change the type of validate_vm to
bool since it returns valid_vm_1_10_[32|64].
Suggested-by: Andrew Jones
Signed-off-by: Alexandre Ghiti
Reviewed-by: Andrew Jones
Reviewed-by: Alistair
One can extract the DeviceState pointer from the Object pointer, so pass
the Object for future commits to access other fields of Object.
No functional changes intended.
Signed-off-by: Alexandre Ghiti
Reviewed-by: Alistair Francis
Reviewed-by: Frank Chang
Reviewed-by: Andrew Jones
---
target
rivos one
Alexandre Ghiti (5):
riscv: Pass Object to register_cpu_props instead of DeviceState
riscv: Change type of valid_vm_1_10_[32|64] to bool
riscv: Allow user to set the satp mode
riscv: Introduce satp mode hw capabilities
riscv: Correctly set the device-tree entry 'mmu-type&
On Wed, Jan 25, 2023 at 1:01 PM Andrew Jones wrote:
>
> On Wed, Jan 25, 2023 at 09:41:05AM +0100, Alexandre Ghiti wrote:
> > RISC-V specifies multiple sizes for addressable memory and Linux probes for
> > the machine's support at startup via the satp CSR register (done i
The 'mmu-type' should reflect what the hardware is capable of so use the
new satp_mode field in RISCVCPUConfig to do that.
Signed-off-by: Alexandre Ghiti
Reviewed-by: Andrew Jones
Reviewed-by: Alistair Francis
---
hw/riscv/virt.c | 19 ++-
1 file changed, 10 insert
r may select
- the user's selection then constrains what's available to the guest
OS.
Signed-off-by: Alexandre Ghiti
---
target/riscv/cpu.c | 74 +++---
target/riscv/cpu.h | 8 +++--
2 files changed, 56 insertions(+), 26 deletions(-)
diff --git
cpu rv64,sv48=on,sv48=off # Linux will boot using sv39 scheme
Co-Developed-by: Ludovic Henry
Signed-off-by: Ludovic Henry
Signed-off-by: Alexandre Ghiti
---
target/riscv/cpu.c | 207 +
target/riscv/cpu.h | 19 +
target/riscv/csr.c | 12 ++-
3
This array is actually used as a boolean so swap its current char type
to a boolean and at the same time, change the type of validate_vm to
bool since it returns valid_vm_1_10_[32|64].
Suggested-by: Andrew Jones
Signed-off-by: Alexandre Ghiti
Reviewed-by: Andrew Jones
Reviewed-by: Alistair
One can extract the DeviceState pointer from the Object pointer, so pass
the Object for future commits to access other fields of Object.
No functional changes intended.
Signed-off-by: Alexandre Ghiti
Reviewed-by: Alistair Francis
Reviewed-by: Frank Chang
Reviewed-by: Andrew Jones
---
target
as suggested by Andrew
- Removed RB from Atish as the patch considerably changed
v2:
- Use error_setg + return as suggested by Alistair
- Add RB from Atish
- Fixed checkpatch issues missed in v1
- Replaced Ludovic email address with the rivos one
Alexandre Ghiti (5):
riscv: Pass Object to
On Mon, Jan 23, 2023 at 2:51 PM Andrew Jones wrote:
>
> On Mon, Jan 23, 2023 at 10:03:24AM +0100, Alexandre Ghiti wrote:
> > Currently, the max satp mode is set with the only constraint that it must be
> > implemented in qemu, i.e. set in valid_vm_1_10_[32|64].
> >
> &g
On Mon, Jan 23, 2023 at 2:31 PM Andrew Jones wrote:
>
> On Mon, Jan 23, 2023 at 12:15:08PM +0100, Alexandre Ghiti wrote:
> > On Mon, Jan 23, 2023 at 11:51 AM Andrew Jones
> > wrote:
> > >
> > > On Mon, Jan 23, 2023 at 10:03:24AM +0100, Alexandre Ghiti wrote:
On Mon, Jan 23, 2023 at 11:51 AM Andrew Jones wrote:
>
> On Mon, Jan 23, 2023 at 10:03:24AM +0100, Alexandre Ghiti wrote:
> > Currently, the max satp mode is set with the only constraint that it must be
> > implemented in qemu, i.e. set in valid_vm_1_10_[32|64].
> >
>
On Mon, Jan 23, 2023 at 11:29 AM Andrew Jones wrote:
>
> On Mon, Jan 23, 2023 at 10:03:22AM +0100, Alexandre Ghiti wrote:
> ...
> > +/* Sets the satp mode to the max supported */
> > +static void set_satp_mode_default(RISCVCPU *cpu, bool is_32_bit)
> > +{
>
> ni
On Mon, Jan 23, 2023 at 11:14 AM Andrew Jones wrote:
>
> On Mon, Jan 23, 2023 at 10:03:22AM +0100, Alexandre Ghiti wrote:
> > RISC-V specifies multiple sizes for addressable memory and Linux probes for
> > the machine's support at startup via the satp CSR register (done i
Hi Andrew,
On Mon, Jan 23, 2023 at 11:11 AM Andrew Jones wrote:
>
> On Mon, Jan 23, 2023 at 10:03:22AM +0100, Alexandre Ghiti wrote:
> > RISC-V specifies multiple sizes for addressable memory and Linux probes for
> > the machine's support at startup via the sat
Hi Alistair,
On Tue, Jan 24, 2023 at 1:41 AM Alistair Francis wrote:
>
> On Mon, Jan 23, 2023 at 7:09 PM Alexandre Ghiti
> wrote:
> >
> > Currently, the max satp mode is set with the only constraint that it must be
> > implemented in qemu, i.e. set in valid_vm_1
On Mon, Jan 23, 2023 at 11:51 AM Andrew Jones wrote:
>
> On Mon, Jan 23, 2023 at 10:03:24AM +0100, Alexandre Ghiti wrote:
> > Currently, the max satp mode is set with the only constraint that it must be
> > implemented in qemu, i.e. set in valid_vm_1_10_[32|64].
> >
>
One can extract the DeviceState pointer from the Object pointer, so pass
the Object for future commits to access other fields of Object.
No functional changes intended.
Reviewed-by: Alistair Francis
Reviewed-by: Frank Chang
Reviewed-by: Andrew Jones
Signed-off-by: Alexandre Ghiti
---
target
ty
Signed-off-by: Alexandre Ghiti
---
target/riscv/cpu.c | 78 +++---
target/riscv/cpu.h | 8 +++--
2 files changed, 59 insertions(+), 27 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index e409e6ab64..19a37fee2b 100644
--- a/targ
The 'mmu-type' should reflect what the hardware is capable of so use the
new satp_mode field in RISCVCPUConfig to do that.
Signed-off-by: Alexandre Ghiti
---
hw/riscv/virt.c | 19 ++-
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/hw/riscv/virt.c
will boot using sv48 scheme
And contradictory configurations:
-cpu rv64,sv48=on,sv48=off # Linux will boot using sv39 scheme
In addition, we now correctly set the device-tree entry 'mmu-type' using
those new properties.
Co-Developed-by: Ludovic Henry
S
This array is actually used as a boolean so swap its current char type
to a boolean and at the same time, change the type of validate_vm to
bool since it returns valid_vm_1_10_[32|64].
Signed-off-by: Alexandre Ghiti
---
target/riscv/csr.c | 21 +++--
1 file changed, 11
-mode with boolean properties as suggested by Andrew
- Removed RB from Atish as the patch considerably changed
v2:
- Use error_setg + return as suggested by Alistair
- Add RB from Atish
- Fixed checkpatch issues missed in v1
- Replaced Ludovic email address with the rivos one
Alexandre Ghiti (5
On Fri, Jan 20, 2023 at 10:53 AM Andrew Jones wrote:
>
> On Fri, Jan 20, 2023 at 09:46:05AM +1000, Alistair Francis wrote:
> > On Thu, Jan 19, 2023 at 11:00 PM Alexandre Ghiti
> > wrote:
> > >
> > > Hi Alistair, Andrew,
> > >
> > > On Thu,
> > wrote:
> > > >
> > > > On Fri, Jan 13, 2023 at 11:34:53AM +0100, Alexandre Ghiti wrote:
> > ...
> > > > > +
> > > > > +/* Get rid of 32-bit/64-bit incompatibility */
> > > > > +for (int i = 0; i < 16; ++i)
Hey Andrew,
On Tue, Jan 17, 2023 at 5:31 PM Andrew Jones wrote:
>
> On Fri, Jan 13, 2023 at 11:34:53AM +0100, Alexandre Ghiti wrote:
> > RISC-V specifies multiple sizes for addressable memory and Linux probes for
> > the machine's support at startup via the sat
x will boot using sv48 scheme
-cpu rv64,sv32=on,sv32=off # Linux will boot using sv57 scheme (the default)
In addition, we now correctly set the device-tree entry 'mmu-type' using
those new properties.
Co-Developed-by: Ludovic Henry
Signed-off-by: Ludovic Henry
Si
One can extract the DeviceState pointer from the Object pointer, so pass
the Object for future commits to access other fields of Object.
No functional changes intended.
Signed-off-by: Alexandre Ghiti
---
target/riscv/cpu.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions
with boolean properties as suggested by Andrew
- Removed RB from Atish as the patch considerably changed
v2:
- Use error_setg + return as suggested by Alistair
- Add RB from Atish
- Fixed checkpatch issues missed in v1
- Replaced Ludovic email address with the rivos one
Alexandre Ghiti (2):
riscv
Hey Andrew,
Sorry about the response delay, I was traveling.
On Fri, Jan 6, 2023 at 4:30 PM Andrew Jones wrote:
>
> On Mon, Dec 12, 2022 at 11:22:50AM +0100, Alexandre Ghiti wrote:
> > RISC-V specifies multiple sizes for addressable memory and Linux probes for
> > the ma
On Fri, Dec 16, 2022 at 2:03 PM Alexandre Ghiti wrote:
>
> Hi Frank,
>
> On Fri, Dec 16, 2022 at 10:32 AM Frank Chang wrote:
> >
> > Hi Alexandre,
> >
> > Thanks for the contribution. This is really helpful.
> >
> > It seems like if we want to sp
Hi Frank,
On Fri, Dec 16, 2022 at 10:32 AM Frank Chang wrote:
>
> Hi Alexandre,
>
> Thanks for the contribution. This is really helpful.
>
> It seems like if we want to specify the SATP mode for the "named" CPUs,
> we have to do, e.g.:
> cpu->cfg.satp_mod
type' using
those new properties.
Co-Developed-by: Ludovic Henry
Signed-off-by: Ludovic Henry
Signed-off-by: Alexandre Ghiti
---
v4:
- Use custom boolean properties instead of OnOffAuto properties, based
on ARMVQMap, as suggested by Andrew
v3:
- Free sv_name as pointed by Bin
- R
Hi Andrew,
On Thu, Dec 1, 2022 at 3:47 PM Andrew Jones wrote:
> On Thu, Dec 01, 2022 at 10:36:23AM +0100, Alexandre Ghiti wrote:
> > RISC-V specifies multiple sizes for addressable memory and Linux probes
> for
> > the machine's support at startup via the sat
type' using
those new properties.
Co-Developed-by: Ludovic Henry
Signed-off-by: Ludovic Henry
Signed-off-by: Alexandre Ghiti
---
v3:
- Free sv_name as pointed by Bin
- Replace satp-mode with boolean properties as suggested by Andrew
- Removed RB from Atish as the patch considerably changed
e now correctly set the device-tree entry 'mmu-type' using
this new satp_mode property.
Reviewed-by: Atish Patra
Co-Developed-by: Ludovic Henry
Signed-off-by: Ludovic Henry
Signed-off-by: Alexandre Ghiti
---
v2:
- Use error_setg + return as suggested by Alistair
- Add RB from Atish
e now correctly set the device-tree entry 'mmu-type' using
this new satp_mode property.
Co-Developed-by: Ludovic Henry
Signed-off-by: Ludovic Henry
Signed-off-by: Alexandre Ghiti
---
hw/riscv/virt.c| 15 ++-
target/riscv/cpu.c | 45 ++
sndio is the native API used by OpenBSD, although it has been ported to
other *BSD's and Linux (packages for Ubuntu, Debian, Void, Arch, etc.).
Signed-off-by: Brad Smith
Signed-off-by: Alexandre Ratchov
---
References to the previous patch versions and related discussions are
here:
: Alexandre Iooss
--
Alexandre
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sndio is the native API used by OpenBSD, although it has been ported to
other *BSD's and Linux (packages for Ubuntu, Debian, Void, Arch, etc.).
Signed-off-by: Brad Smith
Signed-off-by: Alexandre Ratchov
---
Thank you for the reviews and all the comments. Here's a second diff
wi
-devel/2020-03/msg08741.html
https://lists.gnu.org/archive/html/qemu-devel/2021-04/msg04588.html
Thanks,
-- Alexandre
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On 8/14/21 12:11 PM, Peter Maydell wrote:
On Sat, 14 Aug 2021 at 10:20, Alexandre IOOSS wrote:
On 8/12/21 11:33 AM, Peter Maydell wrote:
Instead of passing the MSF2 SoC an integer property specifying the
CPU clock rate, pass it a Clock instead. This lets us wire that
clock up to the
On 8/12/21 11:33 AM, Peter Maydell wrote:
Fix the code style issues in the Stellaris general purpose timer
module code, so that when we move it to a different file in a
following patch checkpatch doesn't complain.
Signed-off-by: Peter Maydell
Reviewed-by: Alexandre Iooss
T
clock_new(OBJECT(machine), "m3clk");
+clock_set_hz(m3clk, 142 * 100);
Maybe something could be added in the commit message to say that M3_CLK
is changed from 100MHz to 142MHz. I do not know the SmartFusion2 but the
clocking guide seems to agree with 142MHz:
https://www.microsemi.com/document-portal/doc_download/132012-ug0449-smartfusion2-and-igloo2-clocking-resources-user-guide
+qdev_connect_clock_in(dev, "m3clk", m3clk);
qdev_prop_set_uint32(dev, "apb0div", 2);
qdev_prop_set_uint32(dev, "apb1div", 2);
Reviewed-by: Alexandre Iooss
Thanks,
-- Alexandre
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Maydell
Reviewed-by: Alexandre Iooss
-- Alexandre
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On 8/12/21 11:33 AM, Peter Maydell wrote:
Connect the sysclk to the armv7m object. This board's SoC does not
connect up the systick reference clock, so we don't need to connect a
refclk.
Signed-off-by: Peter Maydell
Reviewed-by: Alexandre Iooss
-- Alexandre
OpenPGP
ad put the
create/configure/realize parts before we create the armv7m object and
the mmio/irq connection parts afterwards.
Signed-off-by: Peter Maydell
Reviewed-by: Alexandre Iooss
-- Alexandre
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is is why we aren't wiring up a refclk (no need for one).
Signed-off-by: Peter Maydell
Reviewed-by: Alexandre Iooss
-- Alexandre
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where the
systick reference clock was running at 1MHz rather than 21MHz.
Signed-off-by: Peter Maydell
Reviewed-by: Alexandre Iooss
-- Alexandre
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