Re: [PATCH RFC 06/10] target/riscv: Define PMU event related structures

On 10.10.2024 02:09, Atish Patra wrote: Signed-off-by: Atish Patra --- target/riscv/cpu.h | 25 + 1 file changed, 25 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 2ac391a7cf74..53426710f73e 100644 --- a/target/riscv/cpu.h +++ b/target/ris

Re: [PATCH RFC 02/10] target/riscv: Introduce helper functions for pmu hashtable lookup

On 10.10.2024 02:09, Atish Patra wrote: The pmu implementation requires hashtable lookup operation sprinkled through the file. Add a helper function that allows to consolidate the implementation and extend it in the future easily. Signed-off-by: Atish Patra --- target/riscv/pmu.c | 56

Re: [PATCH RFC 05/10] target/riscv: Rename the PMU events

On 10.10.2024 02:09, Atish Patra wrote: The current PMU events are defined by SBI PMU specification. As there is no standard event encoding scheme, Virt machine chooses to use the SBI PMU encoding. A platform may choose to implement a different event encoding scheme completely. Rename the ev

[PATCH v9] target/riscv/kvm/kvm-cpu.c: kvm_riscv_handle_sbi() fail with vendor-specific SBI

igned-off-by: Alexei Filippov Fixes: 4eb47125 ("target/riscv: Handle KVM_EXIT_RISCV_SBI exit") --- target/riscv/kvm/kvm-cpu.c | 10 ++ target/riscv/sbi_ecall_interface.h | 12 2 files changed, 18 insertions(+), 4 deletions(-) diff --git a/target/riscv/kvm/kvm

[RFC PATCH 2/2] hw/riscv/sifive_u.c: Add initial HPM support

combination are working, but right counting for them should be implemented separatly. Signed-off-by: Alexei Filippov --- hw/misc/meson.build| 1 + hw/misc/sifive_u_pmu.c | 384 + hw/riscv/sifive_u.c| 14 ++ include/hw/misc/sifive_u_pmu.h

[RFC PATCH 0/2] target/riscv: Add support for machine specific pmu's events

ithm for different events. There are also no tests, but if you have any suggestions about where I need to look to implement them, please point me to. == Changes since original patch == - Rebased to current master [1] https://lore.kernel.org/all/20240625144643.34733-1-alexei.filip...@syntacore

[RFC PATCH 1/2] target/riscv: Add support for machine specific pmu's events

Was added call backs for machine specific pmu events. Simplify monitor functions by adding new hash table, which going to map counter number and event index. Was added read/write callbacks which going to simplify support for events, which expected to have different behavior. Signed-off-by: Alexei

[PATCH] target/riscv: Add support for machine specific pmu's events

Was added call backs for machine specific pmu events. Simplify monitor functions by adding new hash table, which going to map counter number and event index. Was added read/write callbacks which going to simplify support for events, which expected to have different behavior. Signed-off-by: Alexei

[PATCH v8] target/riscv/kvm/kvm-cpu.c: kvm_riscv_handle_sbi() fail with vendor-specific SBI

igned-off-by: Alexei Filippov Fixes: 4eb47125 ("target/riscv: Handle KVM_EXIT_RISCV_SBI exit") --- Changes since v7: - Fix error handling according to Andrew Jones suggestion. target/riscv/kvm/kvm-cpu.c | 9 + target/riscv/sbi_ecall_interface.h | 12 ++

[PATCH v2] target/riscv: Add support for machine specific pmu's events

Was added call backs for machine specific pmu events. Simplify monitor functions by adding new hash table, which going to map counter number and event index. Was added read/write callbacks which going to simplify support for events, which expected to have different behavior. Signed-off-by: Alexei

[PATCH v7] target/riscv/kvm/kvm-cpu.c: kvm_riscv_handle_sbi() fail with vendor-specific SBI

igned-off-by: Alexei Filippov Fixes: 4eb47125 ("target/riscv: Handle KVM_EXIT_RISCV_SBI exit") --- Changes since v6: - Add appropriate commit message. - Fix error handling according to Andrew Jones suggestion. target/riscv/kvm/kvm-cpu.c | 11

[PATCH v2 1/2] target/riscv: prioritize pmp errors in raise_mmu_exception()

From: Daniel Henrique Barboza raise_mmu_exception(), as is today, is prioritizing guest page faults by checking first if virt_enabled && !first_stage, and then considering the regular inst/load/store faults. There's no mention in the spec about guest page fault being a higher priority that PMP f

[PATCH v2 2/2] target/riscv: do not set mtval2 for non guest-page faults

address that faulted, shifted by 2 bits. *For other traps, mtval2 is set to zero...* Signed-off-by: Alexei Filippov Reviewed-by: Daniel Henrique Barboza --- Changes since v1: -Added Reviewed-by tag. target/riscv/cpu_helper.c | 12 ++-- 1 file changed, 6 insertions(+), 6 delet

[PATCH v6] target/riscv/kvm/kvm-cpu.c: kvm_riscv_handle_sbi() fail with vendor-specific SBI

kvm_riscv_handle_sbi() may return not supported return code to not trigger qemu abort with vendor-specific sbi. Add new error path to provide proper error in case of qemu_chr_fe_read_all() may not return sizeof(ch). Added SBI related return code's defines. Signed-off-by: Alexei Fil

[PATCH v5] target/riscv/kvm/kvm-cpu.c: kvm_riscv_handle_sbi() fail with vendor-specific sbi.

kvm_riscv_handle_sbi() may return not supported return code to not trigger qemu abort with vendor-specific sbi. Add new error path to provide proper error in case of qemu_chr_fe_read_all() may not return sizeof(ch). Added SBI related return code's defines. Signed-off-by: Alexei Fil

[PATCH v4] target/riscv/kvm/kvm-cpu.c: kvm_riscv_handle_sbi() fail with vendor-specific SBI

kvm_riscv_handle_sbi() may return not supported return code to not trigger qemu abort with vendor-specific sbi. Added SBI related return code's defines. Signed-off-by: Alexei Filippov Fixes: 4eb47125 ("target/riscv: Handle KVM_EXIT_RISCV_SBI exit") --- Changes since v3:

[PATCH 2/2] target/riscv: do not set mtval2 for non guest-page faults

address that faulted, shifted by 2 bits. *For other traps, mtval2 is set to zero...* Signed-off-by: Alexei Filippov --- target/riscv/cpu_helper.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 196166f8d

[PATCH 1/2] target/riscv: prioritize pmp errors in raise_mmu_exception()

From: Daniel Henrique Barboza raise_mmu_exception(), as is today, is prioritizing guest page faults by checking first if virt_enabled && !first_stage, and then considering the regular inst/load/store faults. There's no mention in the spec about guest page fault being a higher priority that PMP f

[PATCH] target/riscv/cpu_helper.c: fix wrong exception raise

physical address within a PMP region without read permissions raises a load access-fault exception. Signed-off-by: Alexei Filippov --- target/riscv/cpu_helper.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index

[PATCH v3] target/riscv/kvm/kvm-cpu.c: kvm_riscv_handle_sbi() fail with vendor-specific SBI

kvm_riscv_handle_sbi() may return not supported return code to not trigger qemu abort with vendor-specific sbi. Added SBI related return code's defines. Signed-off-by: Alexei Filippov Fixes: 4eb47125 ("target/riscv: Handle KVM_EXIT_RISCV_SBI exit") Reviewed-by: Daniel Henrique Ba

[PATCH] target/riscv/kvm/kvm-cpu.c: kvm_riscv_handle_sbi() fail with vendor-specific SBI

kvm_riscv_handle_sbi() may return not supported return code to not trigger qemu abort with vendor-specific sbi. Added SBI related return code's defines. Signed-off-by: Alexei Filippov --- target/riscv/kvm/kvm-cpu.c | 5 +++-- target/riscv/sbi_ecall_interface.h | 11 +

[PATCH v2] target/riscv/kvm/kvm-cpu.c: kvm_riscv_handle_sbi() fail with vendor-specific SBI

kvm_riscv_handle_sbi() may return not supported return code to not trigger qemu abort with vendor-specific sbi. Added SBI related return code's defines. Signed-off-by: Alexei Filippov Fixes: 4eb47125 ("target/riscv: Handle KVM_EXIT_RISCV_SBI exit") Reviewed-by: Daniel H